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Vaibbhav Taraate

PLD Based
Design
with VHDL
RTL Design, Synthesis and
Implementation
PLD Based Design with VHDL
Vaibbhav Taraate

PLD Based Design

with VHDL
RTL Design, Synthesis and Implementation

123
Vaibbhav Taraate
Pune, Maharashtra
India

ISBN 978-981-10-3294-3 ISBN 978-981-10-3296-7 (eBook)

DOI 10.1007/978-981-10-3296-7
Library of Congress Control Number: 2016958476

© Springer Nature Singapore Pte Ltd. 2017

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part
of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission
or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar
methodology now known or hereafter developed.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publication does not imply, even in the absence of a specific statement, that such names are exempt from
the relevant protective laws and regulations and therefore free for general use.
The publisher, the authors and the editors are safe to assume that the advice and information in this
book are believed to be true and accurate at the date of publication. Neither the publisher nor the
authors or the editors give a warranty, express or implied, with respect to the material contained herein or
for any errors or omissions that may have been made.

Printed on acid-free paper

This Springer imprint is published by Springer Nature

The registered company is Springer Nature Singapore Pte Ltd.
The registered company address is: 152 Beach Road, #22-06/08 Gateway East, Singapore 189721, Singapore
Dedicated to my Spiritual Guru, my Teachers
and to my Parents
Preface

In the present decade, the complexity of the ASIC and FPGA design has grown
rapidly. Due to that there is need of the intelligent and complex devices, and hence
the FPGA prototyping area has evolved during this decade.
Major FPGA vendors such as XILINX and Altera (Intel FPGA) have come up
with the complex FPGAs which are required for design and realization of the
system on chip (SOC). During this decade, the era of miniaturization has lot many
challenges. The major challenges are to design and deliver the intelligent products
for lesser cost, high speed, less area, and less power.
Under such circumstances for the idea or product feasibility, the complex
FPGAs are used and the complexity of FPGA architecture has grown in the past
decade. Even the multiple FPGA designs are used to validate the complex SOCs.
For easy understanding of the FPGA designs and ASIC prototyping using FPGAs,
this book is organized. This book covers the design for the lower gate count to
higher gate count designs. Even this book is written in such a way that it can give
information about the VHDL, synthesis, FPGAs, and ASIC prototyping.
Chapter 1 of this book discusses the evolution of the logic design, need of HDL,
and differences between the VHDL and other higher level languages, and even this
chapter describes about the different modeling styles using VHDL.
Chapter 2 of this book describes about the basic combinational elements and
their use in the design. Even this chapter describes how to write synthesizable RTL
using the VHDL constructs. This chapter is useful for the beginners to understand
about the basic VHDL constructs and the synthesis outcome of few low gate count
designs.
Chapter 3 discusses the key VHDL constructs such as processes, signals, and
variables, when else, with select, if-then-else and case. Even this chapter covers the
practical scenarios and use of these constructs.
Chapter 4 describes the how to write an efficient RTL using VHDL. Even this
chapter covers the design for the combinational logic such as multibit adders,
multiplexers, decoders, and encoders. The synthesis for the RTL design using
VHDL is covered with the detailed explanation and practical scenarios.

vii
viii Preface

Chapter 5 covers the sequential design scenarios and the RTL using VHDL for
the latches and flip-flops. Even this chapter covers the BCD counters, binary
counters, gray counters, ring counters, Johnson counters and the RTL design and
synthesis for the same. This chapter has information about the timing parameters
and timing analysis for the synchronous sequential designs. This chapter even gives
information about the basics of asynchronous and multiple clock domain designs
and the issues like metastability and how to overcome those during design cycle.
Chapter 6 covers the PLD-based designs and the detail practical-oriented
examples and scenarios for the design using SPLDs, CPLDs, and FPGAs. This
chapter covers the XILINX and ALTERA (Intel) FPGA architectures and their use
in the design and prototyping. The vendor-specific design guidelines are covered in
this chapter.
Chapter 7 covers the VHDL constructs and the use of VHDL for the verification
and simulation of the design. This chapter is useful to understand the test benches
and how to simulate the design for early detection of bugs. Even this chapter covers
the practical issues in the design verification using practical scenarios and
examples.
Chapter 8 covers the design and coding guidelines for the PLD-based designs.
How to use the VHDL for the efficient design is explained in detail with the
practical scenarios and synthesizable VHDL constructs. This chapter covers tech-
niques such as grouping, parallel and concurrent logic, logic duplications, and
resource sharing. Even this chapter covers the low-power basics as clock gating and
clock enabling.
Chapter 9 covers the complex designs such as multipliers, barrel shifters, arbiters
and the processor logic as ALU, and the other basic protocols. This chapter is useful
to understand the synthesis issues in the complex designs and how to overcome
those using the techniques described in Chap. 7.
Chapter 10 discusses the finite state machines (FSMs) using the VHDL. The
Moore and Mealy machines and their use to code the sequence detectors and
counters are described in this chapter. Even the FSM synthesis issues and how to
improve the design performance are discussed with the practical scenarios. Even
this chapter covers the FSM synthesis guidelines and FSM optimization techniques
used while prototyping ASICs using the complex FPGAs.
Chapter 11 covers VIVADO based design flow and case study using VIVADO
for the design implementation. The case study of FIFO is covered in this chapter.
Chapters 1–11 are organized in such a way that it covers the small gate count
RTL using VHDL to the complex design using VHDL with the meaningful sce-
narios. This book is useful for the beginners, RTL design engineers, and profes-
sionals. I hope that this book can give you the excellent understanding of VHDL
constructs and use of VHDL in ASIC prototyping!

Pune, India Vaibbhav Taraate

Acknowledgements

This book is possible due to direct and indirect contribution of many people. While
writing this book, I got the great help from many people. I am thankful to all my
students to whom I have taught this subject over past almost 15 years.
I am thankful to my wife Somi for her sacrifices during the period of writing this
book. Although Somi was hospitalized for three months after returning from the
hospital, she has helped me in finding the grammatical mistakes and even corrected
initial proofs of this book.
I am very much thankful to my dearest friend Ishita Thaker (Ish) for her indirect
help and motivation while writing this book.
I am very much thankful to dearest Kaju for the great wishes and prayers.
Especially I am thankful to my Son Siddesh and my daughter Kajal for
understanding me during this period and for helping me with few suggestions for
the representation of diagrams.
This book would not have been possible without the help of Swati Meherishi and
Aparajita Singh at Springer.
I am thankful to all the Springer staff, especially Praveen V for the review of this
book and for the easy-to-understand outline of this book.
Finally, in advance, I am thankful to all the readers and buyers for buying and
enjoying this book!

ix
Contents

1 Introduction to HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 History of HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 System and Logic Design Abstractions . . . . . . . . . . . . . . . . . . . . 3
1.3 ASIC Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Integrated Circuit Design and Methodologies . . . . . . . . . . . . . . . 8
1.4.1 RTL Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.2 Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.3 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.4 Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Programming Language Verses HDL . . . . . . . . . . . . . . . . . . . . . 11
1.5.1 VHDL Evolution and Popularity . . . . . . . . . . . . . . . . . . 11
1.6 Design Description Using VHDL . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.1 Structural Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.2 Behavior Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6.3 Synthesizable RTL Design . . . . . . . . . . . . . . . . . . . . . . 17
1.7 Key VHDL Highlights and Constructs . . . . . . . . . . . . . . . . . . . . 19
1.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2 Basic Logic Circuits and VHDL Description . . . . . . . . . . . . . . . . . . . 23
2.1 Introduction to Combinational Logic . . . . . . . . . . . . . . . . . . . . . 24
2.2 Logic Gates and Synthesizable RTL Using VHDL . . . . . . . . . . . 25
2.2.1 NOT or Invert Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.2 Two-Input OR Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.3 Two-Input NOR Logic . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.4 Two-Input AND Logic . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.5 Two-Input NAND Logic . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.6 Two-Input XOR Logic . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.7 Two-Input XNOR Logic . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.8 Tri-State Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

xi
xii Contents

2.3 Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.3.1 Half Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.3.2 Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.4 Code Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.4.1 Binary-to-Gray Code Converter . . . . . . . . . . . . . . . . . . . 44
2.4.2 Gray-to-Binary Code Converter . . . . . . . . . . . . . . . . . . . 46
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3 VHDL and Key Important Constructs . . . . . . . . . . . . . . . . . . . . . . . 49
3.1 VHDL Design Paradigm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2 Multiple Architectures and Configuration . . . . . . . . . . . . . . . . . . 53
3.2.1 Multiple Architecture and Configuration . . . . . . . . . . . . 54
3.3 Objects and Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.1 Scalar Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.2 Composite Data Types . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.3 Data Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.4 Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4 Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.1 Signal Assignments Example. . . . . . . . . . . . . . . . . . . . . 61
3.5 Variable Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.5.1 Variable Assignments Example . . . . . . . . . . . . . . . . . . . 63
3.6 Concurrent Constructs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.6.1 When Else . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.6.2 With Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.6.3 Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.7 Sequential Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.7.1 If Then Else . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.7.2 Nested If Then Else . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.7.3 Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.8 Modeling Sequential Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.8.1 Four-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.8.2 Four-Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.9 Wait Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.9.1 Wait On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.9.2 Wait For . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.9.3 Wait Until . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.10 Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.10.1 Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.10.2 While Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.10.3 For Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.11 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Contents xiii

4 Combinational Logic Design Using VHDL Constructs . . . . . . . . . . . 87

4.1 Combinational Logic and Delays . . . . . . . . . . . . . . . . . . . . . . . . 88
4.1.1 Cascade Combinational Logic . . . . . . . . . . . . . . . . . . . . 89
4.1.2 Parallel Combinational Logic . . . . . . . . . . . . . . . . . . . . 90
4.2 Arithmetic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2.1 Multibit Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.2.2 Multibit Adder–Subtractor . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.3 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.2.4 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.3 Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.3.1 Binary-to-Excess-3 Code Converter . . . . . . . . . . . . . . . . 99
4.3.2 BCD-to-Seven-Segment Decoder . . . . . . . . . . . . . . . . . . 101
4.4 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4.1 Multiplexer as Universal Logic . . . . . . . . . . . . . . . . . . . 105
4.5 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.5.1 3 Line to 8 Decoder with Enable Using ‘Case’ . . . . . . . 110
4.5.2 2 Line to 4 Decoder with Enable Using ‘Case’ . . . . . . . 115
4.6 Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.6.1 Priority Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5 Sequential Logic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.1 Sequential Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.1.1 Metastability and Timing Parameters for the
Sequential Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2 D-Latches in the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.2.1 Positive Level Sensitive D-Latch . . . . . . . . . . . . . . . . . . 130
5.2.2 Negative Level Sensitive D-Latch . . . . . . . . . . . . . . . . . 132
5.2.3 Negative Level Sensitive D-Latch with Preset
and Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.2.4 Positive Level Sensitive D-Latch with Asynchronous
Preset and Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3 Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.3.1 Positive Edge-Triggered D Flip-Flop . . . . . . . . . . . . . . . 137
5.3.2 Negative Edge-Triggered D Flip-Flop . . . . . . . . . . . . . . 139
5.4 Synchronous and Asynchronous Reset . . . . . . . . . . . . . . . . . . . . 140
5.4.1 D Flip-Flop with Asynchronous Reset . . . . . . . . . . . . . . 140
5.4.2 D Flip-Flop with Synchronous Reset . . . . . . . . . . . . . . . 142
5.5 Sequential Circuit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.6 Synchronous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.6.1 Four-Bit Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.6.2 Four-Bit Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.6.3 BCD Up Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.6.4 BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.6.5 BCD Up–Down Counter . . . . . . . . . . . . . . . . . . . . . . . . 153
xiv Contents

5.7 Gray Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

5.8 Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.9 Johnson Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.10 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.10.1 Right and Left Shift Registers . . . . . . . . . . . . . . . . . . . . 163
5.10.2 Parallel Input, Parallel Output (PIPO)
Shift Register . . . . . . . . . . . . . . . . . . . . ............. 163
5.11 Asynchronous Designs . . . . . . . . . . . . . . . . . . . ............. 167
5.12 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. 167
6 Introduction to PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.1 History and Evolution of PLDs . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.2 Simple Programmable Logic Device (SPLD) . . . . . . . . . . . . . . . 172
6.2.1 Programmable Read-Only Memory (PROM) . . . . . . . . . 174
6.2.2 Programmable Array Logic (PAL) . . . . . . . . . . . . . . . . 175
6.2.3 Programmable Logic Array (PLA) . . . . . . . . . . . . . . . . 175
6.3 Complex Programmable Logic Devices . . . . . . . . . . . . . . . . . . . 178
6.4 Field-Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . 181
6.4.1 Concept of LUT and Combinational Logic
Realization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.4.2 VHDL Design and Realization Using CLB . . . . . . . . . . 183
6.4.3 IO Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.4.4 Block RAM (BRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.4.5 Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.4.6 DSP Blocks and Multipliers . . . . . . . . . . . . . . . . . . . . . 198
6.4.7 Routing Resources and IO Standards. . . . . . . . . . . . . . . 199
6.5 Practical Scenarios and Guidelines . . . . . . . . . . . . . . . . . . . . . . . 202
6.5.1 Reset Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.5.2 Asynchronous Versus Synchronous Designs . . . . . . . . . 206
6.5.3 Clocking Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7 Design and Simulation Using VHDL Constructs . . . . . . . . . . . . . . . . 211
7.1 Simulation Using VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.1.1 Testbench for 4:1 MUX . . . . . . . . . . . . . . . . . . . . . . . . 212
7.1.2 Testbench for 4-Bit Binary up Counter . . . . . . . . . . . . . 215
7.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.3 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
7.3.1 Package Use in Design . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.4 Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.4.1 Signal Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.4.2 Array Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.5 File Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.5.1 Use of Files in Design Simulation . . . . . . . . . . . . . . . . . 228
7.5.2 TEXTIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Contents xv

8 PLD-Based Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

8.1 Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.2 Use of Signals and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.3 Grouping in Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
8.4 Guidelines for Use of Tri-State Logic . . . . . . . . . . . . . . . . . . . . . 240
8.5 Arithmetic Resource Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
8.6 Logic Duplications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
8.7 Multiple Driver Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
8.8 Inferring Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8.9 Use of If Then Else Versus Case Statements . . . . . . . . . . . . . . . 255
8.10 Use of Pipelining in Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
8.11 Multiple Clock Domain and Data Passing . . . . . . . . . . . . . . . . . 262
8.12 Bidirectional IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
8.13 Gated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
8.14 Design with Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
8.15 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
9 Finite-State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
9.1 Introduction to FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
9.1.1 Moore Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
9.1.2 Mealy Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
9.2 FSM Encoding Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
9.3 How to Code Moore FSM Using VHDL? . . . . . . . . . . . . . . . . . 279
9.3.1 FSM Design Template for Moore Machine . . . . . . . . . . 281
9.4 How to Code Mealy FSM Using VHDL? . . . . . . . . . . . . . . . . . 281
9.4.1 FSM Design Template for Mealy Machine . . . . . . . . . . 283
9.5 FSM Examples and VHDL Coding . . . . . . . . . . . . . . . . . . . . . . 283
9.5.1 Binary Encoding FSM . . . . . . . . . . . . . . . . . . . . . . . . . . 286
9.5.2 Binary Counter FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
9.5.3 One-Hot Counter FSM . . . . . . . . . . . . . . . . . . . . . . . . . 289
9.6 Parity Logic Using Moore FSM . . . . . . . . . . . . . . . . . . . . . . . . . 289
9.6.1 Moore Machine: Three-Process Block FSM
for Parity Checking . . . . . . . . . . . . . . . . . . . . . . . . .... 292
9.7 Parity Logic Using Mealy FSM . . . . . . . . . . . . . . . . . . . . . .... 292
9.7.1 Mealy Machine: Two-Process Block FSM
for Parity Checking . . . . . . . . . . . . . . . . . . . . . . . . .... 298
9.7.2 Mealy Machine: Three-Process Block FSM
for Parity Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
9.8 Sequence Detector Mealy Machine . . . . . . . . . . . . . . . . . . . . . . . 303
9.9 One-Hot Encoding Sequence Detector: Moore Machine . . . . . . . 306
9.10 One-Hot Encoding Sequence Detector: Mealy Machine . . . . . . . 306
9.11 FSM Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9.12 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
xvi Contents

10 Synthesis Optimization Using VHDL . . . . . . . . . . . . . . . . . . . . . . . . . 313

10.1 FPGA Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
10.1.1 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
10.1.2 Design Simulation and Synthesis . . . . . . . . . . . . . . . . . . 315
10.1.3 Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 316
10.1.4 Device Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
10.2 Synthesis Optimization Techniques. . . . . . . . . . . . . . . . . . . . . . . 316
10.2.1 Resource Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.2.2 Common Factors and Subexpressions Used
for Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
10.2.3 Moving the Piece of Code . . . . . . . . . . . . . . . . . . . . . . . 320
10.2.4 Constant Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
10.2.5 Dead Zone Elimination . . . . . . . . . . . . . . . . . . . . . . . . . 322
10.2.6 Use of Parentheses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
10.2.7 Partitioning and Structuring the Design . . . . . . . . . . . . . 323
10.3 ALU Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.3.1 Processor Logic Unit and Design . . . . . . . . . . . . . . . . . 324
10.3.2 Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.3.3 Arithmetic and Logical Unit . . . . . . . . . . . . . . . . . . . . . 335
10.4 Barrel Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
10.5 Parity Checkers and Generators . . . . . . . . . . . . . . . . . . . . . . . . . 339
10.5.1 Parity Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
10.5.2 Parity Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
10.6 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
10.6.1 Single-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
10.6.2 Dual-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
10.7 Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
10.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
11 Design Implementation Using Xilinx Vivado . . . . . . . . . . . . . . . . . . . 369
11.1 Design Implementation Case_Study Using Xilinx Vivado . . . . . 370
11.1.1 Design Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
11.1.2 IO Planning and IO Constraints. . . . . . . . . . . . . . . . . . . 373
11.1.3 Functional Simulation of the Design . . . . . . . . . . . . . . . 375
11.1.4 Design Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.2 Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
11.2.1 Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.3 FPGA Board Bring-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.4 FIFO Design Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
11.4.1 Asynchronous FIFO Depth Calculations . . . . . . . . . . . . 383
11.4.2 FIFO Design Using VHDL . . . . . . . . . . . . . . . . . . . . . . 386
11.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Contents xvii

Appendix A: Key Differences VHDL 87 and VHDL 93 . . . . . . . . . . . . . . 395

Appendix B: Xilinx Spartan Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Appendix C: Altera (Intel FPGA) Cyclone IV Devices . . . . . . . . . . . . . . . 407
Appendix D: VHDL Design Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
About the Author

Vaibbhav Taraate is an entrepreneur and mentor at “Semiconductor Training

@ Rs. 1.” He holds a BE (electronics) degree from Shivaji University, Kolhapur, in
1995 and secured a gold medal for standing first in all engineering branches. He has
completed his M. Tech (aerospace control and guidance) in 1999 from IIT Bombay.
He has over 15 years of experience in semicustom ASIC and FPGA design, pri-
marily using HDL languages such as Verilog and VHDL. He has worked with few
multinational corporations as consultant, senior design engineer, and technical
manager. His areas of expertise include RTL design using VHDL, RTL design using
Verilog, complex FPGA-based design, low-power design, synthesis/optimization,
static timing analysis, system design using microprocessors, high-speed VLSI
designs, and architecture design of complex SOCs.

xix
Chapter 1
Introduction to HDL

VHDL RTL Design

“Imagination is very important than Knowledge.”
--- Albert Einstein
Functional
Design Constraints
Verification
The HDL design engineer should have the Knowledge
YES NO
Synthesis Coverage of hardware and should apply it to solve the practical
goals met?
problems with imagination.
Constraints
Met? Learn to understand and imagine description using
NO
YES efficient VHDL constructs!
Physical Design

Abstract This chapter discusses the digital logic design evolution and the basic
ASIC design flow. The chapter describes the necessity of ASIC SOC prototype.
The comparison of ASIC and FPGA implementation is described in this chapter.
The chapter even discusses the need of HDL and VHDL different modeling styles
using the small gate count example. This chapter is useful to the HDL beginners to
understand about the difference between high-level language and HDL modeling
styles.

Keywords ASIC FPGA HDL

Prototype C C++

Concurrent





Sequential ABEL

Data flow Logic capacity
RTL Simulation







Verification Implementation Structural model Data-flow model Behavior




model ASIC prototyping

© Springer Nature Singapore Pte Ltd. 2017 1

V. Taraate, PLD Based Design with VHDL,
DOI 10.1007/978-981-10-3296-7_1
2 1 Introduction to HDL

1.1 History of HDL

The invention of CMOS logic during 1963 has made integration of logic cells very
easy and it was predicted by Intel’s cofounder Gordon Moore that the density of the
logic cells for the same silicon area will get doubled for every 18–24 months. What
we call as Moore’s law!

How Moore’s prediction was right that experience engineers can get with the
complex VLSI-based ASIC chip designs. In the present decade, the chip area has
shrunk enough, and process technology node on which foundries are working is
14 nm and chip has billions of cells for small silicon die size. With the evolutions in
the design and manufacturing technologies, most of the designs are implemented
using Very-High-Speed Integrate Circuit Hardware Description Language
(VHSICHDL) or using Verilog. We are focusing on the VHDL as hardware
description language. The evolution in the EDA industry has opened up new effi-
cient pathways for the design engineers to complete the milestones in less time.
1.1 History of HDL 3

Table 1.1 Hardware description language and evolution

HDL Description Application Standard
AHDL Analog hardware description Open source and used for analog 1980
language verification
Verilog-AMS Verilog for analog and mixed Open standard and used for the mix Derived
signals of digital and analog simulation from IEEE
1364
VHDL-AMS VHDL for analog and mixed Standard language for both the IEEE
signals analog and digital mixed signal 1076.1-2007
simulations
ABEL Advanced Boolean Used for the PLD-based design None
expression language
System C The high-level abstraction It uses the C++ classes for higher IEEE
language for the hardware level behavioral and transaction-level 1666-2011
designs modeling(TLM) for describing
hardware at system level
System Superset of Verilog Used to address the system-level IEEE
Verilog design and verification 1800-2012
Verilog Widely used hardware Used for the design and verification IEEE
description language (HDL) of digital logic 1364-2005
VHDL Very-high-speed integrated Use for the design and verification of IEEE
circuit (HSIC) hardware digital logic 1076-2008
description language (HDL)

Table 1.1 describes the various hardware description languages (HDLs) and
their standard with the description.

1.2 System and Logic Design Abstractions

As shown in Fig. 1.1, most of the designs have various abstraction levels. The
design approach can be top-down or bottom-up. The implementation team takes
decision about the right approach depending on the design complexity and the

Functional Design

Architecture

Micro-architecture

RTL Design
Gate Level Design

Switch level Design

Bottom Up Top Down

Approach Approach

Fig. 1.1 Design abstractions

4 1 Introduction to HDL

availability of design resources. Most of the complex designs are using the
top-down approach instead of bottom-up approach.
The design is described as functional model initially, and the architecture and
microarchitecture of the design are described by understanding the functional
design specifications. Architecture design involves the estimation of the memory
processor logic and throughput with associative glue logic and functional design
requirements. Architecture design is in the form of functional blocks and represents
the functionality of design in the block diagram form.
The microarchitecture is a detailed representation of every architecture block,
and it describes the block and sub-block level details, interface and pin connections,
and hierarchical design details. The information about synchronous or asyn-
chronous designs and clock and reset trees is also described in the microarchitecture
document.
RTL stands for register transfer level. RTL design uses microarchitecture as
reference design document and can be efficiently coded using VHDL for the
required design functionality. The efficient design and coding guidelines at this
stage play an important role and efficient RTL can reduce the overall time
requirement during the implementation phase. The outcome of RTL design is
gate-level netlist. Gate-level netlist is output from the RTL design stage after
performing RTL synthesis and it is a representation of the functional design in the
form of combinational and sequential logic cells.
Finally, the switch-level design is the abstraction used at the layout to represent
the design in the form of CMOS switches—PMOS, NMOS.

1.3 ASIC Prototyping

ASIC prototyping is also called as FPGA prototyping or SOC prototyping. ASIC is

an application-specific integrated circuit, FPGA is field programmable gate array,
and SOC is system-on-a-chip. If we consider the past one decade, then due to
availability of high logic density FPGAs the ASIC prototyping using FPGA area
have has been evolved. The main goal is to validate the firmware, software, and
hardware of SOC using high-end available FPGAs. ASIC designs can be proto-
typed by using suitable FPGAs, and it reduces the delivery time, budget, and even
the product launch targets in the market. For million logic gate SOCs, the ASIC
prototyping using FPGA is used to design and prove the prototype and it reduces
the risk while manufacturing of ASICs.
1.3 ASIC Prototyping 5

As the process node has shrunk to 14 nm and even will shrink to less than 10
nm, the complexity of design, the design risk, and the development time has
increased. The main challenge for every organization is to develop the lower cost
products with improved design functionality in small silicon area. In such scenario,
the designers are facing the development and verification challenges. Under such
circumstances, the high-end FPGAs can be used to prototype the ASIC function-
ality and it reduces the overall risk. The verified and implemented design on
high-end FPGAs can be resynthesized using standard cell ASIC using the same
RTL, constraints, and scripts. There are many EDA tools available to port an FPGA
prototype on structured ASICs. This really reduces the overall risk in ASIC design
and saves money and time to market for the product.
Following are key advantages of ASIC prototyping using FPGAs
1. The shrinking process node and chip geometries involve the investment in
millions of dollars in the early stage of design. Using FPGAs, the investment
risk reduces.
2. Due to the uncontrolled market conditions, there is risk involved in the design
and development of products. FPGA prototype reduces such risk as the product
specifications and design can be validated depending on the functional
requirements or changes.
3. FPGA prototyping is efficient as the bugs, those were not detected in simulation,
can be addressed and covered during prototyping.
4. Full-system verification using FPGA prototype can detect the functional bugs in
the early stage of design cycle.
5. FPGA prototyping saves the millions of dollar of EDA tool cost and even it
saves the millions of dollar engineering efforts before ASIC tape-out.
6. As design using FPGA can be migrated using the EDA tool chains onto the
ASICs, it saves the time to market the product with intended functionality.
7. Multiple IPs can be integrated and design functionality can be verified and
tested and that speed up the design cycle.
8. Most of the cases the hardware software portioning is visualized at higher
abstraction level. The hardware software codesign can be evaluated at the
hardware level and it is more important milestone in overall design cycle. So the
ASIC prototyping can be useful in tweaking of the architecture. If there is
additional design overhead in the hardware, then the design architecture can be
changed by pushing few blocks in software and vice versa. This will give the
more efficient architecture and design.
6 1 Introduction to HDL

Table 1.2 Comparison of FPGA with ASIC implementation

FPGA Hard copy Structured ASIC Standard cell ASIC
NRE, mask Up to a Couple of hundred A couple of hundred A million US$
and EDA few thousand US$ for thousand US$ for depending on the
tools thousand FPGA conversion interconnect/meta-one design
US$, so and masks. So the masks so the overall functionality. So
the overall overall cost is cost is moderate the cost is high
cost is low moderate
Unit price High Medium-low Medium-low Low
Time to Immediate Almost around 8– Almost around Almost around
volume 10 weeks. The 8–10 weeks. The 18 weeks +
additional additional conversion conversion time of
conversion time time may require for another 18 weeks
may require for other structured ASIC
other structured products
ASIC products
Engineering Minimum Minimal from Nominal but for the High as most of the
resources developers but other structured ASIC work requires the
and cost other structured products may require development from
product may the additional scratch and
require the engagement of the requires good
additional resources support from the
engineering backend team
resources
FPGA Same For hard It depends upon the Same RTL but
prototype device copy-structured type of IP used and the potentially
correlation ASIC: Nearly functionality. different libraries,
identical—Same Same RTL but process, analog,
logic elements, potentially different and packages
process, analog libraries, process,
components, and analog, and packages
packages

The Table 1.2 gives information about the pros and cons of FPGA and ASIC.
There is always confusion between the prototype and the migration. The ASIC
prototyping is basically the design or validation of idea to check for the early
functional and feasibility of new designs. The design migration from ASIC to
FPGA involves the flow from RTL design to implementation and may be useful in
the upgradation of design with additional features.
Following are the key points need to be considered during ASIC prototyping and
design migration using high-end FPGA.
1. Use the universal prototype board as it saves the time of almost four months to
twelve months for the high-speed prototyping board development.
1.3 ASIC Prototyping 7

2. Choose the FPGA device depending on the functionality and gate count. It is not
possible to fit whole ASIC into single FPGA even if we use the high-end
families of ALTERA or XILINX FPGAs. So the practical solution is use of
multiple FPGAs. But the real issue is the design partitioning and the inter-
communication between multiple FPGAs. If the design is well defined and
partitioned properly, then the manual partitioning into multiple FPGA can give
the efficient results. If the design has complex functionality, then the use of
automatic partitioning can play efficient role and can create the efficient
prototype.
3. As the design library for ASIC and FPGA is totally different, the key challenge
is to map the primitives. So it is essential to map the directly instantiated
primitives during synthesis and during the implementation level. That is at the
post-synthesis, all the primitives from ASIC library need to be remapped for
getting the FPGA prototype.
4. High-end FPGA may have 1000–1500 pins and if one FPGA is used for pro-
totype, then there are limited issues in the pin assignment and pin interface. But
if IO pins required more than the pins available in one FPGA, then the real issue
is due to multiple FPGA interfaces and connectivity. The issue can be resolved
by using the partitioning with the signal multiplexing. This will ensure the
efficient design partitioning and efficient design prototype.
5. Implementation of single clock domain design prototype is easy using FPGAs.
But if the design has more than one clock that is multiple clock domains, then it
is quite difficult to use the clock gating and other clock-generation techniques
during prototype. So the migration of ASIC design into FPGA needs more
efforts and sophisticated solutions. One of the efficient solutions is to convert the
designs into smaller design units clocked by the global clock source.
6. The memory models used in the FPGA are different as compared to ASIC. So it
is essential to use the proper strategy during memory mapping. Most of the time,
the synthesized memory models required are not available. Under such scenario,
the best possible solution is to use the prototyping board with the required
specific memory device.
7. The full functional testing and debugging is one of the main challenges in the
ASIC prototyping. During this phase, it is essential to use the debugging plat-
form which can give the visibility of the results such as speed and functional
testing results.
The ASIC prototyping is achieved by using industry’s standard leading tools
such as Design Compiler FPGA. The design compiler is industry’s leading EDA
tool which is used to get best optimal synthesis result and best timing for the FPGA
8 1 Introduction to HDL

Fig. 1.2 ASIC prototype flow

synthesis. The basic flow for the ASIC prototyping is shown in Fig. 1.2, and in the
subsequent chapters, we will discuss the FPGA based designs and key steps, to
achieve the efficient ASIC prototype using XILINX/Altera FPGA.

1.4 Integrated Circuit Design and Methodologies

With the evolution of VLSI design technology, the designs are becoming more and
more complex and SOC-based design is feasible in shorter design cycle time. The
demand of the customers is to avail the product in the shorter span of time is
possible due to efficient design flow. The design needs to be evolved from speci-
fication stage to final layout. The use of EDA tools with the suitable features has
1.4 Integrated Circuit Design and Methodologies 9

VHDL RTL Design

FuncƟonal
Design Constraints
VerificaƟon

YES NO
Synthesis Coverage
goals met?

Constraints
Met?
NO

YES

Physical Design

Fig. 1.3 Simulation and synthesis flow

made it possible to have the bug-free designs with proven functionality. The design
flow is shown in Fig. 1.3, and it consists of the three major phases to generate the
gate-level netlist.

1.4.1 RTL Coding

Functional design is described in the document form using the architecture and
microarchitecture. Architecture and microarchitecture design is the functional rep-
resentation of the design in the block and sub-block levels. This design document
includes the block level interfaces, timing and logic blocks. The RTL design using
VHDL uses the microarchitecture document as reference document to code the
design. RTL designer uses the suitable design and coding guidelines while
10 1 Introduction to HDL

implementing the RTL design. An efficient RTL design always plays important role
during implementation cycle. During this, designer describes the block-level and
top-level functionality using an efficient VHDL RTL.

1.4.2 Functional Verification

After completion of an efficient VHDL RTL for the given design specifications; the
design functionality is verified by using industry standard simulator. Pre-synthesis
simulation is without any delays and during this the focus is to verify the func-
tionality of design. But common practice in the industry is to verify the function-
ality by writing the testbench. The testbench forces the stimulus of signals to the
design and monitors the output from the design. In the present scenario, automation
in the verification flow and new verification methodologies has evolved and used to
verify the complex design functionality in the shorter span of time using the proper
resources. The role of verification engineer is to test the functional mismatches
between the expected output and actual output. If functional mismatch is found
during simulation, then it needs to be rectified before moving to the synthesis
step. Functional verification is iterative process unless and until design meets the
required functionality.

1.4.3 Synthesis

When the functional requirements of the design are met, the next step is synthesis to
perform the RTL synthesis for the design. Synthesis tool uses the RTL VHDL code,
design constraints, and libraries as inputs to generate the gate-level netlist as an
output. Synthesis is iterative process until the design constraints are met. The
primary design constraints are area, speed, and power. If the design constraints are
not met then the synthesis tool performs more optimization on the RTL design.
After the optimization if it has observed that the constraints are not met then it
becomes compulsory to modify RTL code or tweak the microarchitecture. The
synthesizer tool generates the area, speed, and power reports and gate-level netlist
as an output.

1.4.4 Physical Design

It involves the floor planning of design, power planning, place and route, clock tree
synthesis, post-layout verification, static timing analysis, and generation of GDSII
for an ASIC design. This step is out of scope for the subsequent discussions!
1.5 Programming Language Verses HDL 11

1.5 Programming Language Verses HDL

Most of the engineers have familiarity with the programming languages such as C
and C++. The most important point is to understand the differences between the
programming language and the HDL. Table 1.3 illustrates the key differences
between the programming language and HDL.

1.5.1 VHDL Evolution and Popularity

Very-high-speed integrated circuit hardware description language used to describe

the hardware is also called as the programing language. It is used to describe the
hardware for the programmable logic devices and the integrated circuit designs. The
design automation flow using VHDL RTL plays crucial role while implementing
the designs for high-end PLDs and ASICs.
To document the behavior of the ASICs, the VHDL was introduced by US
Department of Defense. The initial version of VHDL was named as IEEE
1076-1987 standards and has wide variety of the data types. But this was not

Table 1.3 Programming language verses HDL

Parameters Programming language (C or C++) HDL
Instructions Understands only sequential constructs Understands both the sequential and
concurrent constructs
Description Description of program is always Description using HDL is register
style behavioral model. To code the transfer level (RTL). To describe the
behavior, programmer uses analytical, functionality of electronic circuit, the
algorithmic, or logical thinking! designer should have knowledge and
understanding of the hardware circuits
Resources While writing program in C or C++, While describing the electronic circuits
and usage the programmer will never consider using the HDLs, the designer needs to
the use of resources or area. Even most consider the area, speed, and power
of the time programmer does not care requirements. The use of memory and
about the use of memory and the speed resources for the PLD-based designs is
for the program the important parameter needs to be
understood by the designer
Application Used as programming language to Used to design an electronic circuit.
describe the functionality. The user is The user is designer.
programmer. It is a mix of assembly
and high-level language
Time It does not support the notion of time It supports the time constructs and the
constructs notion of time
Flow It supports the data flow in the It supports the data and control flow
constructs sequential manner
12 1 Introduction to HDL

enough to describe the behavior of the hardware and later updated with the mul-
tivalued logic (nine-valued logic) using IEEE std_logic_1164.all package.
The IEEE 1076-1993 standard has made the syntax more consistent to describe the
behavior of the hardware functionality and concurrency. To resolve the restrictions
on the port mapping rules, the minor changes carried out during year 2000–2002
and even the class structure of C++ introduced in the standard. During June 2006,
the new standard for the VHDL was introduced and it is backward compatible with
all the older standards. During February 2008, technical committee of Accellera
approved VHDL 4.0 and it is called as VHDL-2008. During the same year
Accellera released the IEEE standard 1076-2008 and the standard was published
during year 2009.
Table 1.4 describes the various VHDL revisions and the relevant description for
the respective revisions.
Following are the key reasons for which VHDL is popular in the semiconductor
industry.
1. Used to describe the synthesizable logic designs and used for the simulation of
the logic design.
2. VHDL is not case-sensitive language and it is easy to interpret in the context of
logic design.
3. VHDL supports parallelism due to the concurrent constructs.
4. VHDL supports the sequential statements to describe the RTL designs.
5. VHDL supports the notion of time and file input and output handling and thus
used for the simulation of the described design.
6. VHDL code is translated into the real digital logic using the gates and nets
(wires) and very user friendly to design the PLD/ASIC-based designs.
7. VHDL supports the synthesizable and non-synthesizable constructs.
8. VHDL descriptions are described by using the electronic design automation
(EDA) tools. The popular EDA tools used for PLD-based applications are
Xilinx ISE series, Altera Quartus II and Mentor Graphics ModelSim or

Table 1.4 VHDL IEEE standard and revisions

Revision IEEE standard Description
year
1987 IEEE 1076-1987 First standard for the language from the United States of Air Force
1993 IEEE 1076-1993 The most widely used version with the EDA tool support
2000 IEEE 1076-2000 Minor additions in the 1076-1993 standard and support for the
protected type
2002 IEEE 1076-2002 Minor additions in the 1076-2000 standard and support for the
buffer ports
2008 IEEE 1076-2008 The standard supports the use of external names
1.5 Programming Language Verses HDL 13

QuestaSim. The ASIC EDA tools are Synopsys DC, PT, and IC compilers and
Cadence SOC Encounter.
VHDL Description consists of the following:

1. Library declaration IEEE

2. Package declaration for the required IEEE library
STD_LOGIC_1164.all using ‘USE’
3. Entity declaration to describe the input and output interface
4. Architecture declaration to describe the functionality
5. Component: The instance used to describe the logic functionality
is called as component. The component is associated with the
‘entity architecture’ pair. For example for the half adder
description: xor_gate, and_gate are treated as components.
6. Configuration: to define the linkage between the entity
and architecture and components. Configuration is used
for binding of all the components specified in the architecture
with the entity, and will be discussed in the subsequent chapters
7. Package : It is basically subprogram or procedures for the
reuse. Declared by using the keyword ‘USE’ with the
package name. Package consists of the multiple objects
and is visible for the architecture functional description

Note The configuration, component declarations, and the packages will be used
according to the design requirements and will be discussed in the subsequent
chapters.
The template shown in Fig. 1.4 describes the VHDL code structure with the
relevant and required explanation in the respective boxes.
As described in Table 1.5 the VHDL supports nine-valued logic using
STD_LOGIC and used to model or to describe the digital logic designs. Table 1.5
describes the nine-valued logic and the description for the respective logic level.
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I swear by Mary, that mild maiden,
I know no more such under the skye;
When I am king and wear the crown, then
I will be chief of the poor commenty:
Task nor mize I will make none,
In no countrey farr nor nigh;
If their goods I shoud take and pluck them downe,
For me they woud fight full faintly:
There is no riches to me so rich,
As is the love of our poor commenty.
When they had ended all their speeches,
They take their leave full heartiley;
And to his bower King Richard is gone.
The earle and Humphrey Brereton
To Bessy's bower anon were gone;
When Bessy Humphrey did see anon,
She took him in her arms and kissed him times three.
Welcome, she said, Humphrey Brereton;
How hast thou spedd in the West Countrey
I pray thee tell me quickly and anon.
Into a parlour they went from thence,
There were no more but he and shee:
Humphrey, said Bessy, tell me e're we go hence
Some tideings out of the West Countrey;
If I shall send for yonder prince
To come over the sea, for the love of me,
And if King Richard shoud him convince,
Alas! it were great ruthe to see,
Or murthered among the Stanley's blood to be,
Indeed that were great pitty;
That sight on that prince I woud not see,
For all the gold in Christantie!
Tell me, Humphrey, I thee pray,
How hast thou spedd in the West Countrey?
What answer of them thou had now say,
And what reward they gave to thee.
By the third day of May it shall be seen,
In London all that they will bee;
Thou shalt in England be a queen,
Or else doubtless that they will dye.
Thus they proceed forth the winter then,
Their councell they kept close all three,
The earle he wrought by prophecy certaine,
In London he would not abide or bee,
But in the subburbs without the city
An ould inn chosen hath hee.
A drew an Eagle foot on the door truely,
That the western men might know where he did lye.
Humphrey stood on a high tower then,
He looked into the West Countrey;
Sir William Stanley and seven in green,
He was aware of the Eagle drawne;
He drew himselfe so wonderous nigh,
And bad his men go into the towne,
And drink the wine and make merry;
Into the same inn he went full prest,
Whereas the earle his brother lay.
Humphrey full soon into the west
Looks over a long lee;
He was aware of the Lord Strange and seven in green,
Come rideing into the city.
When he was aware of the Eagle drawn,
He drew himself so wonderously nigh,
He bad his men go into the towne certain,
And drink the wine and make merry;
And he himselfe drew then,
Where as his father in the inne lay.
Humphrey looked in the west, I say,
Sixteen in green then did he see;
He was aware of the Warden and Edward Stanley,
Come rideing both in one company.
When they were aware of the Eagle drawne,
The gentlemen they drew it nee;
And bad their men go into the towne,
And drink the wine and make merry.
And did go themselves into the same inn full prest,
Where the earle their father lay.
Yet Humphrey beholdeth into the west,
And looketh towards the north countrey;
He was aware of Sir John Savage and Sir Gilbert Talbot,
Came rideing both in one company.
When they were aware of the Eagle drawn,
Themselves drew it full nigh,
And bad their men go into the towne,
To drink the wine and make merry.
They did go themselves into the same inn,
Where as the earle and Bessy lye.
When all the lords together were,
Amongst them all Bessy was full buissy;
With goodly words Bessy then said there,
Fair lords, what will you do for me?
Will you relieve yonder prince,
That is exiled beyond the sea?
I woud not have King Richard him to convince,
For all the gold in Christentye.
The Earle of Darby came forth then,
These words he said to young Bessye,—
Ten thousand pounds will I send,
Bessy, for the love of thee,
And twenty thousand Eagle feet,
The Queen of England for to make thee;
Then Bessy most lowly the earle did greet,
And thankt his honor most heartiley.
Sir William Stanley came forth then,
These words he said to fair Bessy:
Remember, Bessy, another time,
Who doth the most, Bessy, for thee;
Ten thousand coats, that shall be red certaine,
In an hours warning ready shall bee;
In England thou shall be our queen,
Or doubtlesse I will dye.
Sir John Savage came forth then,
These words he said to young Bessye,—
A thousand marks for thy sake certaine,
Will I send thy love beyond the sea.
Sir Gilbert Talbott came forth then,
These were the words he said to Bessy:
Ten thousand marks for thy sake certaine,
I will send to beyond the sea.
The Lord Strange came forth then,
These were the words he said to Bessy:
A little money and few men,
Will bring thy love over the sea;
Let us keep our gold at home, said he,
For to wage our company;
For if we should send it over the sea,
We shoud put our gold in jeopartie.
Edward Stanley came forth then,
These were the words he said to Bessye:
Remember, Bessye, another time,
Who that now doth the best for thee,
For there is no power that I have,
Nor no gold for to give thee;
I will be under my father's banner, if God me save,
There either to live or dye.
Bessye came forth before the lords all,
And downe she falleth upon her knee;
Nineteen thousand pound of gold, I shall
Send my love behind the sea,
A love letter, and a gold ring,
From my heart root rite will I.
Who shall be the messenger the same to bring,
Both the gold and the writeing over the sea?
Humphrey Brereton, said Bessy,
I know him trusty and true certaine,
Therefore the writeing and the gold truely
By him shall be carried to Little Brittaine.
Alas, said Humphry, I dare not take in hand,
To carry the gold over the sea;
These galley shipps they be so strange,
They will me night so wonderously;
They will me robb, they will me drowne,
They will take the gold from me.
Hold thy peace, Humphrey, said Bessye then,
Thou shalt it carry without jepordye;
Thou shalt not have any caskett nor any male,
Nor budgett, nor cloak sack, shall go with thee;
Three mules that be stiff and strong withall,
Sore loaded with gold shall they bee,
With saddle-side skirted I do tell thee
Wherein the gold sowe will I:
If any man faine whose is the shipp truely
That saileth forth upon the sea,
Say it is the Lord Lislay,
In England and France well beloved is he.
Then came forth the Earle of Darby,
These words he said to young Bessy:
He said, Bessye, thou art to blame
To appoint any shipp upon the sea;
I have a good shipp of my owne,
Shall carry Humphrey with the mules three;
An eagle shall be drawne upon the mast top,
That the Italians may it see;
There is no freak in all France
The eagle that dare come nee
If any one ask whose ship it is, then
Say it is the Earles of Darby.
Humphrey took the three mules then,
Into the west wind wou'd hee,
Without all doubt at Liverpoole
 He took shipping upon the sea:
With a swift wind and a liart,
He so saild upon the sea,
To Beggrames Abbey in Little Brittain,
Where as the English Prince lie;
The Porter was a Cheshire man,
Well he knew Humphrey when he him see;
Humphrey knockt at the gate truely,
Where as the porter stood it by,
And welcomed me full heartiley,
And received then my mules three;
I shall thee give in this breed
To thy reward pounds three;
I will none of thy gold, the porter said,
Nor Humphrey none of the fee,
I will open thee the gates certaine
To receive thee and the mules three;
For a Cheshire man born am I certain,
From the Malpas but miles three.
The porter opened the gates that time,
And received him and the mules three.
The wine that was in the hall that time
He gave to Humphrey Brereton truely.
Alas! said Humphrey, how shoud I doe,
I am strayed in a strange countrey,
The Prince of England I do not know,
Before I never did him see.
I shall thee tell, said the porter then,
The Prince of England know shall ye,
Low where he siteth at the butts certaine,
With other lords two or three;
He weareth a gown of velvet black
And it is cutted above the knee,
With a long visage and pale and black—
Thereby know that prince may ye;
A wart he hath, the porter said,
 A little alsoe above the chinn,
His face is white, his wart is redd,
No more than the head of a small pinn;
You may know the prince certaine,
As soon as you look upon him truely.—
He received the wine of the porter, then
With him he took the mules three.
When Humphrey came before that prince
He falleth downe upon his knee,
He delivereth the letters which Bessy sent,
And so did he the mules three,
A rich ring with a stone,
Thereof the prince glad was hee;
He took the ring of Humphrey then,
And kissed the ring times three.
Humphrey kneeled still as any stone,
As sure as I do tell to thee;
Humphrey of the prince answer gott none,
Therefore in heart was he heavy;
Humphrey stood up then full of skill,
And then to the prince said he:
Why standest thou so still at thy will,
And no answer dost give to me?
I am come from the Stanleys' blood so dear,
King of England for to make thee,
A fairer lady then thou shalt have to thy fair,
There is not one in all christantye;
She is a countesse, a king's daughter, Humphrey said,
The name of her it is Bessye,
She can write, and she can read,
Well can she work by prophecy;
I may be called a lewd messenger,
For answer of thee I can gett none,
I may sail home with heavy cheare,
What shall I say when I come home?
The prince he took the Lord Lee,
 And the Earle of Oxford was him nee,
The Lord Ferris wou'd not him beguile truely,
To councell they are gone all three;
When they had their councell taken,
To Humphrey then turned he:
Answer, Humphrey, I can give none truely
Within the space of weeks three;
The mules into a stable were taken anon,
The saddle skirts unopened were,
Therein he found gold great plenty
For to wage a company.
He caused the abbot to make him chear:
In my stead now let him be,
If I be king and wear the crown
Well acquited Abbott shalt thou be.
Early in the morning they made them knowne,
As soon as the light they cou'd see;
With him he taketh his lords three,
And straight to Paris he took his way.
An herriott of arms they made ready,
Of men and money they cou'd him pray,
And shipps to bring him over the sea,
The Stanleys' blood for me hath sent,
The King of England for to make me,
And I thank them for their intent,
For if ever in England I wear the crowne,
Well accquited the King of France shall be:
Then answered the King of France anon,
Men nor money he getteth none of me,
Nor no shipps to bring him over the sea;
In England if he wear the crowne,
Then will he claim them for his own truely:
With this answer departed the prince anon,
And so departed the same tide,
And the English lords three
To Beggrames Abbey soon coud the ride,
 There as Humphrey Brereton then lee;
Have Humphrey a thousand mark here,
Better rewarded may thou be;
Commend me to Bessy that Countesse clear,
Before her never did I see:
I trust in God she shall be my feer,
For her I will travell over the sea;
Commend me to my father Stanley, to me so dear,
My owne mother married hath he,
Bring him here a love letter full right
And another to young Bessye,
Tell her, I trust in Jesus full of might
That my queen that she shall bee;
Commend me to Sir William Stanley,
That noble knight in the west countrey,
Tell him that about Michaelmas certaine
In England I do hope to be;
At Millford haven I will come inn
With all the power that make may I,
The first town I will come inn
Shall be the towne of Shrewsbury;
Pray Sir William Stanley, that noble knight,
That night that he will look on me:
Commend me to Sir Gilbert Talbot, that royall knight,
He much in the north countrey,
And Sir John Savage, that man of might,—
Pray them all to look on me,
For I trust in Jesus Christ so full of might,
In England for to abide and bee.
I will none of thy gold, sir prince, said Humphrey then,
Nor none sure will I have of thy fee,
Therefore keep thy gold thee within,
For to wage thy company;
If every hair were a man,
With thee, sir prince, will I be:
Thus Humphrey Brereton his leave hath tane,
 And sailed forth upon the sea,
Straight to London he rideth then,
There as the earle and Bessy lay;
And bad them behold, read and see.
The earle took leave of Richard the king,
And into the west wind wou'd he;
He left Bessye in Leicester then
And bad her lye in pryvitye,
For if King Richard knew thee here anon,
In a fire burned thou must be.
Straight to Latham the earle is gone,
There as the Lord Strange then lee;
He sent the Lord Strange to London,
To keep King Richard company.
Sir William Stanley made anone
Ten thousand coats readily,
Which were as redd as any blood,
Thereon the hart's head was set full high,
Which after were tryed both trusty and good
As any cou'd be in Christantye.
Sir Gilbert Talbot ten thousand doggs
In one hour's warning for to be,
And Sir John Savage fifteen white hoods,
Which wou'd fight and never flee;
Edward Stanley had three hundred men,
There were no better in Christantye;
Sir Rees ap Thomas, a knight of Wales certain,
Eight thousand spears brought he.
Sir William Stanley sat in the Holt Castle,
And looked over his head so high;
Which way standeth the wind, can any tell?
I pray you, my men, look and see.
The wind it standeth south east,
So said a knight that stood him by.
This night yonder prince, truely
Into England entereth hee.
 He called a gentleman that stood him nigh,
His name was Rowland of Warburton,
He bad him go to Shrewsbury that night,
And bid yonder prince come inn:
But when Rowland came to Shrewsbury,
The portculles was let downe;
They called him Henry Tydder, in scorn truely,
And said, in England he shou'd wear no crowne;
Rowland bethought him of a wyle then,
And tied a writeing to a stone,
And threw the writeing over the wall certain,
And bad the bailiffs to look it upon:
They opened the gates on every side,
And met the prince with procession;
And wou'd not in Shrewsbury there abide,
But straight he drest him to Stafford towne.
King Richard heard then of his comeing,
He called his lords of great renowne;
The Lord Pearcy he came to the king
And upon his knees he falleth downe,
I have thirty thousand fighting men
For to keep the crown with thee.
The Duke of Northfolk came to the king anone,
And downe he falleth upon his knee;
The Earle of Surrey, that was his heir,
Were both in one company;
We have either twenty thousand men here,
For to keep the crown with thee.
The Lord Latimer, and the Lord Lovell,
And the Earle of Kent he stood him by,
The Lord Ross, and the Lord Scrope, I you tell,
They were all in one company;
The Bishopp of Durham, he was not away,
Sir William Bonner he stood him by,
The good Sir William of Harrington, as I say,
Said, he wou'd fight and never fly.
 King Richard made a messenger,
And sent him into the west countrey,
And bid the Earle of Darby make him bowne,
And bring twenty thousand men unto me,
Or else the Lord Strange his head I will him send,
And doubtless his son shall dye;
For hitherto his father I took for my friend,
And now he hath deceived me.
Another herald appeared then
To Sir William Stanley that doughty knight,
Bid him bring to me ten thousand men,
Or else to death he shall be dight.
Then answered that doughty knight,
And spake to the herald without letting;
Say, upon Bosseworth Field I meen to fight,
Uppon Monday early in the morning;
Such a breakfast I him behight,
As never did knight to any king.
The messenger home can him gett,
To tell King Richard this tydeing.
Fast together his hands then cou'd he ding,
And said, the Lord Strange shou'd surely dye;
And putt him into the Tower of London,
For at liberty he shou'd not bee.
Lett us leave Richard and his lords full of pride,
And talk we more of the Stanleys' blood,
That brought Richmond over the sea with wind and tyde,
From Litle Brittain into England over the flood.
Now is Earle Richmond into Stafford come,
And Sir William Stanley to Litle Stoone;
The prince had rather then all the gold in Christantye,
To have Sir William Stanley to look upon;
A messenger was made ready anone,
That night to go to Litle Stoon;
Sir William Stanley he rideth to Stafford towne,
With a solemn company ready bowne.
 When the knight to Stafford was comin,
That Earle Richmond might him see,
He took him in his arms then,
And there he kissed him times three;
The welfare of thy body doth comfort me more
Then all the gold in Christantye.
Then answered that royall knight there,
And to the prince these words spake he,—
Remember, man, both night and day,
Who doth now the most for thee;
In England thou shalt wear a crown, I say,
Or else doubtless I will dye;
A fairer lady then thou shalt have for thy feer,
Was there never in Christanty;
She is a countesse, a king's daughter,
And there to both wise and witty;
I must this night to Stone, my soveraigne,
For to comfort my company.
The prince he took him by the hand,
And said, farewell, Sir William, fair and free.
Now is word come to Sir William Stanley there,
Early in the Monday, in the morning,
That the Earle of Darby, his brother dear,
Had given battle to Richard the king.
That wou'd I not, said Sir William anone,
For all the gold in Christantye,
That the battle shou'd be done;
Straight to Lichfield cou'd he ride,
In all the hast that might bee,
And when he came to Lichfield that tyde,
All they cryed King Henry:
Straight to Bolesworth can they go
In all the hast that might be,
But when he came Bolesworth Field unto,
There met a royall company;
The Earle of Darby thither was come,
 And twenty thousand stood him by;
Sir John Savage, his sister's son,
He was his nephew of his blood so nigh,
He had fifteen hundred fighting men,
That wou'd fight and never flye;
Sir William Stanley, that royall knight, then
Ten thousand red coats had he,
They wou'd bicker with their bows there,
They wou'd fight and never flye;
The Red Rosse, and the Blew Boar,
They were both a solemn company;
Sir Rees ap Thomas he was thereby,
With ten thousand spears of mighty tree;
The Earle of Richmond went to the Earle of Darby,
And downe he falleth upon his knee,
Said, father Stanley, full of might,
The vaward I pray you give to me,
For I am come to claime my right,
And faine revenged wou'd I bee.
Stand up, he said, my son, quickly,
Thou hast thy mother's blessing truely,
The vaward, son, I will give to thee,
So that thou wilt be ordered by me:
Sir William Stanley, my brother dear,
In the battle he shall be;
Sir John Savage, he hath no peer,
He shall be a wing then to thee;
Sir Rees ap Thomas shall break the array,
For he will fight and never flee;
I myselfe will hove on the hill, I say,
The fair battle I will see.
King Richard he hoveth upon the mountaine;
He was aware of the banner of the bould Stanley,
And saith, Fetch hither the Lord Strange certain,
For he shall dye this same day;
To the death, Lord, thee ready make,
 For I tell thee certainly
That thou shalt dye for thy uncle's sake,
Wild William of Stanley.
If I shall dye, said the Lord Strange then,
As God forbid it shou'd so bee,
Alas! for my lady that is at home,
It should be long or she see me,
But we shall meet at doomsday,
When the great doom shall be.
He called for a gent in good fay,
Of Lancashire, both fair and free,
The name of him it was Lathum;
A ring of gould he took from his finger,
And threw it to the gent then,
And bad him bring it to Lancashire,
To his lady that was at home;
At her table she may sit right,
Or she see her lord it may be long,
I have no foot to fligh nor fight,
I must be murdered with the king:
If fortune my uncle Sir William Stanley loose the field,
As God forbid it shou'd so bee,
Pray her to take my eldest son and child,
And exile him over behind the sea;
He may come in another time
By feild or fleet, by tower or towne,
Wreak so he may his father's death in fyne,
Upon Richard of England that weareth the crown.
A knight to King Richard then did appeare,
The good Sir William of Harrington.
Let that Lord have his life, my dear
Sir king, I pray you grant me this boone,
We shall have upon this field anon,
The father, the son, and the uncle all three;
Then shall you deem, lord, with your own mouth then,
What shall be the death of them all three.
 Then a block was cast upon the ground,
Thereon the lord's head was laid,
A slave over his head can stand,
And thus that time to him thus said:
In faith there is no other booty tho',
But need that thou must be dead.
Harrington in hart was full woe,
When he saw that the lord must needs be dead.
He said, our ray breaketh on ev'ry side,
We put our feyld in jepordie.
He took up the lord that tyde,
King Richard after did him never see.
Then they blew up their bewgles of brass,
That made many a wife to cry alas!
And many a wive's child fatherlesse;
They shott of guns then very fast,
Over their heads they could them throw:
Arrows flew them between,
As thick as any hayle or snowe,
As then that time might plaine be seene;
Then Rees ap Thomas with the black raven,
Shortly he brake their array;
Then with thirty thousand fighting men
The Lord Pearcy went his way;
The Duke of Northefolke wou'd have fledd with a good will,
With twenty thousand of his company,
They went up to a wind millne uppon a hill,
That stood soe fayre and wonderousse hye;
There he met Sir John Savage, a royall knight,
And with him a worthy company;
To the death was he then dight,
And his sonne prisoner taken was he;
Then the Lord Alroes began for to flee,
And so did many other moe;
When King Richard that sight did see,
In his heart hee was never soe woe:
 I pray you, my merry men, be not away,
For upon this field will I like a man dye,
For I had rather dye this day,
Then with the Standley prisoner to be.
A knight to King Richard can say there,
Good Sir William of Harrington;
He said, sir king, it hathe no peer,
Upon this feyld to death to be done,
For there may no man these dints abide;
Low, your horse is ready at your hand:
Sett the crown upon my head that tyde,
Give me my battle axe in my hand;
I make a vow to myld Mary that is so bright,
I will dye the king of merry England.
Besides his head they hewed the crown down right,
That after he was not able to stand;
They dinge him downe as they were woode,
They beat his bassnet to his heade,
Until the braynes came out with the bloode;
They never left him till he was dead.
Then carryed they him to Leicester,
And pulled his head under his feet.
Bessye mett him with a merry cheare,
And with these words she did him greete;
How like you the killing of my brethren dear?
Welcome, gentle uncle, home!
Great solace ytt was to see and hear,
When the battell yt was all done;
I tell you, masters, without lett,
When the Red Rosse soe fair of hew,
And young Bessye together mett,
It was great joy I say to you.
A bishopp then marryed with a ringe
The two bloods of great renowne.
Bessy said, now may we singe,
Wee two bloods are made all one.
 The Earle of Darby hee was there,
And Sir William Stanley, that noble knight,
Upon their heads he set the crown so fair,
That was made of gould so bright.
And there he came under a cloud,
That some time in England looked full high;
But then the hart he lost his head,
That after no man cou'd him see.
But Jesus, that is both bright and shine,
And born was of mylde Mary,
Save and keepe our noble kinge,
And also the poore commentie. Amen.
The other version of this ballad, to which I have referred, is
preserved in the Harleian MSS. It differs considerably from the one
here printed, as will be at once apparent from the following opening
passage:—

God that is moste of myghte,

And born was of a mayden free,
Save and kepe our comlye queene,
And also the poore comynalitie;
For wheras Kynge Richard, I understande,
Had not reigned yeares three,
But the beste Duke in all this lande
He caused to be headit at Salysburye;
That tyme the Standleyes without dowte
Were dred over England ferre and nee,
Next Kynge Richard that was soe stowte
Of any lorde in England free.
There was a ladye faire on moulde,
The name of hir was litill Bessie;
She was yonge, she was not oulde,
Bot of the yeares of one and twentye;
She colde wryte and she coulde reede,
Well she coulde wyrke by propesye;
She sojorned in the cetye of London
That tyme with the Earle of Derbye.
Upon a tyme, as I you tell,
There was noe moe bot the Earle and she,
She made complaynte one Richard the Kynge,
That was hir uncle of blode soe nee.
There are many other ballads having reference to the Stanleys, Earls
of Derby; but this will be sufficient as a present example.
 Devonshire's Noble Duel
WITH LORD DANBY IN THE YEAR 1687.

Of this curious ballad, which is also known by the name of "The

Long Armed Duke," there are several versions. The one here given is
printed from a broad-sheet, and is, perhaps, the most complete of
any of the versions which has come under my notice. The
circumstance which gave rise to the ballad has not as yet been
satisfactorily explained. It has been suggested that its origin was the
quarrel in which the Earl of Devonshire, Lord Delamere, and Colonel
Colepepper were engaged. It is traditionally said that the arms of
the "Long Armed Duke" were so long that he could garter his
stockings below the knee without stooping down or being seated!

Good people give attention to a story you shall hear,

Between the King and my Lord Delamere
A quarrel arose in the Parliament House,
Concerning the Taxes to be put in force.
With my fal de ral de ra.

I wonder, I wonder, that James our good King,

So many hard Taxes upon the poor should bring;
So many hard Taxes, as I have heard them say
Makes many a good farmer to break and run away.

Such a rout has been in the Parliament, as I hear,

Betwixt a Dutch lord and my Lord Delamere.
He said to the King, as he sat on the throne,
"If it please you, my Liege, to grant me a boon."

"Oh, what is thy boon? Come let me understand."

"'Tis to give me all the poor you have in the land;
I'll take them down to Cheshire, and there I will sow
Both hemp seed and flax seed, and hang them in a row.

It's better, my Liege, they should die a shorter death,

Than for your Majesty to starve them on earth."
With that up starts a Dutch Lord, as we hear,
And he says, "Thou proud Jack," to my Lord Delamere,

"Thou ought to be stabbed," and he turned him about,

"For affronting the King in the Parliament House."
Then up got a brave Duke, the Duke of Devonshire,
Who said, "I will fight for my Lord Delamere:—

He is under age, as I'll make it appear;

So I'll stand in defence of my Lord Delamere."
A stage then was built, and to battle they went,
To kill or be killed it was their intent.

The very first blow, as we understand,

Devonshire's rapier went back to his hand;
Then he muséd awhile, but not a word spoke
When against the King's armour his rapier he broke.

Oh, then he stept backward, and backward stept he,

And then stept forward my Lord Willoughby;
He gave him a rapier, and thus he did say,
"Play low, Devonshire, there's treachery, I see."

He knelt on his knee, and he gave him the wound;

With that the Dutch Lord fell dead on the ground.
The King call'd his soldiers, and thus he did say,
"Call Devonshire down, take the dead man away."

He answered, "My Liege, I've killed him like a man,

And it is my intent to see what clothing he's got on.
O treachery! O treachery! as I well may say,
It was your intent, O King, to take my life away.
He fought in your armour, while I fought him bare,
And thou, King, shalt win it before thou dost it wear;
I neither do curse King, Parliament, or Throne,
But I wish every honest man may enjoy his own.

The rich men do flourish with silver and gold,

While poor men are starving with hunger and cold;
And if they hold on as they have begun,
They'll make little England pay dear for a King."
Another version, which I have in MS., has, besides many minor
variations, these additional verses:—

Oh the Duchess of Devonshire was standing hard by,

Upon her dear husband she cast her lovely eye;
"Oh, fie upon treachery—there's been treachery, I say,—
It was your full intent to have ta'en my Duke's life away."

Then away to the Parliament these votes all went again,

And there they acted like just and honest men.
I neither curse my King, nor kingdom, crown or throne,
But I wish every honest man to enjoy but what is his own.

One of the versions of this ballad gives the name of Lord Delaware—

"In the Parliament House a great rout has been there,

Betwixt our good King and the Lord Delaware."

And it also gives the locality for sowing "hemp seed and flax seed" to
"Lincolnshire." This same version speaks of the Duke of Devonshire
as—

"Up sprung a Welch Lord, the brave Duke of Devonshire."

There can be no doubt, however, that Lord Delamere is the peer

intended to be commemorated, and that Cheshire is the county to
which he is made to refer, and to which indeed he belonged.
 The Unconsionable Batchelors of
Darby:
Or the Young Lasses Pawn'd by their Sweet-
hearts, for a large Reckning, at Nottingham
Goose-Fair, where poor Susan was forced to
pay the Shot.

To the tune of To thee, to thee, &c.

This curious ballad I reprint from a black-letter broad-sheet in the

Roxburghe Collection in the British Museum, where it is adorned with
three curious wood-cuts. Nottingham Goose Fair, it may be well to
remark, is still the most popular fair in the Midland Counties, and is
annually attended by many of the "Lasses of Darby," who "with
young men" go "to Goose-fair for recreation," by special trains and
otherwise. The distance of Nottingham from Derby by turnpike road,
along which the lasses and young men of the ballad must have
travelled, is fifteen miles. Goose-fair formerly lasted for twenty-one
days.

You lovers of mirth attend a while

a merry new Ditty here I write
I know it will make you laugh and smile
for every line affords delight:
The Lasses of Darby with young Men
they went to Goose-fair for recreation
But how these Sparks did serve them then
is truly worth your observation:
Truly, truly, worth your observation,
therefore I pray observe this Ditty
The Maids did complain they came there in vain
and was not, was not that a pity.

So soon as they came into the Fair

the Batchellers made them conjues low
And bid them a thousand welcomes there
this done, to a tipling-school they go:
How pleasant was honest Kate and Sue?
believing they should be richly treated,
But Neighbours and Friends as I am true
no Lasses ever was so cheated:
Cheated, cheated, very farely cheated
they were left alone to make their moan
And was not, was not that a pity.

The innocent Lasses fair and gay

concluded the Men was kind and free
Because they pass'd the time away
a plenty of cakes and ale they see;
For sider and mead they then did call
and whatever else the House afforded
But Susan was forc'd to pay for all
out of the money she had hoarded
Hoarded, hoarded, money she had hoarded
it made her sing a doleful Ditty
And so did the rest with grief opprest
and was not, was not that a pity.

Young Katy she seemed something coy

because she would make them eager grow,
As knowing thereby she might enjoy
what beautiful Damsels long to know.
On compliments they did not stand
nor did they admire their charming features
For they had another game in hand
which was to pawn those pretty Creatures;
Creatures, creatures, loving loving creatures
which was so charming fair and pretty
The Men sneak'd away and nothing did pay
and was not, was not that a pity?

Though 'f out of the door they enterd first

and left them tipling there behind
Those innocent Maids did not mistrust
that Batchelors could be so unkind;
Quoth Susan, I know their gone to buy
the fairings which we do require
And they will return, I know, for why
they do our youthful charms admire,
Therefore, therefore stay a little longer
and I will sing a pleasant Ditty
But when they found they were catch'd in the pound
they sigh'd and weep'd the more's the pity.

Now finding the Men returned no more

and that the good People would not trust
They presently call'd to know the score
it chanc'd to be fifteen shillings just:
Poor Kate had but five pence in her purse
but Sue had a crown besides a guinney;
And since the case had happen'd thus
poor Soul she paid it e'ry penny;
Penny, penny, e'ry, e'ry penny
tho' with a sad and doleful Ditty
Said she for this I had not a kiss
and was not, was not that a pity?

Printed for J. Bessel, in West-Smithfield.

 The Humours of Hayfield Fair.
This ballad, copied from a broad-sheet, has been printed in
Hutchinson's "Tour through the High Peak of Derbyshire," 1809. It
will be seen to be a version—whether the original one or not
remains to be seen—of the favourite ballad usually called "Come
Lasses and Lads," of which the earliest known copy appears to have
been printed in 1672, under the title of "The Rural Dance about the
May-pole," and which has again been printed in "Pills to purge
Melancholy," in "Tixhall poetry," and also, with the music, in
Chappel's "Popular Music of the Olden Time," as well as in several
other works. It ought to be stated that the ballad I here reprint
—"The Humours of Hayfield Fair,"—although I speak of it as a
version of the "Rural Dance about the May-pole," is, with the
exception of here and there a verse, or part of a verse, totally
distinct from it. It will, of course, be seen to go to the same tune.
Hayfield is a village near Chapel-en-le-Frith, in the High Peak of
Derbyshire,—in the midst of a district as wild in its superstitions as in
its ballad poetry, and in its traditions as in its scenery. It has two
fairs in the year, which were formerly much frequented by the "Lads
and Lasses" of the district, whether they had "leave of their dads" or
not.
Come, lasses and lads, take leave of your dads,
And away to the fair let's hie;
For every lad has gotten his lass,
And a fiddler standing by;
For Jenny has gotten her Jack,
And Nancy has gotten her Joe,
With Dolly and Tommy, good lack,
How they jig it to and fro!
Ritum, raddledum, raddledum; ritum raddledum ri;
Ritum, raddledum, raddledum; ritum raddledum ri.

My heart 'gain ribs ga' thumps,

When I went to th' wake or fair,
Wi' a pair of new sol'd pumps,
To dance when I got there;
I'd ride grey nag I swore,
And were mounted like a king,
Cousin Dickey walked on a'fore,
Driving a pig tied wi' a string.
Ritum raddledum, &c.

Pally Sampson too was there,

Wi' "Neighbour how do you do?"
There were all the world at the fair,
And drunk 'till they were fou';
'Twas neither heigh! nor gee!
For soon as I sold my cow,
The fiddler shog'd his knee,
And I danced my pumps clean through.
Ritum raddledum, &c.

"You're out," says Dick—"I'm not," says Nick,

"The fiddler plays it false;"
And so says Hugh, and so says Sue,
And so says nimble Alice;
The fiddler did agree,
To right us in a crack,
Dance face to face, says he,
And then dance back to back.
Ritum raddledum, &c.

Thus after an hour they tript to a bower

To play for ale and cakes,
And kisses too—until they were due,
The maidens held the stakes;
The women then began
 To quarrel with the men,
And bad them take their kisses back,
And gi' 'em their own again.
Ritum raddledum, &c.

Thus they sat, until it were late,

And they tir'd the fiddler quite,
Wi' singing and playing, without any paying,
From morning until it were night:
They told the fiddler then
They'd pay him for his play,
And each gave two-pence,
(Speaking) (Ey, they gave him two pence a piece)
And then they hopp'd away.
Ritum raddledum, &c.

Come Dolly, says I, now homeward hie,

And I'll go wi' thee a mile;
She twinkled her eyes wi' a sigh
As I handed her over the style;
Then I cuddled, and kissed her face,
Were I much to blame?
Had you been in my place,
(Speaking) (I don't mean you in the smock frock dancing a
hornpipe—I mean that sly looking fellow smoking his
pipe in the corner,)
I vow you'd ha' done the same.
Ritum raddledum, &c.
 ON THE
Strange and Wonderful Sight
That was seen in the Air on the 6th of March, 1716.

This ballad occurs in "The Garland of Merriment: containing Three New Songs. 1st. A
Game at Cards for a Kingdom, or Mar routed. 2d. A Comical Scotch Dialogue between a
Highlander and his Wife about the last Battle. 3d. A Copy of Verses on the Death of my
Lord Derwentwater. 4th. On the Wonderful Sight that was seen in the Air on the 6th of
March last. Nottingham: Printed by William Ayscough in Bridlesmith Gate." I am not
aware that it has ever been reprinted, except by myself in "The Reliquary" for April 1866.
The appearances were probably those of the Aurora borealis. On the title-page of this
curious chap-book, which was printed in 1716-7, is a wood-cut of four persons playing
cards at a table.

The sixth of March, kind neighbours this is true,

A wonder in the Sky came to my View;
I pray believe it, for I tell no Lye,
There's many more did see it as well as I.

I was on a Travel, and was very late,

To speak the truth just about Day-light' gate;
My Heart did tremble being all alone,
To see such Wonders—the like was never known.

The first of all so dark it was to me,

That much ado my Way I had to see;
I turn'd me round to see some Lights appear,
And then I saw those Wonders in the air.

These Lights to me like great long spears did show,

Sharp at one end, kind neighbours this is true;
I was so troubled, I could not count them o'er,
But I suppose there was above a score.

Then I saw like Blood it did appear,

And that was very throng among those spears;
I thought the Sky would have opened in my View,
I was so daunted I knew not what to do.

The next I saw two Clouds meet fierce together

As if they would have fought one another;
And darkened all these Spears excepting one,
They gave a Clash and quickly they were gone.

The very last Day in the same month I am told

Many People did strange Sights behold;
At Hartington, the truth I will not spare,
That Night they saw Great Wonders in the Air.

This Hartington it is in Darbyshire,

And credible persons living there,
They have declared what Wonders they did view
The very last night in March its certain true.

About Eleven a'Clock late in that Night,

A very dark Cloud which did them sore afright;
Great smoke there came, it was perfect to their view,
They cried out, O Lord, what must we do?

They saw Great Lights which did amaze them sore,

The like was never seen in any Age before,
They went into their Houses for to Pray,
We must Repent whilst it is call'd to Day.
 The Drunken Butcher of Tideswell.
Tideswell is one of the largest and most important villages in the High Peak of
Derbyshire, and has been more than once, as will be seen in the present volume,
celebrated in song and ballad. It is situated about seven miles from Buxton, and the
same from Bakewell, in a highly romantic and wildly picturesque neighbourhood. Its
church is a fine building, containing many interesting monuments, among which are
those to the Foljambes, Meverells, &c., and one to Bishop Pursglove. The following ballad
is the production of William Bennett, the author of "The King of the Peak," "The Cavalier,"
etc. Of this ballad Mr. Bennett thus spoke in the "Reliquary," in which it appeared:—"The
ballad (the subject of which is as well known in the Peak as that Kinder Scout is the
highest hill, and Tideswell Church the most stately and beautiful church in it) will perhaps
appear a little modernised to some, who have only heard the tale from the mouths of
unsober topers, accustomed to use ancient provincial and obsolete words, which not only
render the sense less distinguishable, but also mar the flow of the rhythm. I confess,
therefore, to having taken some liberties with the grammar, the orthography, and the
metre; but in all other respects I have strictly adhered to the original; and my honesty in
this respect will be recognized and admitted by many persons to whom these minstrel
relics are precious.
"The legend is still so strong in the Peak, that numbers of the inhabitants do not concur
in the sensible interpretation put upon the appearance by the Butcher's wife, but
pertinaciously believe that the drunken man was beset by an evil spirit, which either ran
by his horse's side, or rolled on the ground before him, faster than his horse could gallop,
from Peak Forest to the sacred inclosure of Tideswell churchyard, where it disappeared;
and many a bold fellow, on a moonlight night, looks anxiously around as he crosses
Tideswell Moor, and gives his nag an additional touch of the spur, as he hears the bell of
Tideswell Church swinging midnight to the winds, and remembers the tale of the
'Drunken Butcher of Tideswell.'"

Oh, list to me, ye yeomen all,

Who live in dale or down!
My song is of a butcher tall,
Who lived in Tiddeswall town.
In bluff King Harry's merry days,
He slew both sheep and kine;
And drank his fill of nut brown ale,
In lack of good red wine.

Beside the Church this Butcher lived,

Close to its gray old walls;
And envied not, when trade was good,
The Baron in his halls.
No carking cares disturbed his rest,
When off to bed he slunk;
And oft he snored for ten good hours,
Because he got so drunk.

One only sorrow quelled his heart,

As well it might quell mine—
The fear of sprites and grisly ghosts,
Which dance in the moonshine;
Or wander in the cold Churchyard,
Among the dismal tombs;
Where hemlock blossoms in the day,
By night the nightshade blooms.

It chanced upon a summer's day,

When heather-bells were blowing,
Bold Robin crossed o'er Tiddeswall Moor,
And heard the heath-cock crowing:
Well mounted on a forest nag,
He freely rode and fast;
Nor drew a rein, till Sparrow Pit,[4]
And Paislow Moss[5] were past.

Then slowly down the hill he came,

To the Chappelle en le firth,[6]
Where, at the Rose of Lancaster,
He found his friend the Smith:
The Parson, and the Pardoner too,
There took their morning draught;
And when they spied a Brother near,
They all came out and laughed.

"Now draw thy rein, thou jolly Butcher;

How far hast thou to ride?"
"To Waylee-Bridge,[7] to Simon the Tanner,
To sell this good cow-hide."
"Thou shall not go one foot ayont,
'Till thou light and sup with me;
And when thou'st emptied my measure of liquor,
I'll have a measure wi' thee."

"Oh no, oh no, thou drouthy Smith!

I cannot tarry to-day:
The Wife, she gave me a charge to keep;
And I durst not say her nay."
"What likes o' that," said the Parson then,
 "If thou'st sworn, thou'st ne'er to rue:
Thou may'st keep thy pledge, and drink thy stoup,
As an honest man e'en may do."

"Oh no, oh no, thou jolly Parson!

I cannot tarry, I say;
I was drunk last night, and if I tarry,
I'se be drunk again to-day."
"What likes, what likes," cried the Pardoner then,
"Why tellest thou that to me?
Thou may'st e'en get thee drunk this blessed night;
And well shrived for both thou shalt be."

Then down got the Butcher from his horse,

I wot full fain was he;
And he drank 'till the summer sun was set,
In that jolly company:
He drank 'till the summer sun went down,
And the stars began to shine;
And his greasy noddle was dazed and addle,
With the nut brown ale and wine.

Then up arose those four mad fellows,

And joining hand in hand,
They danced around the hostel floor,
And sung, tho' they scarce could stand,
"We've aye been drunk on yester night,
And drunk the night before;
And sae we're drunk again to-night,
If we never get drunk any more."

Bold Robin the Butcher was horsed and away;

And a drunken wight was he;
For sometimes his blood-red eyes saw double;
And then he could scantly see.
The forest trees seemed to featly dance,
As he rode so swift along;
And the forest trees, to his wildered sense,
Resang the jovial song.

Then up he sped over Paislow Moss,

And down by the Chamber Knowle:[8]
And there he was scared into mortal fear
By the hooting of a barn owl:
And on he rode, by the Forest Wall,
Where the deer browsed silently;
And up the Slack, 'till, on Tiddeswall Moor,
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