CCSCI 2406 Computer Org.

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Architecture
Addressing Memory
2 ARM Memory Map
The segments of a program in execution
 The Memory Map
3

The ARM architecture

divides the address space into
five parts or segments: the text
segment, global data segment,
dynamic data segment, and
segments for exception
handlers , the operating system
(OS) and input/output (I/O)
 Text and Data Segments
4

● The text segment stores the machine language

program. In addition to code, also literals
(constants) and read-only data
● The global data segment stores global variables
that, in contrast to local variables, can be accessed
by all functions in a program (Read/Write segment)
 Dynamic Data Segment
5

● The dynamic data segment holds the stack and the

heap . The data in this segment is not known at start-up
but is dynamically allocated and deallocated
throughout the execution of the program
● On start-up, the operating system sets up the stack
pointer (SP) to point to the top of the stack. The stack
typically grows downward.
● The stack includes temporary storage and local
variables, such as arrays, that do not fit in the registers
6 Addressing Memory
Modes for accessing memory
 What are ‘Addressing Modes’?
7

● Data is rarely hard-coded into an instruction using

immediates (eg mov r0, #2).
● We nearly always read our data from physical memory
(RAM),
○ Then we can use the data, and
○ Write it back to physical memory
● There are differnt methods (or modes) we can use to
achieve the correct outcome
 Important Addressing Modes
8

● Register direct (aka Register to Register)

○ MOV R0, R1
● Direct (aka Absolute)
○ LDR R0, MEM
● Immediate
○ MOV R0, #15
● Register indirect
○ LDR R0, [R1]
● Register indirect with offset
○ LDR R0, [R1, #4]
● Double Register Indirect
○ LDR R0, [R1, R2]
 Direct (Absolute) Addressing
9

● Direct addressing is a mode where the address is

simply contained within the instruction:
● ARM can’t do this because a 32-bit address doesn’t fit
within 32-bit instruction
 Direct Addressing
10

So far, we assumed direct addresses in LDR/STR instructions

e.g. Java: int a, b, c; ... a = b + c;
LDR R0, b
LDR R1, c
ADD R0, R0, R1
STR R0, a
The address, given as a number/label in the instruction encoding, is
used directly to access memory.
 Problems with Direct Addressing
11

● Not very flexible if we want several consecutive data. e.g.

String – get each char in turn
● ARM: both instructions and addresses are 32 bits, but the
instruction also specifies operation, register etc., so it can’t
contain every possible address.
● Solution: allow a register to contain an address, use the
address in the register to do loads and stores.
● This is Register Indirect Addressing
 Immediate Addressing
12

For example
CMP R0, #22
ADD R1, R2, #18
MOV R1, #30
MOV R1, #0xFF
 Register Indirect Addressing
13

● It takes only a few bits to select a register (4 bits in the

case of ARM . . . R0-R15)
● A register can (typically) hold an arbitrary address (32
bits in the case of ARM)
 Register Indirect Addressing
14

ARM has register indirect addressing e.g. loading a register

from a memory location:

LDR R2, =i ; move the address of i into R2

LDR R0, [R2] ; address in R2 for i
 Indirect with Offset
15

The address is calculated from a register value and a literal

The register specifier is

just a few bits
The offset can be ‘fairly
small’
With one register ‘pointer’
any of several variables in
nearby addresses may be
addressed
 Indirect with Offset
16

ARM allows offsets of 12 bits in LDR/STR

This may be added or subtracted, for example:
LDR R0, [R1, #8]
STR R3, [R6, #-0x240]
LDR R7, [R2, #short constant]
This provides a range of ± ∼4 Kbytes around a ‘base’
register - adequate for most purposes.
 Address Arithmetic
17

We can operate on registers, so we can:

● store/load/move addresses
● do arithmetic to calculate addresses
Rather than using e.g. extra ADD instructions, we often use
Base + Offset Addressing
● address addition done within the operand
We have actually been using this all along:
Base = PC register
 Double Register Indirect
18

ARM also allows offsets using a second register

This may be added or subtracted, for example:
LDR R0, [R1, R2]
STR R3, [R6, -R4]
 PC + Offset Addressing
19

start: The PC is the address of the current instruction

LDR R0, =b plus 8 bytes (2 words). This means
LDR R1, [R0]
ADD R2, R1, #5 LDR R0, =b is actually: LDR R0, [PC, #8]
STR R2, [R0]
What effect does the code have?

.data
b: .word 20
c: .word 30

Why does the ARM PC register point to the instruction after the next one to be executed? - Stack Overflow
Integer (word) Array Data
● Similar data can be grouped
together into an array.
● An array stores its contents at
sequential data addresses in
memory.
● Each array element is identified
by a number called its index.
● The number of elements in the
array is called the length of the
array.
Iterating over an array of words
.global _start
_start:
ldr r0, =array1 // array base pointer
mov r1, #0 // offset
mov r2, #0 // loop counter

loop:
cmp r2, #6
bge end
ldr r3, [r0, r1] // read base + offset to reg
add r3, r3, #10 // add 10 to the value
str r3, [r0, r1] // write reg to base + offset
add r2, r2, #1 // inc loop
lsl r1, r2, #2 // calc offset
b loop
end:
svc #0

.data

array1: .word 2,3,11,4,55,6

A note on Incrementing & offsets
Effect of LSL R2, R1, #2
Itr R1 R2 Dec
0 0000 0000 0
1 0001 0100 4
2 0010 1000 8
3 0011 1100 12
4 0100 10000 16
Optimizations
ARM can scale (multiply) the index, add it to the base
address, and load from memory in a single instruction!
Instead of:

We can execute
Also:
Please note
Operations within an instruction. Consider the code

mov r4, #1
lsl r4, r4, #1
ldr r5, [r0, r4, lsl #1]

The highlighted code does not change the value of r4

 Strings
25

● Java:
○ String message= "Hello";
● ARM:
.data
message: .asciz "Hello World!"
 Iterating over an array of "chars"
26

Suppose we want to iterate ocer each character

individually:

for (int i= 0; i<message.length(); i++) {

// do something with this:
message.charAt(i);
}
 Accessing characters: LDRB, STRB
27

LDR R1, =message

LDRB R0, [R1] // fetch 1st byte
LDRB R0, [R1,#1] // fetch 2nd byte
LDRB R0, [R1,#2] // fetch 3rd byte
 get next character from the string
28

for (int i= 0; . . . ; i++) {

System.out.print(message.charAt(i));
}

Use a second register (e.g. R2) to hold i around loop:

 First attempt, no loop
29

MOV R2, #0 //int i= 0

LDR R0, =message //beginning address of ‘message’
...
LDRB R0, [R1,R2] // message.charAt(i) = R1+R2
ADD R2, R2, #1 // i++
...

LDRB Load Register Byte (immediate) loads a byte from

memory, zero-extends it, and writes the result to a register.
 get next character from the string
30

Part way
through
execution
 get next character from the string
31

Optimisation: avoid using both R1 and R2 for addresses

Actually change the address in R1
LDR R1, =message
...
LDRB R0, [R1] // notice R1 is changed
ADD R1, R1, #1 // R1 is incremented
 Question
32

● How do we terminate an iteration over an array of

integers or an array of characters?
● Its always possible to know in advance how many
charactgers are in a string, or how many integers are in
a file
● In character strings, the ARM assembly will convert this:
message: .asciz "Hello World\n"
message: .asciz "Hello World\n0"
33 Indexing Options
3 main types: offset, pre and post
Indexing modes
In addition to scaling the index register, ARM provides
● offset addressing
● pre-indexed addressing
● post-indexed addressing
 get next character from the string
35

● Optimisation: avoid using ADD R1, R1, #1

● Change the address in R1 using “post-indexed ”
operand form
LDR R1, =message
LDRB R0, [R1],#1
 while not at end of string
36

Every Java/C String knows how long it is. But how do we

know in assembly when the end of the string is reached?

.data
message: .asciz "Hello World!0"

Then iterate over the array of characters until 0 is reached.

In C/C++ this is sometimes referred to as the null
character.
 Whole loop
37

LDR R1, =message

loop:
LDRB R0, [R1],#1
CMP R0, #0
BEQ end
B loop
end: // end here
.data
message: .asciz "Hello World!0"
 Further Examples
38
 Question 1
39

Indicate whether the following instructions use offset, pre

or post-indexed addressing modes:

● STR R6, [R4, #4]

● LDR R3, [R12], #6
● LDRB R4, [R3, R2]!
● LDRSH R12, [R6]