Pipelining in Computer

Introduction-
A program consists of several number of instructions.
 These instructions may be executed in the following two ways-

1. Non-Pipelined Execution-
In non-pipelined architecture,

 All the instructions of a program are executed sequentially one after the other.
A new instruction executes only after the previous instruction has executed
completely.
 This style of executing the instructions is highly inefficient.
Example-

Consider a program consisting of three instructions.

In a non-pipelined architecture, these instructions execute one after the other.

If time taken for executing one instruction = t, then-

Time taken for executing ‘n’ instructions = n x t

To improve the performance of a CPU we have two options:

a) Improve the hardware by introducing faster circuits.

b) Arrange the hardware such that more than one operation can be performed at the same
time.

Since, there is a limit on the speed of hardware and the cost of faster circuits is quite high, we
have to adopt the 2nd option.

Pipelining: Pipelining is a process of arrangement of hardware elements of the CPU such

that its overall performance is increased. Simultaneous execution of more than one
instruction takes place in a pipelined processor.

Let us see a real-life example that works on the concept of pipelined operation. Consider a
water bottle packaging plant. Let there be 3 stages that a bottle should pass through, Inserting
the bottle(I), Filling water in the bottle(F), and sealing the bottle(S). Let us consider these
stages as stage 1, stage 2 and stage 3 respectively. Let each stage take 1 minute to complete
its operation.
Now, in a non pipelined operation, a bottle is first inserted in the plant, after 1 minute it is
moved to stage 2 where water is filled. Now, in stage 1 nothing is happening. Similarly, when
the bottle moves to stage 3, both stage 1 and stage 2 are idle. But in pipelined operation,
when the bottle is in stage 2, another bottle can be loaded at stage 1. Similarly, when the
bottle is in stage 3, there can be one bottle each in stage 1 and stage 2. So, after each minute,
we get a new bottle at the end of stage 3. Hence, the average time taken to manufacture 1
bottle is:

Without pipelining = 9/3 minutes = 3m

With pipelining = 5/3 minutes = 1.67m

Thus, pipelined operation increases the efficiency of a system.

In pipelined architecture,

 The hardware of the CPU is split up into several functional units.

 Each functional unit performs a dedicated task.

 The number of functional units may vary from processor to processor.

 These functional units are called as stages of the pipeline.

 Control unit manages all the stages using control signals.

 There is a register associated with each stage that holds the data.

 There is a global clock that synchronizes the working of all the stages.

 At the beginning of each clock cycle, each stage takes the input from its register.

 Each stage then processes the data and feed its output to the register of the next stage.

Design of a basic pipeline

  In a pipelined processor, a pipeline has two ends, the input end and the output end.
Between these ends, there are multiple stages/segments such that output of one stage
is connected to input of next stage and each stage performs a specific operation.

 Interface registers are used to hold the intermediate output between two stages. These
interface registers are also called latch or buffer.

 All the stages in the pipeline along with the interface registers are controlled by a
common clock.

Execution in a pipelined processor

Execution sequence of instructions in a pipelined processor can be visualized using a space-
time diagram. For example, consider a processor having 4 stages and let there be 2
instructions to be executed. We can visualize the execution sequence through the following
space-time diagrams:
 Non overlapped execution:

Total time = 8 Cycle

Overlapped execution:

Total time = 5 Cycle

Pipeline Stages
Reduced Instruction Set Computer (RISC) processor has 5 stage instruction pipeline to
execute all the instructions in the RISC instruction set. Following are the 5 stages of RISC
pipeline with their respective operations:

1. In the first subtask, the instruction is fetched.

2. The fetched instruction is decoded in the second stage.

3. In the third stage, the operands of the instruction are fetched.

4. In the fourth, arithmetic and logical operation are performed on the operands to
execute the instruction.

5. In the fifth stage, the result is stored in memory.

Now, understanding the division of the instruction into subtasks. Let us understand, how the
n number of instructions in a process, are pipelined.

Look at the figure below the 5 instructions are pipelined. The first instruction gets completed
in 5 clock cycle. After the completion of first instruction, in every new clock cycle, a new
instruction completes its execution.

Pipeline for 5 Instructions

Observe that when the Instruction fetch operation of the first instruction is completed in the
next clock cycle the instruction fetch of second instruction gets started. This way the
hardware never sits idle it is always busy in performing some or other operation. But, no two
instructions can execute their same stage at the same clock cycle.
Classifications of Pipelining

In 1977 Handler and Ramamoorthy classified pipeline processors depending on their

functionality.

1. Arithmetic Pipelining

It is designed to perform high-speed floating-point addition, multiplication and division.

Here, the multiple arithmetic logic units are built in the system to perform the parallel
arithmetic computation in various data format. Examples of the arithmetic pipelined
processor are Star-100, TI-ASC, Cray-1, Cyber-205.

2. Instruction Pipelining

Here, the number of instructions are pipelined and the execution of current instruction is
overlapped by the execution of the subsequent instruction. It is also called instruction
lookahead.

3. Processor Pipelining

Here, the processors are pipelined to process the same data stream. The data stream is
processed by the first processor and the result is stored in the memory block. The result in the
memory block is accessed by the second processor. The second processor reprocesses the
result obtained by the first processor and the passes the refined result to the third processor
and so on.

4. Unifunction Vs. Multifunction Pipelining

The pipeline performing the precise function every time is unifunctional pipeline. On the
other hand, the pipeline performing multiple functions at a different time or multiple
functions at the same time is multifunction pipeline.

5. Static vs Dynamic Pipelining

The static pipeline performs a fixed-function each time. The static pipeline is unifunctional.
The static pipeline executes the same type of instructions continuously. Frequent change in
the type of instruction may vary the performance of the pipelining.

Dynamic pipeline performs several functions simultaneously. It is a multifunction pipelining.

Advantages of Pipelining
  The cycle time of the processor is decreased. It can improve the instruction
throughput. Pipelining doesn't lower the time it takes to do an instruction. Rather than,
it can raise the multiple instructions that can be processed together ("at once") and
lower the delay between completed instructions (known as 'throughput').

 If pipelining is used, the CPU Arithmetic logic unit can be designed quicker, but more
complex.

 Pipelining increases execution over an un-pipelined core by an element of the

multiple stages (considering the clock frequency also increases by a similar factor)
and the code is optimal for pipeline execution.

 Pipelined CPUs frequently work at a higher clock frequency than the RAM clock
frequency, (as of 2008 technologies, RAMs operate at a low frequency correlated to
CPUs frequencies) increasing the computer’s global implementation.

Pipelining Hazards

Whenever a pipeline has to stall due to some reason it is called pipeline hazards. Below we
have discussed four pipelining hazards.

1. Data Dependency

Consider the following two instructions and their pipeline execution:

Data Dependency

In the figure above, you can see that result of the Add instruction is stored in the
register R2 and we know that the final result is stored at the end of the execution of the
instruction which will happen at the clock cycle t4.
But the Sub instruction need the value of the register R2 at the cycle t3. So, the Sub
instruction has to stall two clock cycles. If it doesn’t stall it will generate an incorrect result.
Thus, depending of one instruction on other instruction for data is data dependency.

2. Memory Delay

When an instruction or data is required, it is first searched in the cache memory if not found
then it is a cache miss. The data is further searched in the memory which may take ten or
more cycles. So, for that number of cycle the pipeline has to stall and this is a memory
delay hazard. The cache miss, also results in the delay of all the subsequent instructions.

3. Resource Limitation

If the two instructions request for accessing the same resource in the same clock cycle, then
one of the instruction has to stall and let the other instruction to use the resource. This stalling
is due to resource limitation. However, it can be prevented by adding more hardware.

Key Takeaways

 Pipelining divides the instruction in 5 stages instruction fetch, instruction decode,

operand fetch, instruction execution and operand store.

 The pipeline allows the execution of multiple instructions concurrently with the
limitation that no two instructions would be executed at the same stage in the same
clock cycle.

 All the stages must process at equal speed else the slowest stage would become the
bottleneck.

 Whenever a pipeline has to stall for any reason it is a pipeline hazard.

This is all about pipelining. So, basically the pipelining is used to improve the performance of
the system by improving its efficiency.