S.K.P.

ENGINEERING COLLEGE
THIRUVANNAMALAI

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

M.E – APPLIED ELECTRONICS

AP 4152 – ADVANCED DIGITAL SYSTEM DESIGN

LABORATORY

Regulation – 2021

NAME : ……………………………………………
YEAR : ……………………………………………
SEMESTER: ……………………………………………
REG NO:…………………………………………….

S.K.P.ENGINEERING COLLEGE Page 1

 S.K.P. ENGINEERING COLLEGE
THIRUVANNAMALAI

BONAFIDE CERTIFICATE

NAME……………………………………………………………..YEAR……………
SEM ………. … BRANCH……….…………………………………… REGISTER
NO…………………………………….… certified that this bonafide record of work
done by the above Student of the…….………………………… …….laboratory
during the year 2021-2022.

Staff in-charge Head of the Department

Submitted for the practical Examination held on…………………………..

at S.K.P.ENGINEERING COLLEGE, THIRUVANNAMALAI.

INTERNAL EXAMINER EXTERNAL EXAMINIER

S.K.P.ENGINEERING COLLEGE Page 2

 CONTENT

S.NO. DATE NAME OF THE EXPERIMENTS SIGNATURE

PAGE NO.

1.
Design of Universal Shift Register

2.
Design of Finite State Machine

3.
4 Bit synchronous counter using flip flops

4. Design and Implementation of combinational

circuitsusing FPGA

5. Implementation of MAC unit using FPGA

6. Implementation of GCD using Verilog/VHDL

7. Implementation of 8-Bit RISC Processor

8. Simulate the NAND and NOR circuit using

PSPICE circuit simulator

S.K.P.ENGINEERING COLLEGE Page 3

EXP.
NO 1. Design of Universal Shift Register
DATE

AIM:
To develop the source code for the design of universal shift register using VERILOG and
obtainthe simulation, synthesis, place and route and implement into FPGA.

APPARATUS REQUIRED:
● Xilinx.

● Modelsim

PROCEDURE:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using Verilog source code.

Step3: Write the source code in VERILOG.

Step4: Check the syntax and debug the errors if found, obtain the synthesis report.

Step5: Verify the output by simulating the source code.

Step6: Write all possible combinations of input using the test bench.

Step7: Obtain the place and route report.

S.K.P.ENGINEERING COLLEGE Page 4

LOGIC DIAGRAM:

PROGRAM :
Verilog Code:
module usr(clk, clear, sel, p1, p2, p3, p4, seri, sele, q1, q2, q3, q4);
input clk, clear, p1, p2, p3, p4, seri, sele;
input [1:0]sel;
output q1, q2, q3, q4;
mux u1(p4, q3, seri, q4, sel, y4);
mux u2(p3, q2, q4, q3, sel, y3);
mux u3(p2, q1, q3, q2, sel, y2);
mux u4(p1, sele, q2, q1, sel, y1);
dff u5(y4, clk, clear, q4);
dff u6(y3, clk, clear, q3);
dff u7(y2, clk, clear, q2);
dff u8(y1, clk, clear, q1);
endmodule

S.K.P.ENGINEERING COLLEGE Page 5

******************************************************************
module dff(d,clk,clear,q);
input d, clk, clear;
output reg q;
initial begin q = 0;
end

Test Bench:
module usr_tb; reg clk, clear, p1, p2, p3, p4, seri, sele;
reg [1:0] sel;
wire q1, q2, q3, q4;
usr uut(clk, clear, sel, p1, p2, p3, p4, seri, sele, q1, q2, q3, q4);
initial begin clk = 0;
forever #10 clk = ~clk;

end initial begin clear = 1;

sel = 2'b00;

p1 = 0;
p2 = 0;
3 = 0;
p4 = 0;

seri = 0;
sele = 0;
#10
clear = 0;

sel = 2'b11; //pipo

p1 = 1;
p2 = 0;

p3 = 1;
p4 = 0;
#20

S.K.P.ENGINEERING COLLEGE Page 6

sel = 2'b10; //shift left
sele = 1;
#20
sele = 0;
#20 sele = 1;
#20 sele = 0;

#80 sel = 2'b01; //shift right

seri = 1;
#20 seri = 0;

#20 seri = 1;
#20 seri = 0;
end

endmodule

output:

S.K.P.ENGINEERING COLLEGE Page 7

Result:
Thus the output for the design of Universal Shift Register was verified by synthesizing and
simulating the Verilog code.

S.K.P.ENGINEERING COLLEGE Page 8

EXP.
NO 2. Design of Finite State Machine
DATE

AIM:
To develop the source code for Finite State Machine by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.

SOFTWARE REQUIRED:
● Xilinx
● Modelsim

PROCEDURE:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using Verilog source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

S.K.P.ENGINEERING COLLEGE Page 9

PROGRAM:
Verilog Source Code:
module seq_det(sin,clk,reset,y);
input sin,clk,reset;
output y;
reg y;
reg [1:0] r_reg, n_reg;
parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10;
always @(posedge clk or posedge reset)
if (reset) r_reg <= s0;
else r_reg <= n_reg;
always @(r_reg or sin)
if (r_reg==s0 && sin==0) n_reg=s0;
else if (r_reg==s0 && sin==1) n_reg=s1;
else if (r_reg==s1 && sin==0) n_reg=s0;
else if (r_reg==s1 && sin==1) n_reg=s2;
else if (r_reg==s2 && sin==0) n_reg=s0;
else if (r_reg==s2 && sin==1) n_reg=s2;
always @(r_reg or sin)
if (r_reg==s2 && sin==0) y=1;
else y=0;
endmodule

Test Bench:
module seq_det_tb;
reg sin,clk,reset;
wire y;
seq_det d1(sin,clk,reset,y);
initial
begin
clk = 1'b0;
repeat (41) #5 clk = ~clk;
end
initial
begin
$monitor($time,"sin=%b,clk=%b,reset=%b,y=%b", sin, clk, reset, y);
reset = 1;
sin=0;
#10 reset =0;
#10 sin = 1;
#10 sin = 0;
#10 sin = 1;
#10 sin = 1;
#10 sin = 0;
#10 sin = 0;
#10 sin = 1;
#10 sin = 1;
S.K.P.ENGINEERING COLLEGE Page 10
 #10 sin = 0;
#10 sin = 1;

end
endmodule

Verilog Source Code:

module seq_det_moore(sequence_in,clock,reset,detector_out );
input clock;
input reset;
input sequence_in;
output reg detector_out;
parameter Zero=3'b000, One=3'b001, OneZero=3'b011,
OneZeroOne=3'b010,OneZeroOneOne=3'b110;
reg [2:0] current_state, next_state;
always @(posedge clock, posedge reset)
begin
if(reset==1)
current_state <= Zero;
else
current_state <= next_state;
end
always @(current_state,sequence_in)
begin
case(current_state) Zero:
begin
if(sequence_in==1)
next_state = One;
else
next_state = Zero;
end
One:
begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = One;
end OneZero: begin
if(sequence_in==0)
next_state = Zero;
else
next_state = OneZeroOne;
end
OneZeroOne:
begin
if(sequence_in=
=0)
next_state =
S.K.P.ENGINEERING COLLEGE Page 11
 OneZero;else
next_state = OneZeroOneOne;
end
OneZeroOneOne:be
gin
if(sequence_in==0)
next_state = OneZero;

S.K.P.ENGINEERING COLLEGE Page 12

else
next_state = One;
end
default:
next_state = Zero;
end
case
end
always @(current_state)
begin case(current_state) Zero:
detector_out = 0;
One: detector_out = 0;
OneZero: detector_out = 0;
OneZeroOne: detector_out = 0;
OneZeroOneOne: detector_out = 1;
default: detector_out = 0;
endcase
end
endmodule

Test Bench:

module seq_det_moore_tb;
reg sequence_in;
reg clock; reg reset;
wire detector_out;
seq_det_moore uut(sequence_in,clock,reset,detector_out );
initial begin clock = 0;
forever #5 clock = ~clock;
end
initial
begin
sequence_in = 0;
reset = 1;
#30;
reset = 0;
#20;
sequence_in = 1;
#20; sequence_in = 1;
#10; sequence_in = 0;
#10; sequence_in = 1;
#20; sequence_in = 0;
#20; sequence_in = 1;
#20; sequence_in = 0;
End endmodule

S.K.P.ENGINEERING COLLEGE Page 13

OUTPUT:

RESULT:

Thus the outputs of finite state machine are verified by synthesizing and simulating the
Verilog code.

S.K.P.ENGINEERING COLLEGE Page 14

EXP
NO 3 4 Bit synchronous counter using flip flops
DATE

AIM:
To develop the layout design for 4 bit synchronous counter using D flip flop by Microwind
andobtain the simulation results.

SOFTWARE REQUIRED:
● Xilinx
● Modelsim

S.K.P.ENGINEERING COLLEGE Page 15

Logic Diagram:

S.K.P.ENGINEERING COLLEGE Page 16

Layout Design:

S.K.P.ENGINEERING COLLEGE Page 17

Output:
Voltage vs Time:

S.K.P.ENGINEERING COLLEGE Page 18

RESULT:
Thus the layout of 4 bit synchronous counter using flip flop are designed and outputs are
verified by using Microwind tools.

S.K.P.ENGINEERING COLLEGE Page 19

EXP.
NO 4.
DESIGN AND IMPLEMENTATION OF COMBINATIONAL
DATE CIRCUITS USING FPGA

AIM:
To implement a combinational circuits using FPGA.

SOFTWARES REQUIRED:

 Xilinx.Modelsim.
 TOOLS REQUIRED: FPGA kit.

ALGORITHM:

HALF ADDER:
Step 1: Start the program.
Step 2: Declare the input ports a, b.
Step 3: Declare output ports s, c.
Step 4: Begin the process using behavioral architecture.
Step 5:.Assign s=a b.
Step 6: Assign c=a.b.
Step 7: End the process.

FULL ADDER:
Step 1: Start the program.
Step 2: Declare the input ports a, b, cin.
Step 3: Declare the output ports s, cy.
Step 4: Begin the process using behavioral architecture.
Step 5: Assign s= a b cin. Assign cy= (a.b) + (b.cin) + (cin.a).
Step 6: End the process.

S.K.P.ENGINEERING COLLEGE Page 20

THEORY:

HALF ADDER:

The half adder operation needs two binary inputs, augends and addend bits and two binary
outputs are sum and carry. Sum= a b. Carry=ab. In multi-digit addition, we have to add two bytes
along with the carry of the previous digit addition. Effectively such addition requires addition of
three bits. This is not possible with the half adder.

FULL ADDER:

Full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of three inputs and two outputs. Two of the input variables denoted by A and B, represent
the two significant bits to be added. The third input Cin represents the carry from the previous
lower significant position.
__ _ _ _ _ _
Sum= A.B. Cin+ A.B. Cin+ A.B. Cin+ A.B. Cin.
Cin= Cin (A B)
Cout=A.B+A.Cin+B.Cin

S.K.P.ENGINEERING COLLEGE Page 21

PROGRAM: HALF ADDER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ha is
Port ( a,b : in STD_LOGIC;
s,c : out STD_LOGIC);
end ha;
architecture Behavioral of ha is
begin
s<=a XOR b;
c<=a AND b;
end Behavioral;

FULL ADDER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full is Port ( a,b,cin : in STD_LOGIC;
s,cy : out STD_LOGIC);
end full;
architecture Behavioral of full is
begin s<=a xor b xor cin;
cy<=(a and b)or(b and cin)or(cin and a);
end Behavioral;

S.K.P.ENGINEERING COLLEGE Page 22

 RTL SCHEMATIC:

HALF ADDER

FULL ADDER

RESULT:
Thus the combinational circuit was designed and implemented using FPGA and its
truth table was verified.

S.K.P.ENGINEERING COLLEGE Page 23

EXP.
NO 5.
IMPLEMENTATION OF MAC UNIT USING FPGA
DATE

AIM:

To implement MAC unit using FPGA.

SOFTWARE REQUIRED:

 Xilinx

TOOLS REQUIRED:

 FPGA kit

ALGORITHM:

Step 1: Start the program.

Step 2: Declare the input variables.
Step 3: When x1=1 arithmetic operation. Step
4: When x1=0 logical operation.
Step 5: Example:When x1=1,s1=1,s2=1 and s3=1 it gives invalid Output
using conditional operator.
Step 6: Example:When x1=0,s1=1,s2=1 and s3=0 it gives 2’s Compliment Output
using conditional operator.Similarly for Everyother input values.
Step 7: Stop the program.

THEORY:

In the majority of digital signal processing (DSP) applications the critical operations
usually involve many multiplications and/or accumulations. For real-time signal processing, a
high speed and high throughput Multiplier Accumulator (MAC) is always a key to achieve a
high performance digital signal processing system. In the last few years, the main consideration
of MAC design is to enhance its speed. This is because; speed and throughput rate is always the
concern of digital signal processing system.

But for the epoch of personal communication, low power design also becomes another
main design consideration. This is because; battery energy available for these portable products
limits the power consumption of the system. Therefore, the main motivation of this work is to

S.K.P.ENGINEERING COLLEGE Page 24

investigate various VLSI Design and Implementation of Low Power MAC Unit with Block
Enabling Technique.

PROGRAM:

module MAC(clk,rst,a,b,z);
input clk,rst;
input[2:0] a,b;
output z;
wire[5:0] w;
multiplier U1(.a(a),.b(b),.p(w));
pipo U2(.RIN(w),.clk(clk),.rst(rst),.ROUT(z));
endmodule
module multiplier(a,b,p);
input[2:0] a,b;
output[5:0] p;
wire[7:0] u;
wire[1:0] su;
wire[8:0] i;
and(p[0],a[0],b[0]);
and(u[0],a[1],b[0]);
and(u[1],a[2],b[0]);
and(u[2],a[0],b[1]);
and(u[3],a[1],b[1]);
and(u[4],a[2],b[1]);
and(u[5],a[0],b[2]);
and(u[6],a[1],b[2]);
and(u[7],a[2],b[2]);
hadd h1(.l(u[0]),.m(u[2]),.sum(p[1]),.cry(i[0]));
hadd h2(.l(i[0]),.m(u[1]),.sum(su[0]),.cry(i[1]));
hadd h3(.l(u[3]),.m(u[5]),.sum(su[1]),.cry(i[2]));
hadd h4(.l(su[0]),.m(su[1]),.sum(p[2]),.cry(i[6]));
hadd h5(.l(i[1]),.m(i[2]),.sum(i[5]),.cry(i[6]));
or(i[7],i[5],i[4]);
fadd f3(.d(i[7]),.e(u[4]),.cin(u[6]),.s(p[3]),.cout(i[8]));
fadd f4(.d(i[8]),.e(i[6]),.cin(u[7]),.s(p[4]),.cout(p[5]));
endmodule
module pipo(RIN,clk,rst,ROUT);
input[5:0] RIN;
input clk,rst; output[5:0]
ROUT; reg[5:0] ROUT;
always @(posedge clk or negedge rst) begin
if(!rst)
begin
ROUT<=6'b000000;

S.K.P.ENGINEERING COLLEGE Page 25

 end else
begin
ROUT<=RIN;
end
end
endmodule
module fadd(s,cout,d,e,cin); input
d,e,cin;
output s,cout; assign
s=(d^e^cin);
assign cout=((d&e)|(e&cin)|(d&cin));
endmodule
module hadd(sum,cry,l,m); input
l,m;
output sum,cry; wire
sum,cry; assign
sum=(l^m); assign
cry=(l&m); endmodule

RESULT:

Thus the MAC unit was implemented using FPGA

S.K.P.ENGINEERING COLLEGE Page 26

EXP.
NO 6. IMPLEMENTATION OF GCD UNIT USING VERILOG/VHDL
DATE

AIM:

To implement GCD unit using Verilog/VHDL

SOFTWARE REQUIRED:

 Verilog/VHDL

PROGRAM:

module GCD(clk, rst, start, A, B, done, result, ERROR);

input clk, rst, start;
input [31:0] A, B;
output done, ERROR;
output [31:0] result;
wire startGCD, doneGCD, startDiv, doneDiv;
wire [31:0] dividend, divisor, quotient, remainder;
wire [3:0] stateGCD;
assign done = doneGCD;

Datapath dp(clk, startDiv, doneDiv, dividend, divisor, quotient, remainder);

masterFSM mf(clk, rst, start, doneGCD, startGCD, done);

GCDFSM gf(clk, rst, startGCD, doneGCD, startDiv, doneDiv, A, B, dividend, divisor,

quotient, remainder, result, ERROR);
endmodule

module Datapath(clk, startDiv, doneDiv, dividend, divisor, quotient, remainder);

input clk, startDiv;
input [31:0] dividend, divisor;

S.K.P.ENGINEERING COLLEGE Page 27

 output doneDiv;

output [31:0] quotient, remainder;

divider32 d32(clk, startDiv, dividend, divisor, quotient, remainder, doneDiv); endmodule

// define stateGCD

`define WAIT 4'b0000

`define LOAD 4'b0001
`define JUDGE 4'b0010
`define DIVIDE0 4'b0011

`define DIVIDE1 4'b0100

`define CHANGE 4'b0101
`define RESULT 4'b0110

`define ERROR 4'b0111

`define DONE 4'b1000
`define DELAY0 4'b1001
`define DELAY1 4'b1010

module GCDFSM(clk, rst, startGCD, doneGCD, startDiv, doneDiv, A, B, dividend, divisor,

quotient, remainder, result, ERROR);
input clk, rst, startGCD, doneDiv;
input [31:0] A, B, quotient, remainder;

output reg doneGCD, startDiv, ERROR;

output reg [31:0] dividend, divisor, result;

reg [3:0] stateGCD;

reg [3:0] nsGCD;

reg [31:0] nextDividend, nextDivisor;
reg [2:0] delay;

always @(posedge clk or posedge rst) begin

if (rst) stateGCD <= `WAIT;
else stateGCD <= nsGCD;

S.K.P.ENGINEERING COLLEGE Page 28

end
always @(*) begin
case (stateGCD)
`WAIT: begin

nsGCD = startGCD ? `LOAD : `WAIT;

doneGCD = 1'b0;
startDiv = 1'b0;
ERROR = 1'b0;

result = 0;
end
`LOAD: begin
$display("state: LOAD");
$display("load A = %d, B = %d", A, B);

nsGCD = `CHANGE;
nextDividend = (A > B) ? A : B;
nextDivisor = (A < B) ? A : B;

if (nextDivisor == 0) begin

// ERROR, need some delay

delay = 7;
nsGCD = `DELAY0;
end
end
`JUDGE: begin

$display("state: JUDGE");
// check if divisor == 1 or 0
$display("JUDGE, divisor = %d", divisor);
nsGCD = `DIVIDE0;

if (divisor == 0 || divisor == 1) begin

nsGCD = `RESULT;
S.K.P.ENGINEERING COLLEGE Page 29
 end
end
`DIVIDE0: begin
$display("state: DIVIDE0");
startDiv = 1'b1;
nsGCD = `DIVIDE1;
end
`DIVIDE1: begin

$display("state: DIVIDE1");
startDiv = 1'b0;
nsGCD = (doneDiv) ? `CHANGE : `DIVIDE1;
if (doneDiv) begin

nextDividend = divisor;
nextDivisor = remainder;
$display("quotient = %d, remainder = %d", quotient, remainder);
end
end
`CHANGE: begin

$display("state: CHANGE");
dividend = nextDividend;
divisor = nextDivisor;
nsGCD = `JUDGE;

$display("changed, dividend = %d, divisor = %d", dividend, divisor);

end
`RESULT: begin

$display("state: RESULT");
result = (divisor == 1) ? 1 : dividend;
nsGCD = `DONE;

end
S.K.P.ENGINEERING COLLEGE Page 30
 `ERROR: begin
$display("state: ERROR");
$display("ERROR");

ERROR = 1'b1;

nsGCD = `DONE;

end
`DONE: begin
$display("state: DONE");
doneGCD = 1'b1;

nsGCD = `WAIT;

end
`DELAY0: begin

$display("state: DELAY0, %d", delay);

nsGCD = (delay > 0) ? `DELAY1 : `ERROR;
end
`DELAY1: begin

$display("state: DELAY1");
delay = delay - 1;
nsGCD = `DELAY0;
end
default: begin
nsGCD = `WAIT;

end
endcase
end
endmodule

module masterFSM(clk, rst, start, doneGCD, startGCD, done);

S.K.P.ENGINEERING COLLEGE Page 31

input clk, rst, start, doneGCD;
output startGCD, done;
reg state, ns;
reg startGCD, done;
parameter idle = 1'b0;

parameter gcd = 1'b1;

always @(posedge clk or posedge rst) begin

if (rst) state <= idle;
else state <= ns;
end
always @(*) begin
case (state)
idle: begin
startGCD = 1'b0;
done = 1'b0;
ns = idle;
if (start) begin
startGCD = 1'b1;
ns = gcd;

end
end
default : begin
startGCD = 1'b0;
done = 1'b0;
ns = gcd;

if (doneGCD) begin
ns = idle;
done = 1'b1;
end
S.K.P.ENGINEERING COLLEGE Page 32
 end
endcase
end
endmodule

define SUB 4'b0101

module divider32(clk, start, dividend, divisor, quotient, remainder, done);

input clk, start;

input [31:0] dividend, divisor;output done;

output [31:0] quotient, remainder;

reg [31:0] quotient, remainder;
reg done;

//expand dividend and divisor,

reg [63:0] long_dividend;
reg [63:0] long_divisor;

reg [4:0] state;

reg inner_start;
wire [63:0] differ;
wire dontcare;

// finite state machine

always @(posedge clk or posedge start) begin

if (start) begin
state = 0;

inner_start = 1;
end
else if (clk) begin
state = state + 1;

end

S.K.P.ENGINEERING COLLEGE Page 33

 end

ALU64 sub(long_dividend, long_divisor, 1'b0, `SUB, differ, dontcare, dontcare, dontcare,

dontcare);

// Datapath

always @(*) begin

if (state == 0) begin
long_dividend = {{32{1'b0}}, dividend};
long_divisor = {divisor, {32{1'b0}}};
quotient = 0;

remainder = 0;
end
long_divisor = long_divisor >> 1;
quotient = quotient << 1;

done = 0;
if (long_dividend >= long_divisor) begin
long_dividend = long_dividend - long_divisor;

quotient = quotient + 1;

end
if (state == 31) begin
remainder = long_dividend[31:0];
if (inner_start) begin
inner_start = 0;
done = 1;

end
end

end
endmodule

S.K.P.ENGINEERING COLLEGE Page 34

FLOWCHART:

S.K.P.ENGINEERING COLLEGE Page 35

OUTPUT:

RESULT:

Thus the GCD was implemented using Verilog/VHDL

S.K.P.ENGINEERING COLLEGE Page 36

EXP.
NO 7. IMPLEMENTATION OF 8-BIT RISC PROCESSOR
DATE

AIM:

To implement 8-Bit RISC processor using Verilog/ VHDL

SOFTWARE REQUIRED:

 Verilog/VHDL
PROGRAM:

module testbench;
reg clk, reset;
initial
begin
clk = 1'b0;

reset = 1'b1;
reset = #161 1'b0;
end
always clk = #5 ~clk;
processor_top proc_top1(clk, reset);
endmodule
module processor_top (clk, reset);
input clk, reset;

wire clk, store_to_mem,reg_wr_en;

wire [9:0] prog_ctr;
wire [15:0] instr_mem_out;
wire [2:0] op1_addr, op2_addr,destination_reg_addr;
wire [7:0] op1_rd_data, op2_rd_data, mem_data;

S.K.P.ENGINEERING COLLEGE Page 37

 wire [7:0] data_rd_addr, data_wr_addr;
wire [7:0] datamem_rd_data, datamem_wr_data;

wire [7:0] operation_result;

instr_and_data_mem mem1(clk, prog_ctr,

instr_mem_out, data_rd_addr, data_wr_addr,
datamem_rd_data, datamem_wr_data,
store_to_mem);

processor_core proc1(clk,reset,op1_rd_data,op2_rd_data, instr_mem_out,op1_addr,

op2_addr,prog_ctr, store_to_mem, reg_wr_en, data_rd_addr, data_wr_addr, datamem_rd_data,
datamem_wr_data, operation_result, destination_reg_addr );

register_file regfile1(clk, reset, datamem_wr_data, op1_rd_data, op2_rd_data, op1_addr,

op2_addr, destination_reg_addr, reg_wr_en);
endmodule
module instr_and_data_mem (clk, prog_ctr, instr_mem_out, data_rd_addr, data_wr_addr,
datamem_rd_data, datamem_wr_data, store_to_mem);

input clk;
input [9:0] prog_ctr;
input [7:0] data_rd_addr, datamem_wr_data;
input [7:0] data_wr_addr;

input store_to_mem;
output [15:0] instr_mem_out;
output [7:0] datamem_rd_data;
reg [15:0] instr_mem_out;
reg [7:0] datamem_rd_data;
// instruction memory operations

reg [15:0] instr_mem[0:1023];

// load program into memory
initial
begin

S.K.P.ENGINEERING COLLEGE Page 38

 $readmemh("C:/Users/ekstep1/Desktop/verlog/run/program2.txt",instr_mem);
end

// read instructions from memory

always @(posedge clk)
instr_mem_out <= #1 instr_mem[prog_ctr];
// data memory operations
reg [7:0] data_mem[255:0];
// initialize data memory from file
initial
begin

$readmemh("C:/Users/ekstep1/Desktop/verlog/run/data2.txt",data_mem);
end

// get data during LOAD instruction

always @(data_rd_addr)
datamem_rd_data <= data_mem[data_rd_addr];

// write to data memory in STORE instruction

always @(posedge clk)
if (store_to_mem == 1'b1)
data_mem[data_wr_addr] <= datamem_wr_data;
endmodule

module processor_core (clk,reset,op1_rd_data,op2_rd_data,

instr_mem_out,op1_addr,op2_addr,prog_ctr,store_to_mem, reg_wr_en, data_rd_addr, data_wr_addr,
datamem_rd_data, datamem_wr_data, operation_result,destination_reg_addr);

input clk, reset;

input [7:0] op1_rd_data, op2_rd_data;
input [7:0] datamem_rd_data;
input [15:0] instr_mem_out;

S.K.P.ENGINEERING COLLEGE Page 39

output [2:0] op1_addr, op2_addr;

output [9:0] prog_ctr;

output [7:0] datamem_wr_data;

output [7:0] data_rd_addr, data_wr_addr;
output [7:0] operation_result;

output [2:0] destination_reg_addr;

output store_to_mem, reg_wr_en;
reg [2:0] op1_addr, op2_addr, op1_addr_reg , op2_addr_reg;
reg [9:0] branch_addr,prog_ctr,nxt_prog_ctr;

reg [9:0] nxt_prog_ctr_reg, nxt_prog_ctr_r2;

reg [7:0] op1_data_reg, op2_data_reg;
reg [7:0] operation_result,data_rd_addr;

reg [15:0] instruction;

reg [4:0] opcode;
reg [7:0] ld_mem_addr;
reg [7:0] data_wr_addr;
reg [2:0] destination_reg_addr ;
reg [7:0] logical_data_out;

reg [7:0] data_in1,data_in2;

reg [7:0] ld_mem_addr_reg;
reg [7:0] alu_data_out,shift_data_out;
reg [7:0] data_out_reg, res_addr, res_addr_reg;
reg [7:0] st_mem_addr, st_mem_addr_reg;

reg add_op_true, carry_in, en_op2_complement;

reg and_op_true, or_op_true, not_op_true;
reg jump_true, shift_left_true,store_to_mem_ex ;
reg add_op_true_reg, carry_in_reg;

reg en_op2_complement_reg,jump_true_reg;

S.K.P.ENGINEERING COLLEGE Page 40

reg and_op_true_reg,or_op_true_reg,not_op_true_reg;
reg shift_left_true_reg;
reg set_invalidate_instruction;
reg carry_flag, save_carry_flag_reg;
reg lgcl_or_bitwse_T;
reg lgcl_or_bitwse_T_reg;

reg load_true, store_true;

reg write_to_regfile, write_to_regfile_reg;
reg store_true_reg, load_true_reg;
reg alu_carry_out, shift_carry_out;
reg load_mem_data;
reg bypass_op1_ex_stage, bypass_op2_ex_stage;
reg bypass_op1_dcd_stage, bypass_op2_dcd_stage;
reg and_bitwise_true_reg, branch_taken_reg;

reg and_bitwise_true, or_bitwise_true_reg;

reg or_bitwise_true, not_bitwsie_true_reg;

reg not_bitwise_true, not_bitwise_true_reg;

reg invalidate_fetch_instr;
reg invalidate_decode_instr_r1;

reg invalidate_fetch_instr_r2;
reg invalidate_decode_instr,reg_wr_en_ex;
reg invalidate_fetch_instr_r1;
reg invalidate_execute_instr,carry_flag_ex;
reg gt_flag_ex_reg, gt_flag;
reg lt_flag_ex_reg, lt_flag, unconditional_jump;

reg eq_flag_ex_reg, eq_flag, unconditional_jump_reg;

reg compare_true, compare_true_reg, compare_true_r2;
reg jump_gt, jump_lt, jump_eq, jump_carry;

reg jump_gt_reg, jump_lt_reg, jump_eq_reg;

S.K.P.ENGINEERING COLLEGE Page 41
 reg jump_carry_reg;
wire [7:0] datamem_wr_data, data_out;
wire [7:0] operand1, operand2;

wire [7:0] op1_data, op2_data, branch_taken;

wire carry_out,save_carry_flag;
wire invalidate_instr, store_to_mem, reg_wr_en;
wire gt_flag_ex, lt_flag_ex, eq_flag_ex;

wire gt_flag_true, lt_flag_true, eq_flag_true;

wire carry_flag_true;
//****************************************
// RESET INITIALUZATION
//****************************************
//keep instruction and program counter at zero during reset
//Disable register and memory writes during reset
always @(reset)

if (reset == 1'b1)
begin
prog_ctr <= 10'b0;
instruction <= 16'b0;
end
//****************************************
// INSTRUCTION FETCH PIPELINE REGISTERS
//****************************************

always @(posedge clk)

if (reset == 1'b1)
begin

instruction <= 16'b0;

invalidate_fetch_instr <= 1'b0;
S.K.P.ENGINEERING COLLEGE Page 42
 end

else
begin
instruction <= #1 instr_mem_out;
if (branch_taken_reg == 1'b1)

invalidate_fetch_instr <= #1 1'b1;

else

invalidate_fetch_instr <= #1 1'b0;

end

//***************************
// INSTRUCTION DECODE LOGIC
//****************************
always@(instruction)
begin

opcode<= instruction[15:11];
op1_addr <= instruction[2:0];
op2_addr <= instruction[6:4];
res_addr <= instruction[10:8];
ld_mem_addr <= instruction[7:0];
st_mem_addr <= instruction [10:3];
branch_addr <= instruction[9:0];
end

always@ (opcode or branch_addr)

begin
add_op_true <= 1'b0;
and_op_true <= 1'b0;

or_op_true <= 1'b0;

S.K.P.ENGINEERING COLLEGE Page 43
not_op_true <= 1'b0;

carry_in <= 1'b0;

en_op2_complement <= 1'b0;

jump_true <= 1'b0;
compare_true <= 1'b0;
shift_left_true <= 1'b0;
lgcl_or_bitwse_T <= 1'b0;
load_true <= 1'b0;
store_true <= 1'b0;
write_to_regfile <= 1'b0;
unconditional_jump <= 1'b0;

jump_gt <= 1'b0;

jump_lt <= 1'b0;

jump_eq <= 1'b0;

jump_carry <= 1'b0;

case (opcode)
// OP_NOP:
// 5'h00: ;

// OP_ADD: begin
5'h01: begin
write_to_regfile <= 1'b1;

add_op_true <= 1'b1;

end

S.K.P.ENGINEERING COLLEGE Page 44

// OP_SUB: begin
5'h02: begin
add_op_true <= 1'b1;
carry_in <= 1'b1;

en_op2_complement <= 1'b1;

write_to_regfile <= 1'b1;

end
// OP_AND: begin
5'h03: begin
and_op_true <= 1'b1;
lgcl_or_bitwse_T <= 1'b1;

write_to_regfile <= 1'b1;

end

// OP_OR: begin
5'h04: begin
or_op_true <= 1'b1;
lgcl_or_bitwse_T <= 1'b1;

write_to_regfile <= 1'b1;

end
// OP_NOT: begin
5'h05: begin
not_op_true <= 1'b1;
lgcl_or_bitwse_T <= 1'b1;
write_to_regfile <= 1'b1;
end

// OP_SHL begin
5'h06: begin
shift_left_true <= 1'b1;

S.K.P.ENGINEERING COLLEGE Page 45

 write_to_regfile <= 1'b1;
end

// OP_JMP: begin
5'h07: begin
nxt_prog_ctr <= branch_addr;
jump_true <= 1'b1;

unconditional_jump <= 1'b1;

end

// OP_LOAD: begin
5'h08: begin
load_true <= 1'b1;
write_to_regfile <= 1'b1;

end
// OP_STORE: store_true <= 1'b1;

5'h09: store_true <= 1'b1;

// OP_ANDBIT: begin
5'h0a: begin

and_bitwise_true <= 1'b1;

lgcl_or_bitwse_T <= 1'b1;
write_to_regfile <= 1'b1;

end
// OP_ORBIT: begin
5'h0b: begin

or_bitwise_true <= 1'b1;

lgcl_or_bitwse_T <= 1'b1;
write_to_regfile <= 1'b1;

S.K.P.ENGINEERING COLLEGE Page 46

 end
// OP_NOTBIT: begin
5'h0c: begin

not_bitwise_true <= 1'b1;

lgcl_or_bitwse_T <= 1'b1;
write_to_regfile <= 1'b1;
end
// OP_COMPARE: begin
5'h0d: begin

add_op_true <= 1'b1;

compare_true <= 1'b1;
carry_in <= 1'b1; //subtract
en_op2_complement <= 1'b1;
end
// OP_JMPGT: begin
5'h0e: begin
nxt_prog_ctr <= branch_addr;
jump_true <= 1'b1;

jump_gt <= 1'b1;

end
// OP_JMPLT: begin
5'h0f: begin

nxt_prog_ctr <= branch_addr;

jump_true <= 1'b1;

jump_lt <= 1'b1;

end
// OP_JMPEQ: begin
5'h10: begin

S.K.P.ENGINEERING COLLEGE Page 47

 nxt_prog_ctr <= branch_addr;
jump_true <= 1'b1;
jump_eq <= 1'b1;

end
// OP_JMPC: begin
5'h11: begin
nxt_prog_ctr <= branch_addr;
jump_true <= 1'b1;

jump_carry <= 1'b1;

end
default: ; //= NOP
endcase
end

//BYPASS logic
//check store pipeline stage signals and address to determine
// if one of the operands have to be bypassed

always @(op1_addr or destination_reg_addr or reg_wr_en or load_true)

begin
if ((op1_addr == destination_reg_addr) && (reg_wr_en == 1'b1) && (load_true == 1'b0))
bypass_op1_dcd_stage <= 1'b1;

else
bypass_op1_dcd_stage <= 1'b0;

end

S.K.P.ENGINEERING COLLEGE Page 48

always @(op2_addr or destination_reg_addr or reg_wr_en or load_true)

begin

if ((op2_addr == destination_reg_addr) && (reg_wr_en == 1'b1) && (load_true == 1'b0))

bypass_op2_dcd_stage <= 1'b1;
else
bypass_op2_dcd_stage <= 1'b0;
end

S.K.P.ENGINEERING COLLEGE Page 49

assign op1_data = bypass_op1_dcd_stage ? datamem_wr_data : op1_rd_data;
assign op2_data = bypass_op2_dcd_stage ? datamem_wr_data : op2_rd_data;
//**********************************************************
// INSTRUCTION DECODE AND OPERAND FETCH PIPELINE REGISTERS
//***********************************************************

always @(posedge clk)

begin

add_op_true_reg <= #1 add_op_true;

or_op_true_reg <= #1 or_op_true;
not_op_true_reg <= #1 not_op_true;
and_bitwise_true_reg <= #1 and_bitwise_true;
or_bitwise_true_reg <= #1 or_bitwise_true;
not_bitwise_true_reg <= #1 not_bitwise_true;
and_op_true_reg <= #1 and_op_true;
or_op_true_reg <= #1 or_op_true;
not_op_true_reg <= #1 not_op_true;
carry_in_reg <= #1 carry_in;
en_op2_complement_reg <= #1 en_op2_complement;
nxt_prog_ctr_reg <= #1 nxt_prog_ctr;
jump_true_reg<= #1 jump_true;

compare_true_reg <= #1 compare_true;

op1_data_reg <= #1 op1_data ;
op2_data_reg <= #1 op2_data ;

shift_left_true_reg <= #1 shift_left_true;

lgcl_or_bitwse_T_reg <= #1 lgcl_or_bitwse_T;
store_true_reg <= #1 store_true;

S.K.P.ENGINEERING COLLEGE Page 50

 load_true_reg <= #1 load_true;
write_to_regfile_reg <= #1 write_to_regfile;
ld_mem_addr_reg <= #1 ld_mem_addr;
st_mem_addr_reg <= #1 st_mem_addr;
invalidate_fetch_instr_r1 <= #1 invalidate_fetch_instr;

jump_gt_reg <= #1 jump_gt;

jump_lt_reg <= #1 jump_lt;
jump_eq_reg <= #1 jump_eq;

jump_carry_reg <= #1 jump_carry;

unconditional_jump_reg <= #1 unconditional_jump;

end
always @(posedge clk)
if (reset == 1'b1)
begin

op1_addr_reg <= 3'b000;

op2_addr_reg <= 3'b000;
res_addr_reg <= 3'b000;
invalidate_decode_instr <= 1'b0;
end
else
begin

op1_addr_reg <= #1 op1_addr;

op2_addr_reg <= #1 op2_addr;
res_addr_reg <= #1 res_addr;
if (branch_taken_reg == 1'b1)
invalidate_decode_instr <= #1 1'b1;
else
invalidate_decode_instr <= #1 1'b0;
end

S.K.P.ENGINEERING COLLEGE Page 51

//*********************
//EXECUTION UNIT LOGIC
//*********************

//BYPASS logic

//check store pipeline stage signals and address to determine

// if one of the operands have to be bypassed

always @(op1_addr_reg or destination_reg_addr or reg_wr_en or op2_addr_reg or load_true_reg)

begin

if ((op1_addr_reg == destination_reg_addr) && (reg_wr_en == 1'b1) && (load_true_reg == 1'b0))

bypass_op1_ex_stage <= 1'b1;
else
bypass_op1_ex_stage <= 1'b0;
if ((op2_addr_reg == destination_reg_addr) && (reg_wr_en == 1'b1) && (load_true_reg == 1'b0))
bypass_op2_ex_stage <= 1'b1;
else

bypass_op2_ex_stage <= 1'b0;

end
assign operand1 = bypass_op1_ex_stage ? datamem_wr_data : op1_data_reg;
assign operand2 = bypass_op2_ex_stage ? datamem_wr_data : op2_data_reg;

// add zero to operand 1 to pass data to store results stage

// in STORE instructions
always @(operand1 or operand2 or en_op2_complement_reg or store_true_reg or add_op_true_reg
or lgcl_or_bitwse_T_reg or shift_left_true_reg)
begin
data_in1 <= operand1;
if (store_true_reg == 1'b1)

S.K.P.ENGINEERING COLLEGE Page 52

 data_in2 <= 8'b0;

else if (en_op2_complement_reg == 1)
data_in2 <= ~operand2;
else
data_in2 <= operand2;
end
//Instruction execution
//ALU and store instructionss
always @(data_in1 or data_in2 or carry_in_reg)
{alu_carry_out, alu_data_out} <= data_in1 + data_in2

+ carry_in_reg;
// Compare instruction
assign gt_flag_ex = (alu_carry_out == 1'b1) && (alu_data_out != 8'b0) && (compare_true_reg ==
1'b1);

assign lt_flag_ex = (alu_carry_out == 1'b0) && (alu_data_out != 8'b0) && (compare_true_reg ==

1'b1);
assign eq_flag_ex = (alu_data_out == 8'b00) && (compare_true_reg == 1'b1);
//Shift Left

always @(data_in1)
begin
shift_carry_out <= data_in1[7];
shift_data_out <= {data_in1[6:0], 1'b0};

end

// Logical and bitwiseinstructions

always @(and_op_true_reg or or_op_true_reg or not_op_true_reg or and_bitwise_true_reg or
or_bitwise_true_reg or not_bitwise_true_reg or data_in1 or data_in2 )

if (and_op_true_reg == 1'b1)

logical_data_out <= data_in1 && data_in2;

else if (or_op_true_reg == 1'b1)

S.K.P.ENGINEERING COLLEGE Page 53

 logical_data_out <= data_in1 || data_in2;
else if (not_op_true_reg == 1'b1)

logical_data_out <= ! data_in1;

else if (and_bitwise_true_reg == 1'b1)
logical_data_out <= data_in1 & data_in2;
else if (or_bitwise_true_reg == 1'b1)

logical_data_out <= data_in1 | data_in2;

else logical_data_out <= ! data_in1; //defaault is NOT op
//merge results
assign data_out = (add_op_true_reg || store_true_reg) ? alu_data_out :
(lgcl_or_bitwse_T_reg ? logical_data_out : shift_data_out);

assign carry_out = add_op_true_reg ? alu_carry_out : shift_carry_out;

assign save_carry_flag = (add_op_true_reg && !compare_true_reg) || shift_left_true_reg;

// BRANCH LOGIC
// add for conditional jumps

assign gt_flag_true =
(((compare_true_r2 && !invalidate_instr) == 1'b1) &&
gt_flag_ex_reg) || gt_flag;
assign lt_flag_true =
(((compare_true_r2 && !invalidate_instr) == 1'b1) &&
lt_flag_ex_reg) || lt_flag;
assign eq_flag_true =
(((compare_true_r2 && !invalidate_instr) == 1'b1) &&
eq_flag_ex_reg) || eq_flag;

assign carry_flag_true =
(((save_carry_flag_reg && !invalidate_instr) == 1'b1)
S.K.P.ENGINEERING COLLEGE Page 54
 && carry_flag_ex) || carry_flag ;
assign branch_taken = unconditional_jump_reg || (gt_flag_true && jump_gt_reg) ||

(lt_flag_true && jump_lt_reg) || (eq_flag_true && jump_eq_reg) || (carry_flag_true

&& jump_carry_reg) ;

//****************************************
// EXECUTION STAGE PIPELINE REGISTERS

//****************************************

// Note that asynchronous read of memory ensures that no bypass

// is needed for STORE followed by LOAD

always @(posedge clk)

begin
if (save_carry_flag == 1'b1)

carry_flag_ex <= #1 carry_out;

operation_result <= #1 data_out;

data_wr_addr <= #1 store_true_reg ? st_mem_addr_reg : ld_mem_addr_reg;

data_rd_addr <= #1 ld_mem_addr_reg;
data_out_reg <= #1 data_out;
load_mem_data <= #1 load_true_reg;
invalidate_fetch_instr_r2 <= #1 invalidate_fetch_instr_r1;

invalidate_decode_instr_r1 <= #1 invalidate_decode_instr;

gt_flag_ex_reg <= #1 gt_flag_ex;

lt_flag_ex_reg <= #1 lt_flag_ex;

eq_flag_ex_reg <= #1 eq_flag_ex;
compare_true_r2 <= #1 compare_true_reg;
nxt_prog_ctr_r2 <= #1 nxt_prog_ctr_reg;
end
// data_wr_addr[10:8] is also the result wr addr
// and datamem wr data is also the wr data for register writes

S.K.P.ENGINEERING COLLEGE Page 55

//Disable register and memory writes during reset
always @(posedge clk)

if (reset == 1'b1)
begin
store_to_mem_ex <= #1 1'b0;
reg_wr_en_ex <= #1 1'b0;
destination_reg_addr <= 3'b0;
branch_taken_reg <= 1'b0;

invalidate_execute_instr <= 1'b0;

save_carry_flag_reg <= 1'b0;
end
else

begin
store_to_mem_ex <= #1 store_true_reg;
reg_wr_en_ex <= #1 write_to_regfile_reg;
destination_reg_addr <= #1 res_addr_reg;

branch_taken_reg <= #1 branch_taken;

save_carry_flag_reg <= #1 save_carry_flag;

if (branch_taken_reg == 1'b1)
invalidate_execute_instr <= #1 1'b1;
else
invalidate_execute_instr <= #1 1'b0;
end

//****************************************
// STORE RESULTS STAGE LOGIC
//****************************************

S.K.P.ENGINEERING COLLEGE Page 56

//During LOAD instruction data is fetched from memory and
// written to the register here

assign datamem_wr_data = load_mem_data ? datamem_rd_data : data_out_reg;

assign invalidate_instr = (invalidate_fetch_instr_r2 ||
invalidate_decode_instr_r1 || invalidate_execute_instr);
assign store_to_mem = (store_to_mem_ex && !invalidate_instr);

assign reg_wr_en = (reg_wr_en_ex && !invalidate_instr);

//****************************************
// STORE RESULT STAGE PIPELINE REGISTERS

//****************************************
always @(posedge clk)
begin
if (reset == 1'b1)
begin

carry_flag <= 1'b0;

gt_flag <= 1'b0;
lt_flag <= 1'b0;
eq_flag <= 1'b0;
end
else
begin
if ((save_carry_flag_reg && !invalidate_instr) == 1'b1)
carry_flag <= #1 carry_flag_ex;

if ((compare_true_r2 && !invalidate_instr) == 1'b1)

begin

S.K.P.ENGINEERING COLLEGE Page 57

 gt_flag <= #1 gt_flag_ex_reg;
lt_flag <= #1 lt_flag_ex_reg;

eq_flag <= #1 eq_flag_ex_reg;

end
end
end

//****************************************
// PROGRAM COUNTER
//****************************************
always @(posedge clk)

if (reset == 1'b1)
prog_ctr <= #1 10'b1;
else
begin
if (branch_taken_reg == 1) //update in store res stage
begin

prog_ctr <= #1 nxt_prog_ctr_r2;

set_invalidate_instruction <= #1 1'b1;
end
else
begin
prog_ctr <= #1 prog_ctr + 1'b1;
set_invalidate_instruction <= #1 1'b0;

end
end

endmodule

module register_file (clk, reset, wr_data, rd_data1, rd_data2, rd_addr1, rd_addr2, wr_addr, wr_en);
input clk, reset;
S.K.P.ENGINEERING COLLEGE Page 58
 input [7:0] wr_data;
input [2:0] rd_addr1, rd_addr2, wr_addr;
input wr_en;

output[7:0] rd_data1, rd_data2;

reg [7:0] rd_data1, rd_data2;

// register file
reg [7:0] reg_file [7:0];

always @(rd_addr1 or rd_addr2 or reset or wr_en or wr_data)

begin

rd_data1 <= reg_file[rd_addr1];

rd_data2 <= reg_file[rd_addr2];
end
always @(posedge clk)
begin
if (wr_en == 1)
reg_file[wr_addr] <= #1 wr_data;
end

endmodule

S.K.P.ENGINEERING COLLEGE Page 59

OUTPUT:

S.K.P.ENGINEERING COLLEGE Page 60

RESULT:
Thus the implemention of 8-Bit RISC processor using Verilog/ VHDL has been
verified successfully

S.K.P.ENGINEERING COLLEGE Page 61

EXP.
NO 8 To Simulate the NAND and NOR circuit using PSPICE circuit
simulator
DATE

AIM
To simulate the NAND and NOR circuit using PSPICE circuit simulator and to verify the
waveform
SOFTWARE REQUIRED
PSPICE students‘ version 9.1
PROCEDURE
1. Draw the schematic diagram in pspice schematic editor
2. Go choose the icon ―set up -> analysis‖, for choosing proper analysis options.
3. Now select the option ―transient‖.
4. Choose appropriate print step (eg:10 ns) and final time.
5. Now choose the icon ―set up -> Examine netlist‖, and if the netlist has no errors, choose
the ―simulate‖ option which is under ―set up‖.
6. The waveform window will pop up after the simulation.
PROGRAM:
NAND
* Schematics Netlist *

V_V4 N00052 0 5Vdc

M_M1 V0 V1 N00052 N00052 M2N6804
M_M2 V0 V2 N00052 N00052 M2N6804
M_M3 V0 V1 N00065 N00065 M2N6659
M_M4 N00065 V2 0 0 M2N6659
V_V1 V1 0
+PULSE 0v 5v 25ms 1ms 1ms 25ms 50ms
V_V2 V2 0
+PULSE 0v 5v 25ms 1ms 1ms 25ms 50ms

NOR
* Schematics Netlist *

V_V1 N00017 0 0Vdc

M_M1 N00020 V1 N00017 N00017 M2N6804
M_M2 V0UT V2 N00020 N00020 M2N6804
M_M3 V0UT V2 0 0 M2N6659
M_M4 V0UT V1 0 0 M2N6659

S.K.P.ENGINEERING COLLEGE Page 62

V_V2 V1 0
+PULSE 0v 5v 25ms 1ns 1ns 25ms 50ms
V_V3 V2 0
+PULSE 0v 5v 25ms 1ns 1ns 35ms 50ms

S.K.P.ENGINEERING COLLEGE Page 63

CIRCUIT DIAGRAM FOR NAND

CIRCUIT DIAGRAM FOR NOR

S.K.P.ENGINEERING COLLEGE Page 64

MODEL GRAPH

RESULT:

Thus the NAND circuit is simulated and the required waveforms are obtained.

S.K.P.ENGINEERING COLLEGE Page 65