Jnanaprabha Campus, Bidarahalli, Virgonagar Post, Bengaluru- 560049

ACCREDITED BY NATIONAL BOARD OF ACCREDITATION (ECE, CSE & ISE)

Department of Electronics and Communication Engineering

LABORATORY MANUAL
2023-2024

Semester VII

Subject : VLSI Laboratory

Subject code : 18ECL77

Name of the Student :

University Seat Number :
Batch :
 Department of Electronics and Communication Engineering

DEPARTMENT VISION AND MISSION

VISION
The Department aspires to be a centre of excellence in Electronics and Communication
Engineering to develop competitive and ethical professionals through holistic development.
MISSION
M1: To impart quality education and provide a conducive environment for innovation and
Research
M2: To develop skills to meet the scientific, technological and socio-economic needs
M3: To inculcate professional ethics, team work, leadership qualities and lifelong learning

PROGRAM EDUCATIONAL OBJECTIVES (PEO’s):

PEO-1: To produce graduates to have successful professional career with the acquired
knowledge in Electronics and Communication Engineering to analyse, design, develop and
implement electronic systems
PEO-2: To produce graduates who apply their engineering skills and develop ingenious
solutions for real world problems
PEO-3: To produce graduates who can exhibit leadership qualities, ethical values and adapt
to current trends by engaging in lifelong learning.
PROGRAM SPECIFIC OUTCOMES (PSO’s):

PSO1: To conceptualise, model, design, simulate, analyse, develop, test electronic and
communication systems and solve technical problems arising in the field of Electronics and
Communication Engineering.

PSO2: To specialize in the areas of Electronics and Communication Engineering such as

Analog and Digital electronics, communication, Signal processing, VLSI systems, Embedded
Systems and IOT.

PSO3: To demonstrate building and testing of electronics and communication systems

and evaluate their performance and efficiency using appropriate tools and techniques.
 VLSI Design and Testing LAB
Subject Code: BECL606 Total Hours: 40
Hours/Week : 3 Hrs Exam Hours: 03

Subject Code BECL606

I A Marks 50
Exam Marks 50

Course objectives:
This laboratory course enables students to:
• Design, model, simulate and verify digital circuits.
• Perform ASIC design flow and understand the process of synthesis, synthesis constraints and
evaluating the synthesis reports to obtain optimum gate level netlist.
• Perform RTL-GDSII flow and understand the ASIC Design flow.

Course Outcomes
At the end of this course, students should be able to:
CO1 Design and simulate combinational and sequential digital circuits using
Verilog HDL

CO2 Understand the synthesis process of digital circuits using EDA tool.

CO3 Perform ASIC design flow and understand the process of synthesis,
synthesis constraints and evaluating the synthesis reports to obtain optimum
gate level netlist.
CO4 Design and simulate basic CMOS circuits like inverter, NOR gate and any
Boolean expression .
CO5 Perform RTL_GDSII flow and understand the stages in ASIC design
 VLSI Design and Testing LAB
Effective from Academic year
SEMESTER-VI
Subject Code BECL606 CIE Marks 50

Number of Lecture Hours/Week 2 (Laboratory SEE Marks 50

Total Number of Lab Hours Exam Hours 3 Hours

Credits – 1
Course Learning Objectives :

This laboratory course enables students to:

• Design, model, simulate and verify digital circuits.
• Perform ASIC design flow and understand the process of synthesis, synthesis constraints
and evaluating the synthesis reports to obtain optimum gate level netlist.
• Perform RTL-GDSII flow and understand the ASIC Design flow.

Syllabus:

Experiments
Use any VLSI design tools to carry out the experiments, use library files and
technology files below 180 nm.

1 Design a 4-Bit Adder

• Write a Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and generate the gate
level netlist.
From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required
2 4-Bit Shift and add Multiplier
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the gate level
netlist.
From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required.

3 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case

and if
statement for ALU Behavioral Modeling
• Write Verilog description
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and
 timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path
4 Flip-Flops (D, SR and JK)
• Write the Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the gate level
netlist.
• Verify the functionality using Gate level netlist and compare the results at
RTL and
gate level netlist.
From the report gate level netlist identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required.

5 Four-bit Synchronous MOD-N counter with Asynchronous reset

• Write Verilog Code
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing
constraints
• Tabulate the Area, Power and Delay for the Synthesized Netlist
Identify Critical path
• Verify the functionality using Gate level netlist and compare the results at
RTL and gate level netlist.
6 a) Construct the schematic of CMOS inverter with load capacitance of 0.1pF
and set the widths of inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and
length at selected technology. Carry out the following:
i. Set the input signal to a pulse with rise time, fall time of 1ns and pulse
width of 10ns and the time period of 20ns and plot the input voltage and
output voltage of designed inverter.
ii. From the simulation result compute tpHL, tpLH and td for all three
geometrical settings of width.
iii. Tabulate the results of delay and find the best geometry for minimum
delay for CMOS inverter.
b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods.
Verify for DRC and LVS, extract parasitic and perform post layout
simulations, compare the results with pre layout simulations and compare the
results.
7. Capture the schematic of 2-input CMOS NOR gate having similar delay as
that of CMOS inverter computed in experiment above. Verify the functionality
of NOR gate and also find out the delay td for all four possible combinations
of input vectors. Table the results. Increase the drive strength to 2X and 4X
and tabulate the results.

8. Construct the schematic of the Boolean Expression Y= AB+CD+E using

CMOS Logic. Verify the functionality of the expression find out the delay td
for some combination of input vectors. Tabulate the results..
9. a) Construct the schematic of Common Source Amplifier with PMOS Current
Mirror Load and find its transient response and AC response. Measure the
Unit Gain Bandwidth (UGB), amplification factor by varying transistor
geometries, study the impact of variation in width to UGB.

b) Draw Layout of common source amplifier, use optimum layout methods.

Verify for DRC & LVS, extract parasitic and perform post layout simulations,
compare the results with prelayout simulations. Record the observations.

10 a) Construct the schematic of two-stage operational amplifier and measure

the following: i. Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and
phase margin with and without coupling capacitance iv. Use the op-amp in the
inverting and non-inverting configuration and verify its functionality. v. Study
the UGB, 3dB bandwidth, gain and power requirement in op-amp by varying
the stage wise transistor geometries and record the observations.

b) Draw layout of two-stage operational amplifier with minimum transistor width

set to 300 (in 180/90/45 nm technology), choose appropriate transistor
geometries as per the results obtained in part a. Use optimum layout methods.
Verify for DRC and LVS, extract parasitic and perform post layout
simulations, compare the results with pre-layout simulations and perform the
comparative analysis.
Demonstration Experiments (For CIE)
11 UART
• Write Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing
constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist, Identify
Critical path

12 De Design and characterize 6T binary SRAM cell and measure the following:
• Read Time, Write Time, SNM, Power
• Draw Layout of 6T SRAM, use optimum layout methods.
Verify for DRC & LVS, extract parasitic and perform post layout simulations,
compare the results with pre-layout simulations. Record the observations
Course Outcomes:
On the completion of this laboratory course, the students will be able to:
 Design and Simulate combinational and sequential digital circuits using
Verilog HDL.

 Understand the Synthesis process of digital circuits using EDA Tool

 Perform ASIC Design flow and understand the process of Synthesis, Synthesis
constraints and evaluating the synthesis reports to obtain optimum gate level
netlist.

 Design and simulate basic CMOS circuits like Inverter, Common Source Amplifier
and Differential Amplifiers.

 Perform RTL-GDSII flow and Understand the stages in ASIC Design

 Index

Sl Program List CO PO RBT Page

No No
PART A
1 a) Schematic of CMOS Inverter CO4 1,2,5 L1 4
b) Layout of CMOS Inverter CO5
2 a) Schematic of CMOS NAND Gate CO4 1,5 L1 22
b) Layout of CMOS NAND Gate CO5
3 a) Schematic of CMOS Common Source CO4 1,2,5 L2 27
Amplifier CO5
b) Layout of CMOS Common Source
Amplifier

4 a) Schematic of Two Stage Operational CO4 1,2,5 L2 33

Amplifier CO5
b) Layout of Two Stage Operational
Amplifier
PART B
1 Verilog code for 4-bit up/down counter CO1 1,2,5 L1 39
asynchronous reset counter CO2
CO3
2 Verilog code for 4-bit adder and verify its CO1 1,2,5 L1 42
functionality using test bench CO2
CO3
3 Verilog Code for UART and verify using Test CO1 1,2,3,5 L3 45
Bench CO2
CO3
4 Verilog code 32- bit ALU supporting four CO1 1,2 L2 53
logical and four arithmetic operations CO2
CO3
5 Verilog code for Latch and Flipflop, CO1 1,2,5,12 L1 57
Synthesize the design and compare the CO2
synthesis report (D, SR, JK)
6 Synthesized netlist carry out Floor planning CO1 1,2,12,5 L2 62
(automatic) identify the placements of pads CO2
Placement and Routing)
7 Additional Lab Experiment-1 CO4 1,2,5 L2 76
Design a single stage Differential Amplifier CO5
8 Additional Lab Experiment-2 CO1 1,2 L2 79
Simulate the Verilog code for the successive CO2
approximation register.

Viva Questions
VLSI LABORATORY Manual BECL606

Programs-Part A

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Lab 1: 4-bit Adder

Aim: To write a verilog code for 4bit adder and verify the functionality using Test bench.
• Synthesize, Analyse Reports and Netlist, Critical Path and Max Operating Frequency.
• From the report generated find the total number of cells, power requirement and total area
requirement.
Tool Required:
● Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
● Synthesis: Genus

Design Information and Bock Diagram:

A full adder is a combinational circuit that performs the arithmetic sum of three input bits Ai, addend
Bi and carry in Cin from the previous adder. Its results contain the sum Si and the carry out, Cout to the
next stage. So to design a 4-bit adder circuit we start by designing the 1 – bit full adder then
connecting the four 1-bit full adders to get the 4-bit adder as shown in the diagram below. For the 1-
bit full adder, the design begins by drawing the Truth Table for the three input and the corresponding
output SUM and CARRY.

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Creating Source Codes:

● In the Terminal, type gedit <filename>.v or <filename>.vhdl depending on the HDL
Language you are to use (ex: 4bitadder.v).
● A Blank Document opens up into which the following source code can be typed down.
Note : File name should be with HDL Extension

a) Verify the Functionality

⮚ Three Codes shall be written for implementation of 4-bit Adder as follows,
✔ fa.v → Single Bit 3-Input Full Adder [Sub-Module / Function]
✔ fa_4bit.v → Top Module for Adding 4-bit Inputs.
✔ fa_test.v → Test bench

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Functional Simulation:
→ Invoke the cadence environment by type the below commands
✔ csh (Invokes C-Shell)
✔ source /home/install/cshrc (mention the path of the tools)
✔ (The path of cshrc could vary depending on the installation destination as
/home/install/ or /home etc.)
⮚ After this you can see the window like below

The following figure shows how to invoke the cadence environment:

⮚ To Launch Simulation tool:

✔ linux:/> nclaunch -new& // “-new” option is used for invoking NCVERILOG
for the first time for any design
✔ linux:/> nclaunch& // On subsequent calls to NCVERILOG
⮚ It will invoke the nclaunch window for functional simulation we can compile,elaborate
and simulate it using Multiple

⮚Select Multiple Step and then select “Create cds.lib File” as shown in below figure

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⮚ Click the cds.lib file and save the file by clicking on Save option

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⮚ Save cds.lib file and select the correct option for cds.lib file format based on the HDL Language and libraries
used.
⮚ Select “Don’t include any libraries (verilog design)” from “New cds.lib file” and click on “OK” as in below
figure
✔ We are simulating verilog design without using any libraries.

⮚ A Click “OK” in the “nclaunch: Open Design Directory” window as shown in below
figure

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⮚ A ‘NCLaunch window’ appears as shown in figure below

⮚ Left side you can see the HDL files. Right side of the window has worklib and snapshots
directories listed.
⮚ Worklib is the directory where all the compiled codes are stored while Snapshot will have
output of elaboration which in turn goes for simulation

To perform the function simulation, the following three steps are involved Compilation, Elaboration and
Simulation.
Step 1: Compilation:– Process to check the correct Verilog language syntax and usage
Inputs: Supplied are Verilog design and test bench codes
Outputs: Compiled database created in mapped library if successful, generates report else error
reported in log file

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Steps for compilation:
1. Create work/library directory (most of the latest simulation tools creates automatically)
2. Map the work to library created (most of the latest simulation tools creates automatically)
3. Run the compile command with compile options
i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v

⮚ Left side select the file and in Tools : launch verilog compiler with current selection will
get enable. Click it to compile the code
⮚ Worklib is the directory where all the compiled codes are stored while Snapshot will have
the output of elaboration which in turn goes for simulation.
⮚

After compilation it will come under the worklib you can see in right side window.

⮚ Select the test bench and compile it. It will come under worklib. Under Worklib you can
see the module and test-bench.

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Step 2: Elaboration:– To check the port connections in hierarchical design

Inputs: Top level design / test bench Verilog codes
Outputs: Elaborate database updated in mapped library if successful, generates report else error
reported in log file
Steps for elaboration – Run the elaboration command with elaborate options
1. It builds the module hierarchy
2. Binds modules to module instances
3. Computes parameter values
4. Checks for hierarchical names conflicts
5. It also establishes net connectivity and prepares all of this for simulation.

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Step 3: Simulation: – Simulate with the given test vectors over a period of time to observe
the output behaviour.
Inputs: Compiled and Elaborated top level module name
Outputs: Simulation log file, waveforms for debugging
Simulation allow to dump design and test bench signals into a waveform
Steps for simulation – Run the simulation command with simulator option

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b) Synthesize the design using Constraints and analyse reports, critical path
and Max Operating Frequency.

Step 1: Getting Started

⮚ Make sure you close out all the Incisive tool windows first.
⮚ Synthesis requires three files as follows,
✔ Liberty Files (.lib)
✔ Verilog/VHDL Files (.v or .vhdl or .vhd)
✔ SDC (Synopsis Design Constraint) File (.sdc)

Step 2: Creating an SDC File

⮚ In your terminal type “gedit constraints_top.sdc” to create an SDC File if you do not
have one.
⮚ The SDC File must contain the following commands;

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Step 3 : Performing Synthesis

⮚ The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
⮚ The Available technology nodes are 180nm ,90nm and 45nm.
⮚ In the terminal, initialise the tools with the following commands if a new terminal is
being used.
✔ csh
✔ source /home/install/cshrc
⮚ The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
⮚ The Following are commands to proceed,
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl counter.v
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Effort level to medium for generic, mapping
and optimization
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10.syn_opt //Performing Synthesis Mapping and Optimisation
11.report_timing > counter_timing.rep
//Generates Timing report for worst datapath and dumps into file
12.report_area > counter_area.rep
//Generates Synthesis Area report and dumps into a file
13.report_power > counter_power.rep
//Generates Power Report [Pre-Layout]
14. write_hdl > counter_netlist.v //Creates readable Netlist File
15. write_sdc > counter_sdc.sdc //Creates Block Level SDC

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Lab 2: 4-Bit Shift and Add Multiplier

Aim: To write a verilog code for 4-Bit Shift and Add Multiplier and verify the functionality
using Test bench.
⮚ Synthesize, Analyse Reports and Netlist, Critical Path and Max Operating Frequency.
⮚ From the report generated, find the total number of cells, power requirement and total
area requirement.
Tool Required:
⮚ Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
⮚ Synthesis: Genus
Design Information and Flow Chart:
Binary multipliers are used for multiplication of 2 binary numbers and are used mainly in signal
processing and also in other computationally intensive applications. Shift and add binary multiplier
is a type of sequential multiplier. Sequential multipliers generate the partial products sequentially
and add each newly generated partial product to the previously accumulated sum. Shift and add
binary multiplier is a type of sequential multiplier.

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Shift and add multiplier is similar to multiplication done by paper and pencil. This method adds
the multiplicand X to itself Y times, where Y denotes the multiplier In the case of binary
multiplication, since the digits are 0 and 1, if the multiplier digit is 1, a copy of the multiplicand is

placed in the proper positions; if the multiplier digit is 0, a number of 0 digits are placed. The 2n-
bit product register (A) is initialized to 0. A 2n-bit multiplicand register with the multiplicand

placed in the right half of the register and with 0 in the left half is used. The algorithm starts by
loading the multiplicand into the B register, loading the multiplier into the Q register, and
initializing the A register to 0. The counter N is initialized to n. The least significant bit of the
multiplier register (Q0) determines whether the multiplicand is added to the product register. The
left shift of the multiplicand has the effect of shifting the intermediate products to the left and right
shift prepares the next bit of the multiplier to examine in the following iteration.

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b) Synthesis and Report/Output Analysis

Step 1: Getting Started
⮚ Make sure you close out all the Incisive tool windows first.
⮚ Synthesis requires three files as follows,
✔ Liberty Files (.lib)
✔ Verilog/VHDL Files (.v or .vhdl or .vhd)
✔ SDC (Synopsis Design Constraint) File (.sdc)

Step 2 : Creating an SDC File

Step 3 : Performing Synthesis

● The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
⮚ The Available technology nodes are 180nm ,90nm and 45nm.
⮚ In the terminal, initialise the tools with the following commands if a new terminal is
being used.
✔ csh
✔ source /home/install/cshrc
⮚ The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
⮚ The Following are commands to proceed,
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {shift_and_add_binary_multiplier.v} //Reading multiple Verilog Files
3. elaborate
4. set_top_module booth.v //Differentiating Top & Sub Module
5. set_dont_use *XL //Dont Use Cells with High Driving Strength
6. set_db syn_generic_effort medium //Setting effort medium
7. set_db syn_map_effort medium
8. set_db syn_opt_effort medium
9. syn_generic
10.syn_map
11.syn_opt
//Performing Synthesis Mapping and Optimisation
12.report_timing -unconstrained > adder_timing.rep
//Generates Timing report for worst datapath and dumps into file
//-unconstrained is to be given as no timing constraints are given
13.report_area > booth_area.rep
//Generates Synthesis Area report and dumps into a file
14.report_power > booth_power.rep
//Generates Power Report [Pre-Layout]
15. write_hdl > booth_netlist.v //Creates readable Netlist File
16. write_sdc > booth_sdc.sdc //Creates Block Level SDC
17.report_qor > booth_qor.rpt // Critical slack path
Commands 1-11 are intended for the synthesis process while 12-17 for Generating reports and
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Outputs.
Note 1:-
1. The Cells given in the netlist can be checked in the .lib files for their properties.
2. The Max Operating Frequency does not apply for Purely Combinational Circuit.

Synthesis script file

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Figure 2.6 SDC Constraints

Note 2:-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints
as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports
do not overwrite the earlier ones.

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Lab 3: 32-Bit ALU

Aim: Write a verilog code for 32 bit ALU supporting four logical and four arithmetic
operations, use case statement and if statement for ALU behavioral modeling.
⮚ To Verify the Functionality using Test Bench
⮚ Synthesize and compare the results using if and case statements
⮚ Identify Critical Path and constraints
Tool Required:
⮚ Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
⮚ Synthesis: Genus
Design Information and Bock Diagram:
The ALU will take in two 32-bit values, and control line. An Arithmetic unit does the
following task like addition subtraction, multi-fiction and logical operations. As the input is
given in 32 bit we get 32 bit output. The arithmetic will show only one output at a time so a
selector is necessary to select one of the operator.

Creating a Work space :

● Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

A) To Verify the Functionality using Test Bench

Source Code – Using Case Statement :

module alu_32bit_case(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
case(f)
3'b000:y=a&b; //AND Operation
3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b010:y=a+b; //Addition
3'b011:y=a-b; //Subtraction
3'b100:y=a*b; /Multiply
default:y=32'bx;
endcase
end
endmodule
Test Bench :
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module alu_32bit_tb_case;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end
initial
#50 $finish;
endmodule

Source Code

- Using If Statement :

module alu_32bit_if(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
if(f==3'b000)
y=a&b; //AND Operation
else if (f==3'b001)
y=a|b; //OR Operation
else if (f==3'b010)
y=a+b; //Addition
else if (f==3'b011)
y=a
-b; //Subtraction
else if (f==3'b100)
y=a*b; //Multiply
else
y=32'bx;
end
endmodule

Test bench :
module alu_32bit_tb_if;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_if test(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
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b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end
initial
#50 $finish;
endmodule

b) Synthesize Design
● Run the synthesis Process one time for each code and make sure the output File names
are changed accordingly.
Synthesis Process :
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {alu_32bit_if.v (OR) alu_32bit_case.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Optional-Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10.syn_opt
//Performing Synthesis Mapping and Optimisation
11.report_timing > alu_timing.rep
//Generates Timing report for worst datapath and dumps into file
12.report_area > alu_area.rep
//Generates Synthesis Area report and dumps into a file
13.report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. write_hdl > uart_netlist.v
//Creates readable Netlist File
15. write_sdc > uart_sdc.sdc
//Creates Block Level SDC

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Note :-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints
as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports
do not overwrite the earlier ones.

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Lab 4: Flip Flops

Aim: Write a verilog code for Flip-flops (D, SR, JK), Synthesize the design and compare the
synthesis report.
Tool Required:
● Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
● Synthesis: Genus
Design Information and Bock Diagram:

Latches and flip-flops are the basic elements for storing information. One latch or flip-
flop can store one bit of information. The main difference between latches and flip-flops is that

for latches, their outputs are constantly affected by their inputs as long as the enable signal is
asserted.
In other words, when they are enabled, their content changes immediately when their
inputs change. Flip-flops, on the other hand, have their content change only either at the rising or
falling edge of the enable signal. This enable signal is usually the controlling clock signal. After
the rising or falling edge of the clock, the flip-flop content remains constant even if the input
changes.
There are basically four main types of latches and flip-flops: SR, D, and JK. The major
differences in these flip-flop types are the number of inputs they have and how they change state.
For each type, there are also different variations that enhance their operations.

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Creating a Work space :

● Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.
A) Verilog Codes for D-Flip Flop, JK-Flip Flop and SR-Flip Flop.
Source code for D-Flip Flop:

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b) Synthesize the Design & Comparing Reports

Synthesis Commands :
1. read_libs /home/install_run/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl dff.v
3. elaborate
4. read_sdc constraints_top.sdc
5. set_db syn_generic_effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt
11. report_timing > dff_timing.rep
12. report_area > dff_area.rep

13. report_power > dff_power.rep

14. write_hdl > dff_netlist.v
15. write_sdc > dff_sdc.sdc

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Note :-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints
as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports
do not overwrite the earlier ones.

Lab 5: Four bit Synchronous MOD-N counter with

Asynchronous Reset

Aim: Write a verilog code for 4-bit Synchronous MOD-N counter with Asynchrounous reset,
verify the functionality using Test bench and Synthesize the design and compare the synthesis
report.
Tool Required:
● Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
● Synthesis: Genus
MOD-N Counter
Counters are sequential logic devices that follow a predetermined sequence of counting states
triggered by an external clock (CLK) signal. The number of states or counting sequences through
which a particular counter advances before returning to its original first state is called the modulus
(MOD). In other words, the modulus (or modulo) is the number of states the counter counts and is
the dividing number of the counter.
Modulus Counters, or MOD counters, are defined based on the number of states that the counter
will sequence before returning to its original value.
For example, a 2-bit counter that counts from 002 to 112 in binary, 0 to 3 in decimal, has a
modulus value of 4 ( 00 → 1 → 10 → 11, and return to 00 ); therefore, be called a modulo-4, or
mod-4, counter. Note also that it has taken four clock pulses to get from 00 to 11.
In this example, there are only two bits ( n = 2 ) then the maximum number of possible output
states (maximum modulus) for the counter is 2n = 22 or 4. However, counters can be designed to
count to any 2n states in their sequence by cascading together multiple counting stages to produce
a single modulus or MOD-N counter.
Therefore, a "Mod-N" counter will require the "N" number of flip-flops connected to count a single
data bit while providing 2n different output states (n is the number of bits). Note that N is always
a whole integer value. Then we can see that MOD counters have a modulus value that is an integral
power of 2, that is, 2, 4, 8, 16 and so on to produce an n-bit counter depending on the number of
flip-flops used, and how they are connected, determining the type and modulus of the counter.

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B) Synthesis and Report/Output Analysis
Step 1: Getting Started
Make sure you close out all the Incisive tool windows first.
Synthesis requires three files as follows,
● Liberty Files (.lib)
● Verilog/VHDL Files (.v or .vhdl or .vhd)
● SDC (Synopsis Design Constraint) File (.sdc)

Step 3 : Performing Synthesis

The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
● The Available technology nodes are 180nm ,90nm and 45nm.
● In the terminal, initialise the tools with the following commands if a new terminal is
being used.
● csh
● source /home/install/cshrc
● The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
● The Following are commands to proceed,
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {mod_n_counter.v} //Reading multiple Verilog Files
3. elaborate
4. set_top_module mod_n_counter.v //Differentiating Top & Sub Module
5. set_dont_use *XL //Dont Use Cells with High Driving Strength
6. set_db syn_generic_effort medium //Setting effort medium
7. set_db syn_map_effort medium
8. set_db syn_opt_effort medium
9. syn_generic

10. syn_map
11. syn_opt//Performing Synthesis Mapping and Optimisation
12. report_timing -unconstrained > mod_n_counter_timing.rep
//Generates Timing report for worst datapath and dumps into file
//-unconstrained is to be given as no timing constraints are given
13. report_area > mod_n_counter_area.rep
//Generates Synthesis Area report and dumps into a file
14. report_power > mod_n_counter_power.rep
//Generates Power Report [Pre-Layout]
15. write_hdl >mod_n_counter_netlist.v //Creates readable Netlist File
16. write_sdc > mod_n_counter_output.sdc //Creates Block Level SDC
17. report_qor > mod_n_counter_qor.rpt // Critical slack path
Commands 1-11 are intended for Synthesis process while 12-17 for Generating reports
and Outputs.

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Note 1:-
1. The Cells given in the netlist can be checked in the .lib files for their properties.
2. The Max Operating Frequency does not apply for Purely Combinational Circuit.

Synthesis RTL Schematic :

Figure No. 5.3: Common SDC Constraints

Note 2:-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints
as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports
do not overwrite the earlier ones.

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ANALOG EXPERIMENTS:
GENERAL NOTES

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Type the command “csh” to initialize shell and source the “cshrc” file with the
command “source /home/install/cshrc”. “cshrc” file will provide the details of the
installation directory of the Cadence Tools.

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INVOKING VIRTUOSO:
After sourcing the “cshrc” file, click on “Enter” on the keyboard. The welcome
screen with the text “Welcome to Cadence Tools Suite” can be seen as shown in
Figure - 5.

Invoke virtuoso using the command “virtuoso &” or “virtuoso” as shown in Figure
– 7 and click on “Enter” in the keyboard.

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LAB – 01: CMOS INVERTER

Objective:
(a) Capture the Schematic of a CMOS Inverter with Load Capacitance of 0.1 pF
and set the Widths of Inverter with
(i) WN = WP
(ii) WN = 2 WP
(iii) WN = WP / 2
and Length at selected Technology. Carry out the following:
1. Set the Input Signal to a pulse with Rise Time, Fall Time of 1 ps and Pulse
Width of 10 ns, Time Period of 20 ns and plot the input voltage and output
voltage of the designed Inverter
2. From the Simulation Results, compute tpHL, tpLH and tPD for all the three
geometrical settings of Width
3. Tabulate the results of delay and find the best geometry for minimum delay
for CMOS Inverter

Solution:
(a) Schematic Capture of CMOS Inverter
CREATE A LIBRARY:
To create a New Library, select “Tools 🡪 Library Manager” from the top menu as
shown in Figure – 1.1.

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A “New Library” window will show up as in Figure – 1.4. Name the Library (for eg:
VTU_LAB_MANUAL_180nm) and click on “OK”.

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Select “Technology File..” tab that keeps blinking at the bottom of the screen as
shown in Figure – 1.5 to map the New Library to a technology node based on the
specification.

From the list of available Technology Libraries, select the respective Technology
Node as shown in Figure – 1.7 (for example: gpdk180) and click on “OK”.

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The New Library can be verified from the Library Manager under “Library” column
as shown in Figure – 1.8.

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A “New File” window can be seen as shown in Figure – 1.11.

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Name the Cell and click on “OK”. A blank “Virtuoso Schematic Editor L Editing”
window can be seen as shown in Figure – 1.12.

(i) SCHEMATIC CAPTURE FOR THE CMOS INVERTER

To complete the Schematic for a CMOS Inverter with WN = WP, components have to
be included to the blank Virtuoso Schematic Editor window. These components are
called Instances. The procedure to include the components to the Schematic are given
below.
ADD AN INSTANCE:
Select “Create 🡪 Instance” as in Figure – 1.13 (or) use the bind key ‘I’ (or) the icon
as in Figure – 1.13.

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The “Add Instance” form can be seen as shown in Figure – 1.14.

Figure – 1.14: “Add Instance” Window

Click on the drop down close to the Browse option as shown in Figure – 1.14. Select
the Technology Node from the list of libraries. Similarly, click on the drop down next
to Cell and select the required device from the list. For the CMOS Inverter circuit,
PMOS and NMOS transistors are required. The parameters for the devices as given
in the requirement are considered as in Table – 1, Table – 2 and Table – 3.

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Make a left mouse click to place it on the Schematic Editor. The device after
placement on the Schematic Editor can be seen as shown in Figure – 1.16. Similarly,
other components can be instantiated.

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Name the pins by separating them with “space”, choose its direction and click on
“Hide” as shown in Figure – 1.19(a) and Figure – 1.19(b).

Figure – 1.19(a): Naming the Input Pins Figure – 1.19(b): Naming the Output
Pins

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Place the pins on the Schematic Editor using a left mouse click and the pins after
placement can be visualized as shown in Figure – 1.21.

Use the bind key “R” to rotate the pins and it can be done either before or after Pin
Placement. The direction of the pins before and after rotation are shown in Figure –
1.22.

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Use the left mouse click to start / complete the wire from one terminal / pin to another.
The complete Schematic after connecting the pins and terminals for all the three
conditions WN = WP, WN = 2 * WP, WN = WP / 2 is shown in Figure – 1.25(a), 1.25(b)
and 1.25(c) respectively.

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CHECK AND SAVE THE DESIGN:

It is mandatory to save the design before we move ahead to the Simulation and there
are two options, “Save” and “Check and Save” as in Figure – 1.26.

“Save” option saves the design as it is and “Check and Save” option checks for
discontinuities like floating net or terminal and provides the “error” or “warning”
messages accordingly and then saves the design. Sample message can be seen in the
“Command Interpreter Window” as shown in Figure – 1.27.

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SYMBOL MODIFICATION:
The symbol can be modified using the drawing tools from the top menu as shown in
Figure – 1.32.
To modify the symbol, remove the inner rectangle (green), highlighted in Figure –
1.33(a). To remove the inner rectangle (green), place the mouse pointer within and
make a left mouse click to select the entire rectangle as shown in Figure – 1.33(b).
Click on ‘Delete’ in the keyboard to remove the rectangle as shown in Figure –
1.33(c).

Figure – 1.33(a): Inner Rectangle Highlighted, Figure – 1.33(b): Inner Rectangle

Selected, Figure – 1.33(c): Inner Rectangle Deleted

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Since the focus is to design an Inverter, to create a triangle, use the “Create Line”
option as shown in Figure – 1.32. Use the same procedure as “wiring the schematic”
to create the triangle.

To create a bubble, use “Create Circle” option as shown in Figure – 1.32, place the
mouse pointer
at the center between the ‘Triangle’ and the ‘Output Pin’, make a left mouse click and
expand the circle and make a left mouse click to fix its size as shown in Figure – 1.35.
Click on “Check and Save” option to ‘Save’ the symbol.

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(1) TEST CIRCUIT FOR SIMULATION:

The Test Circuit can be created using the symbol created in the previous section. To
create a test circuit, create a “New Cellview” with a different “Cell Name” as shown
in Figure – 1.36.

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The remaining devices to be included on the Schematic and its properties are given
below in Table - 4.

The screenshot of the device properties for the instances vdc, vpulse, cap and gnd are
shown in Figure – 1.38, Figure – 1.39, Figure – 1.40 and Figure – 1.41. The complete
Test Schematic after wiring is shown in Figure – 1.42.

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The complete circuit after instantiating all the devices and interconnections is shown
in Figure – 1.42.

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To Label the nets, click on “L” in the keyboard. The “Create Wire Name” window
pops up as shown in Figure – 1.43. Name the nets, different net names can be
mentioned at the same instance of time by separating them with “Spaces”, same net
names can also be repeated as per the requirement and click on “Hide” as shown in
Figure – 1.44.

The “Wire Name before placement” can be seen in Figure – 1.45. The “Dot” just
under the wire name has to be placed over the “wire” and make a left mouse click to
fix it. The “Placed Wire Name” can be seen in Figure – 1.45.

The complete schematic after placing all the wire names is shown in Figure – 1.46.
“Check and Save” the Test Schematic.

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FUNCTIONAL SIMULATION WITH SPECTRE:

To simulate the design and perform the DC Analysis and Transient Analysis for the
CMOS Inverter, click on “Launch 🡪 ADE L” from the top menu of the Test
Schematic Cellview as shown in Figure – 1.47.

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Before running the simulation, check for the Simulator and Model Libraries.
SELECTING THE SIMULATOR:
To select the Simulator, click on “Setup 🡪 Simulator/Directory/Host” as shown in
Figure – 1.49.

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Figure – 1.49: Setup 🡪 Simulator/Directory/Host..

SELECTING THE MODEL LIBRARIES AND PROCESS CORNERS:

The Model Libraries and Process Corners are important to run the simulation.
To select the “.scs” file with respect to the technology node, select “Setup 🡪 Model
Libraries” as shown in Figure – 1.51.

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Select the respective “.scs” file and make a double click under “Section” to select the
processing corner of interest using a Left Mouse Click on the drop down and click on
“OK” as shown in Figure – 1.53.

SELECTING THE ANALYSIS:

To select the analysis required to be performed on the Test Circuit, select “Analyses
🡪 Choose” from the top menu in the ADE L window as shown in Figure – 1.54.

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The “Choose Analyses – ADE L” window pops up as shown in Figure – 1.55.

TRANSIENT ANALYSIS:
To set up a “Transient Analysis”, select “tran”, mention the “Stop Time” (for
example: 100n), select “Accuracy Defaults” (for example: moderate), click on
“Apply” and click on “OK” as shown in Figure – 1.56.

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The selected analysis and the arguments can be seen under the “Analyses” tab in the
ADE L window as shown in Figure – 1.57.

DC ANALYSIS:
To set up a “DC Analysis”, select “dc” and enable “Save DC Operating Point” as
shown in Figure – 1.58.

Enable “Component Parameter”, click on “Select Component” as shown in Figure

– 1.59.

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Select “DC Voltage” from the list of parameters as shown in the “Select Component
Parameter” window and click on “OK” as shown in Figure – 1.61.

From the “Sweep Range” option, select “Start-Stop” and mention the “Start” value
as “0” and “Stop” value as “1.8”, click on “Apply” and click on “OK” as shown in
the Figure – 1.62.

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The “Outputs” column in the “ADE L” window will be updated as shown in Figure
– 1.68.

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SAVING THE ADE L STATE:

To save the current ADE L state, click on “Session 🡪 Save State” as shown in Figure
– 1.72.

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The “Saving State – ADE L” window pops up. Select the “Save State Option 🡪
Cellview” and click on “OK” as shown in Figure – 1.73.

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The “Loading State – ADE L” window pops up. Select the “Load State Option 🡪
Cellview” and click on “OK” as shown in Figure – 1.76.

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Place the cursor in “Signal 1”, select the signal “IN” from the waveform window as
shown in Figure – 1.82.

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The value of “Switching Potential” should be mentioned under “Threshold Value
1” and “Threshold Value 2”.
Note:
What is Switching Potential?
Switching Potential is defined as the value of Input Voltage for which the
Output Voltage is equal to the Input Voltage.
How to obtain the value of Switching Potential?
To obtain the Switching Potential, use the “intersect” option from the
Function Panel, select the “Signal 1” and “Signal 2” from the DC Analysis
waveform window, click on “Apply”, click on “OK” and click on “Evaluate
the buffer and display the results in a table” icon as shown in Figure – 1.83
to obtain the value.
Select “Edge Number 1” and “Edge Number 2” as “2” (for example). Select “Edge
Type 1 🡪 falling” and “Edge Type 2 🡪 rising” to obtain the value of “tpLH” and
“Edge Type 1 🡪 rising” and “Edge Type 2 🡪 falling” to obtain the value of “tpHL”.
After the above mentioned selections, click on “Apply” and click on “OK” to see the
“Buffer” window in the calculator getting updated as shown in Figure – 1.84.

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• Higher Fills have Higher Widths. As shown Below, The End Caps are added below your
Power Mesh.

To add Well Taps, Select Place → Physical Cell → Add Well Tap → Select →FillX [X →
Strength of Fill = 1,2,4 etc] → Distance Interval [Could be given in range of 30-45u] → OK

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Placement
1. The Placement stage deals with Placing of Standard Cells as well as Pins.
2. Select Place → Place Standard Cell → Run Full Placement → Mode → Enable ‗Place I/O
Pins‘ → OK → OK .
All the Standard Cells and Pins are placed as per the communication between them, i.e., Two
communicating Cells are placed as close as possible so that shorter Net lengths can be used
for connections as Shorter Net Lengths enable Better Timing Results.

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You can toggle the Layer Visibility from the list on the Right. The List of Layers available
are shown on the right under ―Layer‖ tab with colour coding.
Report Generation and Optimization :
1. Timing Report :
1. To generate Timing Report, Timing → Report Timing → Design Stage – PreCTS

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2. Analysis Type – Setup → OK

3. The Timing report Summary can be seen on the Terminal.
2. Area Report :
1. cmd : report_area
3. Power Report :

1. cmd : report_power

In case of any Violating paths, the design could be optimized in the following way.
To optimize the Design, Select ECO → Optimize Design → Design Stage [PreCTS] →
Optimization Type – Setup → OK
After you run the optimization, the terminal displays the latest Timing report and updated area
and power reports can be checked.
• This step Optimizes your design in terms of Timing, Area and Power. You can Generate
Timing, Area, Power in similar way as above report Post – Optimization to compare the
Reports.
Clock Tree Synthesis
• The CTS Stage is meant to build a Clock Distribution Network such that every Register
(Flip Flop) acquires Clock at the same time (Atleast Approximately) to keep them in
proper communication.
• A Script can be used to Build the Clock Tree as follows :

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Report Generation and Design Optimization :

• CTS Stage adds real clock into the Design and hence ―Hold‖ Analysis also becomes
prominent. Hence, Optimizations can be done for both Setup & Hold, Timing Reports are
to be Generated for Setup and Hold Individually.
Setup Timing Analysis :

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Additional Experiments -1
DIFFERENTIAL AMPLIFIER
Objective: To design a single stage Differential Amplifier with given specifications and
verifying the following
1. Schematic:
i) DC Analysis ii) AC Analysis iii) Transient Analysis
2. Layout:
i) DRC ii) LVS iii) RCX
Design:

Specification:

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Figure 11: Diff Amp Schematic

Diff Amp_test Schematic:
Specifications:
Library name Cell name Properties
analoglib Vsin AC Magnitude=1, Amplitude=5m,
Frequency=1k
analoglib Vsin For Vdd: DC voltage =2.5,
For Vss: DC voltage ==-2.5
analoglib Vsin
analoglib Vsin DC Current =30u

Analysis Values
Transient Stop time = 5ms
DC Start time = -5, stop time = 5.
AC Start time= 100,stop time=
100M,points per decade = 20

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Figure 12: Diff Amp_Test Schematic

Result

Diff Amp Layout:

Figure 13: Diff Amp Layout

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Additional Experiment 2
Aim: To compile and to simulate the Verilog code for the successive approximation register.
Design Files:
I Main Design Module: sar.v
module sar (digitalout,done,comp,start,reset,clk);
output [3:0] digitalout;
output done;
input clk, start, reset, comp;
reg [3:0]ring_count;
reg [3:0]digital;
wire D4,set0,set1,set2,set3;
assign D4 = ring_count[0];
assign done = !D4;
always @(posedge clk or negedge reset)
begin
if (~reset)
ring_count <= 4'b1000;
else
begin
if (start)
ring_count <= 4'b1000;
else
ring_count <= (ring_count>>1);
end
end
assign set3 = ring_count[3];
assign set2 = ring_count[2];
assign set1 = ring_count[1];
assign set0 = ring_count[0];
always @(posedge clk or negedge reset)

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begin
if(~reset)
digital[3] <= 1'b1;
else
if(start)
digital[3] <= 1'b1;
else if(set3)
digital[3] <= comp;
end
always @(posedge clk or negedge reset)
begin
if(~reset)
digital[2] <=
1'b1; else
if(start)
digital[2] <= 1'b1;
else if(set2)
digital[2] <= comp;
end
always @(posedge clk or negedge reset)
begin
if(~reset)
digital[1] <=
1'b1; else
if(start)
digital[1] <= 1'b1;
else if(set1)
digital[1] <= comp;
end
always @(posedge clk or negedge reset)

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begin
if(~reset)
digital[0] <= 1'b1;
else
if(start)
digital[0] <= 1'b1;
else if(set0)
digital[0] <= comp;
end
assign digitalout = (digital) | (ring_count);
endmodule
II Sub Design Module: dac.v
module dac (comp,sar_out,vref_d,vin_d,clk,start);
output comp;
input clk,start;
input [3:0]sar_out;
input [63:0]vref_d;
input [63:0]vin_d;
reg comp;
real v_dac,vref,vin;
always @ (vin_d or start)
begin
vref = $bitstoreal(vref_d);
vin = $bitstoreal(vin_d);
end
always @*
begin
if(start)
comp = 1'b0;
else

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begin
v_dac = (vref/15)*(sar_out);
if (vin<v_dac)
comp = 1'b0;
else
comp = 1'b1;
end
end
endmodule
III Test Bench Module: sar_tb.v
module sar_tb;
reg clk,reset,start;
reg [63:0] vref_d,vin_d;
wire done, comp;
wire [3:0] digitalout;
real vref_real = 7.5;
sar s1 (digitalout,done,comp,start,reset,clk);
dac d1
(comp,digitalout,vref_d,vin_d,clk,start); initial
begin
clk = 1'b1;
start = 1'b1;
#4000 $finish;
end
always #10 clk = ~clk;
initial
begin
#1;reset = 1'b1;
#10; reset = 1'b0;
#1; reset = 1'b1;

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end
initial
begin
#10 ;
stimulus (0.0,0.5,vref_real,8'd5);
end
task stimulus (input analog, input step, input reference, input [7:0]delay);
real analog,step;
real reference;
begin
while(analog <= reference)
begin
repeat(delay)
@(posedge clk);
start <= 1'b0;
vref_d = $realtobits (reference);
vin_d = $realtobits (analog);
@(posedge done)
analog = analog + step;
@(posedge clk);
start <= 1'b1;
end
end
endtask
endmodule

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VIVA Questions:
1. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
2. What are set up time & hold time constraints? What do they signify?
3. Explain Clock Skew?
4. Why is NAND gate preferred over NOR gate for fabrication?
5. What is Body Effect?
6. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
7. What is the fundamental difference between a MOSFET and BJT?
8. Why PMOS and NMOS are sized equally in a Transmission Gates?

9. What happens when the PMOS and NMOS are interchanged with one another in an
inverter?

10. Why are pMOS transistor networks generally used to produce high signals, while nMOS
networks are used to product low signals?

11. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you
avoid Latch Up?

12. Difference between Synchronous and Asynchronous reset.

13. What is DRC?
14. What is LVS?
15. What is RCX?
16. What are the differences between SIMULATION and SYNTHESIS?
17. What is a counter?
18. What are the differences between flip-flop and latch?
19. How can you convert JK flip-flop into Jk?
20. What are different types of adders?
21. Give the excitation table for JK flip-flop?
22. Give the excitation table for SR flip-flop?
23. Give the excitation table for D flip-flop?
24. Give the excitation table for T flip-flop?
25. What is the race around condition?
26. What is an amplifier?
27. What is an op-amp?
28. What is differential amplifier?
29. What is elaboration?
30. What is transient analysis?
31. What is DC analysis?
32. What is AC analysis?

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