RISC-V Assembly - II

Computer Architectures

Department of Information Engineering and Computer Science

Prof. Kasim Sinan Yildirim
Representing Instructions
● Instructions are encoded in binary
○ machine language: the numeric version of assembly instructions
○ machine code: a sequence of machine language instructions.

add x9, x20, x21

0000000 10101 10100 000 01001 0110011

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Hexadecimal
● Base 16
○ Compact representation of bit strings, 4 bits per hex digit

0 0000 4 0100 8 1000 c 1100

1 0001 5 0101 9 1001 d 1101
2 0010 6 0110 a 1010 e 1110
3 0011 7 0111 b 1011 f 1111

● Example: eca8 6420

○ 1110 1100 1010 1000 0110 0100 0010 0000

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RISC-V to Machine Language
● The segments of an instruction is called a field.

add x9, x20, x21

7 bit 5 bit 5 bit 3 bit 5 bit 7 bit
0000000 10101 10100 000 01001 0110011
(0) (21) (20) (0) (9) (51)

● This layout of the instruction is called the instruction format.

● Simplicity favors regularity: RISC-V instructions are all 32 bits long

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RISC-V R-format Instructions
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

● R-type (register) Instruction fields

○ opcode: operation code
■ denotes the operation and format of an instruction
○ rd: destination register number
○ funct3: 3-bit function code (additional opcode)
○ rs1: the first source register number
○ rs2: the second source register number
○ funct7: 7-bit function code (additional opcode)

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R-format Example
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

add x9, x20, x21

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R-format Example
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

add x9, x20, x21

0 21 20 0 9 51

0000000 10101 10100 000 01001 0110011

0000 0001 0101 1010 0000 0100 1011 0011 two = 015A04B316

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RISC-V I-format Instructions
immediate rs1 funct3 rd opcode
12 bits 5 bits 3 bits 5 bits 7 bits

● Immediate arithmetic and load instructions

○ rs1: source or base address register number
○ immediate: constant operand, or offset added to base address
■ interpreted as a two’s complement value,
● it can represent integers from −211 to 211−1

● Design Principle 3: Good design demands good compromises

○ Different formats complicate decoding, but allow 32-bit instructions uniformly
○ Keep formats as similar as possible

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RISC-V I-format Instructions
immediate rs1 funct3 rd opcode
12 bits 5 bits 3 bits 5 bits 7 bits

ld x9, 64(x22) // Temporary reg x9 gets A[8]

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RISC-V I-format Instructions
000010000000 10110 001 01001 0000011
12 bits 5 bits 3 bits 5 bits 7 bits

ld x9, 64(x22) // Temporary reg x9 gets A[8]

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RISC-V S-format Instructions
Imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

● Different immediate format for store instructions

○ rs1: base address register number
○ rs2: source operand register number
○ immediate: offset added to base address
■ Split so that rs1 and rs2 fields always in the same place

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Instruction Encoding Example
● C code:
A[30] = h + A[30] + 1

● Compiler output for the RISC-V:

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Instruction Encoding Example
● C code:
A[30] = h + A[30] + 1

● Compiler output for the RISC-V:

ld x9, 240(x10) // Temporary reg x9 gets A[30]

add x9, x21, x9 // Temporary reg x9 gets h+A[30]
addi x9, x9, 1 // Temporary reg x9 gets h+A[30]+1
sd x9, 240(x10) // Stores h+A[30]+1 back into A[30]
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Instruction Encoding Example
ld x9, 240(x10) // Temporary reg x9 gets A[30]
add x9, x21, x9 // Temporary reg x9 gets h+A[30]
addi x9, x9, 1 // Temporary reg x9 gets h+A[30]+1
sd x9, 240(x10) // Stores h+A[30]+1 back into A[30]

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Instruction Encoding Example
ld x9, 240(x10) // Temporary reg x9 gets A[30]
add x9, x21, x9 // Temporary reg x9 gets h+A[30]
addi x9, x9, 1 // Temporary reg x9 gets h+A[30]+1
sd x9, 240(x10) // Stores h+A[30]+1 back into A[30]
000011110000 01010 011 01001 0000011
12 bits 5 bits 3 bits 5 bits 7 bits

0000000 01001 10101 000 01001 0110011

7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

000000000001 01001 000 01001 0010011

12 bits 5 bits 3 bits 5 bits 7 bits

0000111 01001 01010 011 10000 0100011

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7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
Arithmetic and Data Transfer Inst.
(Summary)

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Stored Program Computers
● Instructions represented in binary, just like data The BIG Picture
● Instructions and data stored in memory
● Programs can operate on programs
○ e.g., compilers, linkers, …

● Binary compatibility allows compiled

programs to work on different computers
○ Standardized ISAs

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Logical Operations
● Instructions for bitwise manipulation
● Useful for extracting and inserting groups of bits in a word

Operation C Java RISC-V

Shift left << << slli
Shift right >> >>> srli
Bit-by-bit AND & & and, andi
Bit-by-bit OR | | or, ori
Bit-by-bit XOR ^ ^ xor, xori
Bit-by-bit NOT ~ ~
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Shift Operations
● They move all the bits in a doubleword to the left or right
○ filling the emptied bits with 0s.

● Shift left by 4 (multipy by 2 4):

Before: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001001

After:

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Shift Operations
● They move all the bits in a doubleword to the left or right
○ filling the emptied bits with 0s.

● Shift left by 4 (multipy by 2 4):

Before: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001001

After: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10010000

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Shift Operations
● They move all the bits in a doubleword to the left or right
○ filling the emptied bits with 0s.

● Shift right by 2 (divide by 22):

Before: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001001

After:

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Shift Operations
● They move all the bits in a doubleword to the left or right
○ filling the emptied bits with 0s.

● Shift right by 2 (divide by 22):

Before: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001001

After: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000010

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Shift Operations
● Shift left logical (slli) and Shift right logical (srli)

funct6 immed rs1 funct3 rd opcode

6 bits 6 bits 5 bits 3 bits 5 bits 7 bits

● Use I-type Format

○ immed: how many positions to shift
○ Shift left logical: Shift left and fill with 0 bits
■ slli by i bits multiplies by 2i
○ Shift right logical: Shift right and fill with 0 bits
■ srli by i bits divides by 2i (unsigned only)

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Shift Operations
● slli example

slli x11, x19, 4 // reg x11 = reg x19 << 4 bits

● srli example

srli x11, x19, 2 // reg x11 = reg x19 >> 2 bits

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AND Operations
● Useful to mask bits in a word
○ Select some bits, clear others to 0

and x9,x10,x11
x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000

x11 00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000

x9 00000000 00000000 00000000 00000000 00000000 00000000 00001100 00000000

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OR Operations
● Useful to include bits in a word
○ Set some bits to 1, leave others unchanged

or x9,x10,x11

x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000

x11 00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000

x9 00000000 00000000 00000000 00000000 00000000 00000000 00111101 11000000

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XOR Operations
● Differencing operation
○ Set some bits to 1, leave others unchanged

xor x9,x10,x12 // NOT operation

x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000

x12 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111

x9 11111111 11111111 11111111 11111111 11111111 11111111 11110010 00111111

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NOT Operation
● NOT takes one operand
○ places a 1 in the result if one operand bit is a 0, and vice versa.

● The designers of RISC-V decided to include the instruction XOR (exclusive

OR) instead of NOT.
○ NOT is an XOR with 111…111.

xor x9, x9, x10 // reg x9 = reg x9 ^ reg x10

x9 00000000 00000000 00000000 00000000 00000000 01100011 01100011 11001101

x10 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111

x9 11111111 11111111 11111111 11111111 11111111 10011100 10011100 00110010 28

Example
● Set the most significant 4 bits of a word in x9 to 1:

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Example
● Set the most significant 4 bits of a word in x9 to 1:

addi x10, x0, 0x000F

slli x10, x10, 60
or x9, x9, x10

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Example
● Rotate left (circular shift) the register x9 by four bits
○ four most significant bits of x9 will move to its least significant bits

11010000 00000000 00000000 00000000 11010000 00000000 00000000 00000000

Result: 00000000 00000000 00000000 00001101 00000000 00000000 00000000 00001101

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Example
● Rotate left (circular shift) the register x9 by four bits
○ four most significant bits of x9 will move to its least significant bits

11010000 00000000 00000000 00000000 11010000 00000000 00000000 00000000

Result: 00000000 00000000 00000000 00001101 00000000 00000000 00000000 00001101

srli x10, x9, 60

slli x9, x9, 4
or x9, x9, x10

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Logical Instructions - Summary
● RISC-V also provides the instructions and immediate (andi), or
immediate (ori), and exclusive or immediate (xori).

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The end
● Read Sections 2.5 and 2.6 of your book.

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