Efficient Booth Multiplier Design with Wallace Tree and Hybrid

Adder Architecture
Himanshu Bendale, Pratik Biradar, Gaurav Avghade

Abstract— This project provides an 8x8-bit Booth Multiplier Andrew D. Booth's Booth Multiplication Algorithm,
that is optimized for binary multiplication in digital circuits. It developed in 1951, laid the groundwork for a more efficient
optimizes the multiplication process by minimizing partial product multiplication process by reducing the number of partial
formation using the Booth encoding approach. The project products generated. Booth's method makes use of the power
includes the development of 8-bit adders, multiplexers, and a of two's complement encoding to speed up the multiplication
Wallace Tree-based topology. The Xilinx ISE design suiteis used operation. The algorithm has a high speed and area
for synthesis, which ensures both functionality and resource efficiency, making it an appealing choice for hardware
efficiency. The study examines resource utilization and timing, design.
proving successful implementation at speeds of less than
20 nanoseconds. This Booth Multiplier improves processing Booth Multipliers have been thoroughly investigated and
capability in digital systems and sets the groundwork for future optimized from a variety of perspectives over the years.
arithmetic circuit optimization research. Researchers have looked into a variety of implementations,
Keywords— Carry select adder, Modified Booth Encoder, ranging from simple 4x4-bit multipliers to more complex
Wallace, High speed Adders, Square Root Carry Select Adder, 32x32-bit designs. The primary goal of these studies has been
Look Up Table to find a happy medium between hardware resources and
performance.
I. INTRODUCTION FPGA devices and their synthesis tools have played a
Multiplication is a fundamental operation in digital critical role in the advancement of Booth Multipliers in recent
circuits that underpins a wide range of computational years. Technologies such as Xilinx ISE provide a platform for
activities. The efficiency and speed of binary multiplication rapid prototyping and testing, making it possibleto investigate
are crucial in everything from microprocessors to digital the behaviour of Booth Multipliers under various
signal processing. An existing multiplication technique, the configurations and design constraints.
Booth Multiplier, provides an intuitive solution to optimise Moreover, numerous studies have been conducted to
this procedure. This project focuses on the complete design optimize the delay and area utilization of Booth Multipliers.
and implementation of an 8x8-bit Booth Multiplier, a critical To improve overall performance, advanced techniques such
component that powers modern digital systems. as pipelining, partial product reduction, and sophisticated
The Booth algorithm, a binary multiplication stalwart, adder architectures have been incorporated into Booth
lowers the number of partial products formed during the Multiplier designs. These enhancements are especially
process. It accomplishes this by carefully encodiffng and important in applications requiring high-speed
recoding binary numbers, reducing device complexity and multiplication, such as digital signal processors and graphics
significantly increasing processing speed. processing units.

Our project includes the development of 8-bit adders, Among the works is the elimination of the final sign bit,
multiplexers, and a novel Wallace Tree structure. We use the which lowers power consumption and streamlines the design.
synthesis capabilities of the Xilinx ISE design suite to assure They present new methods for altered Booth encoding,
strong functionality and resource efficiency. We compressors, and a last adder, which produce a low-power
painstakingly scrutinize resource utilization and timing multiplier[1] that can run at 1.6 GHz. This work offers faster
throughout this trip, ensuring that the Booth Multiplier and more power-efficient multiplication for a variety of
performs at an astonishing sub-20 nanosecond speed. applications, which makes significant contributions to digital
circuit design..
This study makes an important contribution to the field of
digital systems. Our 8x8-bit Booth Multiplier shines in One paper introduces a new method of high-speed
instances where binary multiplication is a time-critical multiplication by concentrating on the first stage of partial
activity. It serves as a foundation for a variety of arithmetic product generation[2]. This strategy seeks to produce fewer
and data processing circuits, offering up new possibilities in partial product rows initially, resulting in faster multiplication
digital circuit design. times, in contrast to traditional methods that seek to reduce
the partial product rows in later stages. The main innovation
is a technique that reduces the requirement for extra partial
II. LITERATURE SURVEY product rows by quickly determining a binary number's two's
The field of digital arithmetic has undergone continuous complement. This method produces a more organized and
evolution in response to the increasing demand for efficient effective structure for the implementation of VLSI. The
computation in a wide range of applications, ranging from synthesized results demonstrate notable gains in efficiency
signal processing and data encryption to scientific and speed over traditional techniques for multiplications of 8
computing. The key operation of multiplication is at the heart and 16 bits.
of this evolution, and it has been the subject of intensive study
Parminder Singh Jassal and Lakhvinder Kaur's research
aimed at improving both performance and area utilisation.
paper examines an 8x8-bit Modified Booth's Multiplier[3].
The Booth Multiplier is one approach that has stood the test
The Modified Booth multiplication algorithm, which
of time.
minimizes partial products and improves compression speed,
is examined in this paper. The multiplier is modelled by the This research paper's literature review addresses the
authors using VHDL. In digital signal processing systems, importance of high-speed multipliers in [8] cryptographic
multipliers are essential components, and the goal of this applications like RSA and ECC. It draws attention to the
work is to maximize their effectiveness. The study uses Wallace tree multiplier's structure, which is renowned for
simulation and design verification, and the findings operating at a high speed. The review discusses earlier
demonstrate how effective the multiplier is in terms of attempts to improve and optimise the performance of Wallace
hardware resources and power consumption, which makes it multipliers through the use of modified architectures, layout
a significant addition to the field of digital circuit design. strategies, and Booth encoding. Theauthors suggest a cutting-
edge method to shorten the partial product tree reduction
In their work, Rozman Zakaria and F. Mohd Zaki delay by making use of high-speed counters. The review
investigate novel approaches to digital filter design highlights that their algorithmic methodoffers a general way
optimization, concentrating on [4] Finite Impulse Response to build effective Wallace multipliers that are counter-based.
(FIR) filters. FIR filters are frequently utilized in signal Lastly, it states that when compared to conventional Wallace
processing applications, but because of the multiple multipliers, the suggested counter- based Wallace multiplier
multiplications involved in their implementation, they exhibits a notable speedimprovement.
frequently use excessive power. In order to increase
efficiency, lower power consumption, and conserve space in Several techniques have been proposed in the field of
a 16-Tap FIR filter, the paper presents Radix-4 Booth digital adder design to enhance reconfigurability and
multipliers and improved Booth multipliers respectively. performance. Conventional reconfigurable adders have been
Applications where effective filtering is essential, such as implemented with large delay penalties due to the use of extra
image processing and wireless communication networks, can bits for partitioning. Several techniques have been proposed
benefit from this work. It provides workable answers to the to minimise area cost and delay, including optimised carry-
problems of computational speed and power efficiency in skip schemes and Brent-Kung carry lookahead adders. A
digital filters. novel partition scheme [9] for reconfigurable hybrid carry-
lookahead/carry-select adders (CLSA) is presented in this
An extensive analysis of multiplier optimisation for Field paper. Promising for high-speed,low-area, low-power digital
Programmable Gate Arrays (FPGAs) is presented in this systems, the proposed method efficiently splits large CLSAs
paper[5]. The Redundant Binary Signed Digit (RBSD) into smaller, reconfigurable components with minimal
number system is presented by the authors as a way to additional area cost and no delay penalty.
improve carry propagation delay and computational speed.
Using Vivado 2019.2, they implement the RBSD multiplier The paper [10] investigates integrated circuit adder
in VHDL and compare it to conventional binary multipliers. designs that are efficient. The significance of area and speed
The research highlights the balance between area and timing, optimization in VLSI circuit design is covered. In order to
which makes it an important tool for FPGA designers looking minimize area consumption, the paper reviews several adder
to reduce resource consumption and increase multiplication types, including the Carry Select Adder (CSA), Carry Look-
performance. Ahead Adder (CLA), and Ripple Carry Adder (RCA). It also
introduces the Modified Carry Select Adder (MCSA). Fast
In digital electronics, multiplication optimisation is the adders such as Carry Skip Adder (CSA) and Carry Look-
main topic of this [6] paper. In many applications, Ahead Adder (CLA) are integrated to improve performance.
multiplication is essential and calls for efficiency and speed. In order to show that the Modified Square Root Carry Select
A modified Radix-2 Booth multiplier for signed and unsigned Adder provides optimal performance in terms of delay,
numbers is introduced in the study to address this. Building memory utilization, and logic levels, the authors analyze it
on earlier studies, this work highlights the need for with different fast adders.[design speed eff sqrt csa]
multiplication techniques that are quicker and more effective.
The authors' goal of lowering area and power consumption is Considerable progress in VLSI adder architectures has
consistent with current developments in energy efficiency been made in the last few years. There are restrictions on the
and integrated chip design. Their work supports the need for area and power efficiency of conventional Carry Select
high-speed multiplication while advancing digital circuit Adders (CSLA). Scholars have been experimenting [11] with
design. a number of improvements and alterations, like adding Zero
Finding Logic (ZFC) to Square Root Carry Select Adders
Low-power 8x8 bit multipliers are examined in the paper (SQRT CSLA). Reducing area consumption while keeping
[7] within the framework of cutting-edge semiconductor performance standards is the aim. Studies comparing
technology. It talks about the importance of low-power modified and conventional architectures for various bit sizes
design for high-performance systems and emphasizes the use show that the modified SQRT CSLA with ZFC is a promising
of multipliers in applications related to digital signal method for enhancing VLSI system designs because it
processing. The study compares and contrasts different provides notable benefits in terms of lower area and power
CMOS multipliers with an emphasis on their power consumption.
consumption, delay, and power delay product (PDP).
According to simulation results, bridge-style adders III. METHODOLOGY
combined with array and Wallace tree multipliers provide
better performance in terms of reduced power consumption Modified Booth Multiplier :
and quicker operation. The study emphasizes how crucial This multiplier has been implemented by leveraging
effective multiplier design is to improving system radix-2 encoding. The Modified Booth method dramatically
performance and reducing power usage.[performance reduces the number of partial products by half, or N/2, in
analysis]
comparison to normal multiplication. The multiplier is very Wallace Tree:
efficient for binary operands because of the decrease in The Wallace tree reduction technique is implemented by
partial products, which also results in a decrease in hardware the included Verilog module, Wallacetree8x8, to maximise
needs and an increase in operating speed. Unlike radix-4 the multiplication of two 8-bit values, producing the sum
encoding, Booth Classic places more emphasis on radix-2 (opa) and carry (opb) outputs. A key method for effective
operations. This method yields a multiplier with various multiplication is the Wallace tree reduction. It operates by
benefits for the design, including less hardware area and dividing the multiplication procedure into several steps, each
minimal delays. of which computes a collection of partial products before
Reducing the number of calculation stages and boosting combining them to produce the desired outcome. First and
parallelism is one method for obtaining high-speed second-order partial sums and carries are produced in this
multiplication. The Modified Booth method excels in this module by combining the input partial products, pp0 to pp7,
situation, providing the advantages of fewer partial products in the first step. The ultimate outputs, opa and opb, are
and simplified hardware implementation. The method produced by further processing these intermediate outcomes
optimises the multiplication operation, particularly for larger in later steps.
operands, by transforming the original multiplier using a set In particular, for large operand sizes, the Wallace tree
of redundant digit values. This multiplier is renowned for its reduction is crucial to lowering computational complexity
effectiveness in reducing delays and utilising hardware, and expediting the multiplication operation. It accomplishes
which makes it a great option for a variety of applications this by splitting up the processing into multiple phases, which
where multiplication is a crucial process, especially. For makes it incredibly efficient and parallel. The module ensures
multiplication, the Modified Booth Algorithm performs the precise multiplication results while optimising hardware
following steps: utilisation. This Verilog implementation demonstrates the
• Booth Encoding & Partial Product Generation usefulness of Wallace tree reduction, afundamental technique
in digital design.
• Wallace Tree
• Square Root Carry Select Adder

Booth Encoding & Partial Product Generation:

The binary multiplication has been implemented using a
traditional Booth encoding and partial product creation. By
representing a multiplier as a series of 0s, 1s, and 2s, a
technique known as booth encoding makes multiplication
easier. This block generates partial products (pp0 to pp7) by
using the multiplicand (M) to construct the multiplier (R)
encoded using Booth encoding. The multiplier uses a ternary
operator (?:) to compare pairs of encoded bits (YN andYN+1)
and decide which one to utilise to generate each partial
product: the multiplicand, its 2's complement, or 0. A set of
partial products and their sign extension bits are the end
result, allowing for effective binary multiplication.
Truth Table for Booth Encoder :
Figure 3.1 : Illustration of Wallace Tree Reduction Method
YN YN-1 Operation X 2 Neg
X
Square Root Carry Select Adder
0 0 +0 x X 0 0 0 A 16-bit Carry Select Adder (CSA), intended to
effectively add two 16-bit binary numbers, is represented in
0 0 +0 x X 1 0 0 this work. Offering a balance between speed and area, the
0 1 +1 x X 0 X 0
CSA architecture is a hybrid adder that combines the benefits
of carry lookahead and ripple carry adders.
0 1 +1 x X 1 X 0
The adder is split up into four 4-bit groups in this design,
1 0 -1 x X 0 ~X 0 and each group has its own propagation and carry generation
units. These individual groups use both carry-lookahead
1 0 -1 x X 1 ~X 0 (CLA) and carry-select (CS) techniques to effectively
1 1 +0 x X 0 0 0 minimise the carry chain delay. Because of its square
structure, this is also known as the Square Root Carry Select
1 1 +0 x X 1 0 0 Adder (SQRTCSA).
Table 3.1 : Truth table for Booth Encoder
Because the SQRTCSA offers less delay than a traditional
ripple carry adder, using it in this implementation is a
significant decision. The delay of this adder is given by:
Delay = T_p + N * T_g + T_L + T_pga
 Where,
Delay is a representation of the SQRTCSA's overall
delay.
The propagation delay, or T_p, measures how long it
takes for signals to move through combinational logic inside
of a single group.
N is the SQRTCSA's total number of groups.
The generation delay, or T_g, represents the amount of
time needed to generate carries.
The time required for signal transmission between
groups, including inter-group routing delays, is denoted by Fig 3.2: 16-bit Hybrid Square root Carry Select Adder
T_L.
The propagation delay inside the group carry-lookahead Algorithm for Booth Classic Multiplier
adder is denoted by T_pga. Input:
The SQRTCSA is the best option for applications where M (8-bit Multiplicand)
speed is critical because it drastically lowers the critical path
delay by splitting the addition into smaller groups. By using R (8-bit Multiplier)
this architecture, the adder's performance and efficiency are Output:
increased while the hardware complexity is kept reasonable.
pp0, pp1, pp2, pp3, pp4, pp5, pp6, pp7 (8-bit Partial
Comparison of delay, logic and memory of different Products)
adders :
S (8-bit Sign Extend Bit of Each Partial Product)
Adders Delay
(nano Memory Logic levels Steps:
seconds) (kilobytes)
1. Concatenate 1 zero bit to the right of the
Ripple Carry 33.378ns 177908 18 Multiplier R to create a 9-bit value tmp.
Adder (15.2
2. Calculate pp0 based on tmp[1:0]:
81ns logic,
3. If tmp[1:0] is '01', set pp0 to M.
18.097ns route)
Carry look- 31.744ns 178228 18 4. If tmp[1:0] is '10', set pp0 to 2's complement of
M+
Ahead Adder (15.2
81ns 5. Otherwise, set pp0 to 8'b0.
logic 6. Set S[0] to the 7th bit of pp0.
,16.463ns route)
7. Calculate pp1 to pp7 similarly for their
Carry Select 27.844ns 178164 15 respective slices of tmp and set their sign bits in
Adder (13.6 S[1] to S[7].
28ns 8. Output the partial products pp0 to pp7 and their
logic corresponding sign extend bits in S[0] to S[7].
,14.216ns route)
Sqrt Carry 26.540ns 179508 14
Algorithm for Wallace Tree 8x8 Adder:
Select Adder (13.147ns,
logic,13.393ns
Input:
route) pp0 to pp7 (8-bit Partial Products)
Table 3.2 : Comparison of delay, logic and memory of different adders
Output:
opa (16-bit Operand A)
opb (16-bit Operand B)
Steps:
1. Perform addition and carry-out calculation for 4-
bit groups in parallel (pp0 to pp3 and pp4 to pp7)
using half-adders and full-adders.
2. Repeat the addition and carry-out calculation in
parallel for both groups to create two sets of 4-
bit sums and carry-outs.
 3. Combine the results of both groups to form two Parameter [9] % Th OutOf
4-bit sum and carry-out sets. is
4. Perform another round of addition and carry-out wo
rk
calculation in parallel for both groups.
Number ofsliced
5. Combine the group results to generate 4-bit sums flip 3 0% 0 163
and carry-outs. flops 2
6. Combine the final results to create Operand A
(opa) and Operand B (opb) by concatenating the Number of
bondedIOB 50 54 3 102
sums and zero bits accordingly.
% 2
Algorithm for 16-bit Carry-Select Adder (CS_Adder16)
Table 3.3 : Comparison of Device Utilization Summary
Input:
a (16-bit operand A)
b (16-bit operand B)
cin (carry-in)
Output:
sum (16-bit sum)
Table 4.4 Delay Comparison
cout (carry-out)
Steps:
1. Split operands a and b into four 4-bit groups. IV. ANALYSIS

2. Calculate the generate (g) and propagate (p)

signals for each group.
3. Compute the 4-bit carry-out (cX_s0) for both
groups using g and p.
4. Calculate the 4-bit carry-out (cX_s1)
considering the carry-in cin for both groups.
5. Determine the final 4-bit carry-out (cX) for each
group based on the carry-in.
6. Compute the 4-bit sum for each group.
7. Combine the 4-bit results of all groups to form
the 16-bit sum.
8. Calculate the final carry-out (cout) as the carry-
Figure 4.1 Simulation of our Multiplier
out of the most significant group.
RTL View of the proposed Booth Multiplier:

Figure 4.2 Device Utilization Summary

This figure shows the device utilization summary of the proposed

Fig 3.3 RTL View of the proposed Booth Multiplier Booth Multiplier out of 2400 Sliced LUT’s we have used 6% if it i.e 163 and
the number of IOB’s 32 has been used out of 102 which is 31%.

Novelty
The Adder we have used combines the logic of both carry-
look ahead and carry select techniques in sqrt csa that adds
the last stages partial products.Our work has utilization of less
FF’s and IOB than the previous proposed work.
Also our proposed method has increased the speed of the
multiplier as shown in table 4.4

Figure 4.3 HDL Synthesis Report

 [7] S. Rani et al., "Performance Analysis of Different 8x8 Bit CMOS
Multiplier using 65nm Technology,"
This design makes use of multiplexers, Xors, adders/subtractors, and other
[8] S. Raveendran et al., "Inexact Signed Wallace Tree Multiplier Design
macro components, as shown in the HDL Synthesis Report. With 91 uses, the
Using Reversible Logic,"
1-bit xor2 macro element is the most frequently used one.
[9] J.-F. Li, J.-D. Yu, and Y.-J. Huang, "A Design Methodology for Hybrid
Carry-Lookahead/Carry-Select Adders with
Reconfigurability,"
[10] K. M. Priyadarshini et al., "Design Of Area And Speed Efficient Square
Root Carry Select Adder Using Fast Adders,"
[11] B. S. Kandula et al., "Area Efficient VLSI Architecture for Square Root
Carry Select Adder using Zero Finding Logic,"
[12] Artisan Components, "TSMC 0:13m Process CL013LV 1.2-Volt
SAGE-X Standard Cell Library Databook," Artisan Components, Oct.
2001.
[13] A.D. Booth, "A Signed Binary Multiplication Technique," Quarterly
J. Mechanical and Applied Math., vol. 4, pp. 236-240, 1951.
Figure 4.4 Timing Summary [14] D.P. Agrawal and T.R.N. Rao, "On Multiple Operand Addition of
Signed Binary Numbers," IEEE Trans. Computers, vol. 27, pp. 1068-
A clock's timing summary is displayed in the image. According to the timing 1070, Nov. 1978.
summary, the clock's speed grade is -3 nanoseconds. Any combinational [15] L. Dadda, "Some Schemes for Parallel Multiplier," Alta Frequenza,
logic path in the design must propagate a signal in less time than 18.665 vol. 34, pp. 349-356, 1965.
nanoseconds because the maximum combinational path delay is 18.665
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[17] M.D. Ercegovac and T. Lang, Digital Arithmetic. Los Altos, Calif.:
V. CONCLUSION Morgan Kaufmann, 2003.
[18] J. Fadavi-Ardekani, "M x N Booth Encoded Multiplier Generator
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utilisation in this project, as shown by a notable 54% drop in [19] A. Farooqui and V. Oklobdzija, "General Data-Path Organization of a
bonded IOBs and an overall more efficient design. MAC Unit for VLSI Implementation of DSP Processors," Proc. 1998
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