VLSI LAB MANUAL BECL606

CONTENTS
Syllabus .............................................................................................................................................................. v
CONTENTS ................................................................................................................................................... viii
Introduction to Cadence ...................................................................................................................................... 9
Using the UNIX Operating System ................................................................................................................... 10
General Procedure for Analog Design ............................................................................................................... 11
Design 1: INVERTER ...................................................................................................................................... 21
Design 2: NOR GATE ...................................................................................................................................... 27
Design 3 - Construct the schematic using Boolean Expression using CMOS-Logic .......................................... 32
(Y = AB+CD+E)’ ............................................................................................................................................. 32
Design 4 COMMON SOURCE AMPLIFIER WITH PMOS CURRENT MIRROR LOAD .............................. 36
Design 5 – TWO STAGE OPERATIONAL AMPLIFIER ................................................................................ 42
General Procedure for Digital Simulation ......................................................................................................... 48
General Procedure for Synthesis ....................................................................................................................... 48
Experiment – 6 4- bit Adder .......................................................................................................................... 51
Experiment – 7 4-Bit Booth Multiplier ....................................................................................................... 55
Experiment – 8 32-Bit ALU ........................................................................................................................... 60
Experiment – 9 Latch and Flip-Flop ........................................................................................................... 65
Experiment – 10 Four bit Synchronous MOD-N counter with Asynchronous reset ...................... 73
Procedure for Physical Design ......................................................................................................... 77

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Introduction to Cadence
Cadence Design Systems provides tools for different design styles. In this tutorial you will learn
to use three Cadence products: Composer Symbol, Composer Schematic and the Virtuoso Layout
Editor. This tutorial will help you to get started with Cadence and successfully create symbol,
schematic and layout views of an inverter. You will also learn how to simulate your design using
Hspice. The final check will be seeing if your layout matches your schematic. Figure 1.1 shows
the normal design sequence from design specifications to final layout simulation. This tutorial
will take you through all the steps (except the last). In addition, there are chapters on Verilog,
VHDL, bipolar current mode logic (CML), standard cells, and auto placement and routing.

Design Process Flow Diagram

The Cadence Development System consists of a bundle of software packages such as

schematic editors, simulators, and layout editors. This software manages the development
process for analog, digital, and mixed-mode circuits. In this course, we will strictly use the tools
associated with analog circuit design. All the Cadence design tools are managed by a software
package called the Design Framework II. This program supervises a common database which
holds all circuit information including schematics, layouts, and simulation data. From the Design
Framework II also known as the "framework", we can invoke a program called the Library
Manager which governs the storage of circuit data. We can access libraries and the components
of the libraries called cells. Also, from the framework we can invoke the schematic entry editor
called "Composer". Composer is used to draw circuit diagrams and draw circuit symbols. A
program called "Virtuoso" is used for creating integrated circuit layouts. The layout is used to

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create the masks which are used in the integrated circuit fabrication process. Finally, circuit
simulation is handled through an interface called "Analog Artist." This interface can be used to
invoke various simulators including HSPICE, Spectre, and Verilog. We will be using the
SpectreS simulator in this course.

Using the UNIX Operating System

Using the UNIX operating system is similar to using other operating systems such as
DOS. UNIX commands are issued to the system by typing them in a “shell” or “xterm”. UNIX
commands are case sensitive so be careful when issuing a command, usually they are given in
lower-case. The following list summarizes all the basic commands required to manage the data
files you will be creating in this lab course. All UNIX commands are entered from the shell or
xterm window. Do not use UNIX commands for modifying, deleting, or moving any Cadence
data files.
Common UNIX Commands

ls [–la] Lists files in the current directory. ”l” lists with properties and “a” also
lists hidden files (ones beginning with a “.”).
cd XXXX Changes the current directory to XXXX.
cd .. Changes the current directory back one level.
cp XXXX YYYY Copies the file XXXX to YYYY.
mv XXXX YYYY Move file XXXX to YYYY. Also used for rename
rm XXXX Deletes the file XXXX
mkdir XXXX Creates the directory XXXX.
lp -dXXXX YYYY Prints the textfile or postscript file YYYY to the printer named
XXXX, where XXXX can be either “ipszac” or “hpszac”.
gedit XXXX& Starts the gedit text editor program and loads file XXXX.
top Check available processes and memory usage.
quota –v Check for disk space available

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ASIC Analog Design

General Procedure for Analog Design

1. Initialize the cadence tools:
a. Login as ‘LAB’.
b. Open a terminal.
c. Navigate to the folder ‘cadence_db’
d. Navigate to the folder ‘Analog’
e. Run commands:
i. csh
ii. source cshrc

2. Change to the course directory by entering this command:

> cd ‘Analog’
[Note: You will start the Cadence Design Framework II environment from this directory
because it contains cds.lib, which is the local initialization file. The library search paths
are defined in this file.]

Lab directory details:

. /libs.cdb Contains a technology library for the design (gpdk180nm).

. /models Contains spectre models of components for simulation in gpdk180nm

technology.

. /stream Contains layer map file for GDSII format

. /pv Containing the Assura and Diva verification files

. /techfiles Contains ASCII versions of the oa22 techfiles

. /dig_source Contains verilog codes for SAR register and clock

. /cds.lib File containing pointer to the Cadence OA22 initialization file.

. /hdl.var File defines the work library for AMS simulation

. /docs Reference manual and user manual for gpdk180nm technology.

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3. In the same terminal window, enter:

> virtuoso &

The virtuoso or Command Interpreter Window (CIW) appears at the bottom of the screen.

Note: If the “What’s New ...” window appears, close it.

. Keep opened CIW window for the labs.

4. Create a new library
a. In the Library Manager, execute File - New – Library. The new library form appears.
b. In the “New Library” form, type your .library name in the Name section. In the field of
Directory section, verify that the path to the library is set to ~/cadence_analog_labs_613
and click OK.
Note: A technology file is not required if you are not interested to do the layouts for the design
c. In the next “Technology File for New library” form, select option Attach to an
existing techfile and click OK.

d. In the “Attach Design Library to Technology File” form, select gpdk180 from the
cyclic field and click OK.

e. After creating a new library you can verify it from the library manager.
f. If you right click on the “USN” and select properties, you will find that gpdk180 library
is attached as techlib to “USN”.

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5. Create a schematic cell view

a. In the CIW or Library manager, execute File – New – Cellview.
b. Set up the New file form as follows:

c. Do not edit the Library path file and the one above might be different from the path
shown in your form.
d. Click OK when done the above settings. A blank schematic window for the Inverter
design appears.
6. Add components for the design in concern from libraries available. Edit component parameters
to those specified. Complete the wiring and verify the design connection.
7. Click the Check and Save icon in the schematic editor window.

8. Observe the CIW output area for any errors. If any errors are found make suitable corrections.
9. Create Symbol for the schematic created and saved. In the created designs schematic window
execute Create — Cellview— From Cellview.
a. The Cellview From Cellview form appears. With the Edit Options function active, you
can control the appearance of the symbol to generate.
b. Verify that the From View Name field is set to schematic, and the
c. To View Name field is set to symbol, with the Tool/Data Type set as
SchematicSymbol.

d. Click OK in the Cellview From Cellview form.The Symbol Generation Form appears.
e. Modify the Pin Specifications as follows:

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f. Click OK in the Symbol Generation Options form.

g. A new window displays an automatically created Inverter symbol as shown here

h. Edit the symbol if required. Save the symbol. After creating symbol, click on the save
icon in the symbol editor window to save the symbol. In the symbol editor, execute File
— Close to close the symbol view window.
10. Create Test Bench. .
a. In the CIW or Library Manager, execute File— New— Cellview.
b. Set up the New File form as follows:

c. Click OK when done. A blank schematic window for the new design appears.
d. Using the component list and Properties for the simulation given, build the test bench
schematic.
11. Perform Simulation with Spectrre. Start the Simulation Environment to run a simulation.
a. In the schematic window, execute

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Launch – ADE L
The Virtuoso Analog Design Environment (ADE) simulation window appears.
b. Choose a Simulator.Set the environment to use the Spectre® tool, a high speed, highly
accurate analog simulator. Use this simulator with the Inverter_Test design, which is
made-up of analog components.
c. In the simulation window (ADE), execute
Setup— Simulator/Directory/Host.
d. In the Choosing Simulator form, set the Simulator field to spectre (Not spectreS) and
click OK.
e. The Model Library file contains the model files that describe the nmos and pmos devices
during simulation. Set the Model Libraries.
In the simulation window (ADE), execute
Setup - Model Libraries.
The Model Library Setup form appears. Click the browse button to add
gpdk.scs if not added by default as shown in the Model Library Setup form.
Remember to select the section type as stat in front of the gpdk.scs file.
Your Model Library Setup window should now looks like the below figure.

f. To complete the Model Library Setup, move the cursor and click OK.
The Model Library Setup allows you to include multiple model files.It also allows you to
use the Edit button to view the model file.
g. Choose the Analyses required for the simulation. In the Simulation window (ADE), click

the Choose - Analyses icon.

[You can also execute Analyses - Choose]
The Choosing Analysis form appears. This is a dynamic form, the bottom of the form
changes based on the selection above.
h. After setting each analysis Click Apply.Once all analysis have been set click OK in the
Choosing Analyses Form.
i. Set Design Variables. Set the values of any design variables in the circuit before
simulating. Otherwise, the simulation will not run.

i. In the Simulation window, click the Edit Variables icon. .

ii. The Editing Design Variables form appears.
iii. Click Copy From at the bottom of the form.
iv. The design is scanned and all variables found in the design are listed.
v. If any design variable exist they appear in the Table of Design variables section.

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vi. Set the value of the design variable

vii. Click Change and notice the update in the Table of Design Variables.
viii. Click OK or Cancel in the Editing Design Variables window.
j. Select outputs for plotting. Execute Outputs – To be plotted – Select on Schematic in
the simulation window.
k. Select the nets of the voltages to be plotted. If currrents are to be plotte d click on the
Pins where the currets where the currents flow.
l. The simulation window will look like this.

m. Run the Simulation. Execute Simulation – Netlist and Run in the simulation window to
start the simulation or the icon

This will create the netlist as well as run the simulation.

n. When simulation finishes, the Transient, DC plots automatically will be popped up
along with log file.

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12. Create Layout View of the design. From schematic window menu execute Launch – Layout
XL. A Startup Option form appears.
a. Select Create New option. This gives a New Cell View Form
b. Check the Cellname, Viewname (layout). Click OK from the New Cellview form. LSW
and a blank layout window appear along with schematic window.
c. Add components to layout. Execute Connectivity – Generate – All from Source or
click the icon

in the layout editor window, Generate Layout form appears. Click OK which imports
the schematic components in to the Layout window automatically.
d. Re arrange the components within PR-Boundary.
e. Select the design. Activate the connectivity view under
Connectivity-Nets-Show/Hide all incomplete nets
f. Make connections.to clear all incomplete nets.
g. Save the design.
13. Check the Layout using DRC. Execute
Assura-Run DRC

The DRC form appears. The Library and Cellname are taken from the current design window,
but rule file may be missing. Select the Technology as gpdk180. This automatically loads the
rule file.

Your DRC form should appear like this

Click OK to start DRC.

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14. A Progress form will appears. You can click on the watch log file to see the log file.
When DRC finishes, a dialog box appears asking you if you want to view your DRC results, and
then click Yes to view the results of this run.
15. If there any DRC error exists in the design View Layer Window (VLW) and Error Layer
Window (ELW) appears. Also the errors highlight in the design itself.
Click View – Summary in the ELW to find the details of errors.
16. If there are no errors in the layout then a dialog box appears with No DRC errors found written
in it, click on close to terminate the DRC run.
17. LVS will perform the check to compare the schematic netlist and the layout netlist. To Run LVS
select Assura – Run LVS from the layout window.
The Assura Run LVS form appears. It will automatically load both the schematic and layout
view of the cell.
18. Change the following in the form and click OK

19. The LVS begins and a Progress form appears. If the schematic and layout matches completely,
you will get the form displaying Schematic and Layout Match.
20. If the schematic and layout do not matches, a form informs that the LVS completed successfully
and asks if you want to see the results of this run.
Click Yes in the form. LVS debug form appears, and you are directed into LVS debug
environment.
21. In the LVS debug form you can find the details of mismatches and you need to correct all those
mismatches and Re – run the LVS till you will be able to match the schematic with layout.
22. Assura RCX will extract the RC values from the layout and perform analog circuit simulation on
the designs extracted with RCX.
Before using RCX to extract parasitic devices for simulation, the layout should match with
schematic completely to ensure that all parasites will be backannoted to the correct schematic
nets.
23. To Run RCX , from the layout window execute Assura – Run RCX.

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24. Change the following in the Assura parasitic extraction form. Select output type under Setup tab
of the form

25. In the Extraction tab of the form, choose Extraction type, Cap Coupling Mode and specify the
Reference node for extraction.

26. In the Filtering tab of the form, Enter Power Nets as vdd!, vss! and Enter Ground Nets as
gnd!

27. Click OK in the Assura parasitic extraction form when done. The RCX progress form appears, in
the progress form click Watch log file to see the output log file.
28. When RCX completes, a dialog box appears, informs you that Assura RCX run Completed
successfully.
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29. You can open the av_extracted view from the library manager and view the parasitic.

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Design 1: INVERTER
Objective : To implement an inverter schematic of CMOS inverter with load capacitance of
0.1pF and set the widths of inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at
selected technology. Carry out the following:

a. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and
time period of 20ns and plot the input voltage and output voltage of designed inverter?

b. From the simulation results compute tpHL, tpLH and td for all three geometrical settings
of width?

c. Tabulate the results of delay and find the best geometry for minimum delay for CMOS
inverter?

d) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC
and LVS, extract parasitic and perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.

Design

Device Cutoff Non saturation Saturation

Vgsp>Vtp Vgsp<Vtp Vgsp<Vtp
Vin < Vtp+Vdd Vin<Vtp+Vdd
P device
Vin > Vtp+Vdd Vdsp>Vgsp-Vtp Vdsp<Vgsp-Vtp
Vout> Vin-Vtp Vout<Vin-Vtp
Vgsn<Vtn Vgsn>Vtn Vgsn>Vtn
Vin> Vtn Vin>Vtn
N device
Vin<Vtn Vdsn<Vgs-Vtn Vdsn>Vgs-Vtn
Vout<Vin-Vtn Vout>Vin-Vtn

Region Condition P device n device

A 0≤Vin< Vtn Non saturation Cutoff

B Vtn≤ Vin<Vdd/2 Non saturation Saturation

C Vin=Vdd/2 Saturation Saturation

D Vdd/2<Vin≤Vdd - Vtp| Saturation Non saturation

E Vin>Vdd-|Vtp| Cutoff Non saturation

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Fig 1.1 Schematic

Table 1.1 Symbol Pin Configuration

Pin Names Direction

Vin vdd vss Input

vout Output

Table 1.2 Device parameters of pMOS and nMOS

Library Cell
Sl.No. Properties/Comments
name name
nMOS W=850n, L=180n
1 gpdk180
pMOS W=850n, L=180n
nMOS W=850n, L=180n
2 gpdk180
pMOS W=1.7u, L=180n
nMOS W=850n, L=180n
3 gpdk180
pMOS W=425n, L=180n

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Fig 1.3 Test Bench Schematic

Table 1.3 Test Bench Design Parameters

Cellview
Library name Properties/Comments
name
USN Inverter Symbol
Voltage 1=0, voltage 2=1.8,
Delay time =0, Rise time=Fall
analogLib Vpulse
time=1ns, Pulse width =10n,
Period =20n
analogLib vdc DC voltage, vdc=1.8
anlogLib cap C = 100f F

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Fig 1.4 Analog Simulation with Spectre

Fig 1.5 Expected Test bench Waveform

Analog Simulation with Spectre

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Table 1.5 Values of tpLH, tpHL and tPD for different geometries

Width Settings MOSFET Width tpLH tpHL tpd

pMOS 850n
Wp= Wn 3.233E-10 7.049E-10 5.141E-10
nMOS 850n
pMOS 850n
Wp=2Wp 3.337E-10 4.700E-10 4.019E-10
nMOS 1.7u
pMOS 425u
Wn = Wp/2 1.141E-09 3.154E-10 7.282E-10
nMOS 850u

Library Cell
Sl.No. Properties/Comments
name name
nMOS W=20u, L=180n
1 gpdk180
pMOS W=40u, L=180n

MOSFET Length Width tpLH tpHL tpd

pMOS 180n 40u
1.23E-10 3.55E-11 7.78E-11
nMOS 180n 20u

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Fig 1.6 Expected Layout View

Sample Questions
1. What happens to delay if we include a resistance at the output of a CMOS circuit?
Increases. (RC delay)
2. What are the limitations in increasing the power supply to reduce delay?
The delay can be reduced by increasing the power supply but if we do so the heating effect
comes because of excessive power, to compensate this we have to increase the die size
which is not practical.
3. How does Resistance of the metal lines vary with increasing thickness and increasing
length?
For CMOS logic, give the various techniques you know to minimize power consumption?
Power dissipation = CV2f, from this minimize the load capacitance, dc voltage and the
operating frequency.
4. What is Charge Sharing? Explain the Charge Sharing problem while sampling data
from a Bus?
In the serially connected NMOS logic the input capacitance of each gate shares the charge
with the load capacitance by which the logical levels drastically mismatched than that of the
desired once. To eliminate this load capacitance must be very high compared to the input
capacitance of the gates (approximately 10 times).

Outcome Student will be able to create the schematic, verify schematic functionality and
device regions of operation by simulation and build the layout for the same in Cadence
Virtuoso.

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Design 2: NOR GATE

Objective: To implement a NOR GATE schematic, verify its design with a suitable test bench
and generate the layout of the same.

Schematic of 2-input CMOS NOR gate having similar delay as that of CMOS inverter
computed in experiment

1. Verify the functionality of NOR gate and also find out the delay td for all four possible
combinations of input vectors. Table the results. Increases the drive strength to 2X and 4X
and tabulate the results.

2.b) Draw layout of NOR with Wp/Wn = 40/20, use optimum layout methods. Verify for
DRC and LVS, extract parasitic and perform post layout simulations, compare the results
with pre-layout simulations. Record the observations.

Design

Truth Table for NOR GATE

A B y
0 0 0
0 1 1
1 0 1
1 1 1

Width and Length of NMOS and PMOS Transistors for CMOS NOR

Library Name Cell Name Comments / Properties

gpdk180 nMOS W = 1.7u; L = 180n
gpdk180 pMOS W = 1.275u; L = 180n

Width and Length of NMOS and PMOS Transistors for CMOS NOR Gate with Drive Strength “2”

Library Name Cell Name Comments / Properties

gpdk180 nMOS W = 3.4u; L = 180n
gpdk180 pMOS W = 2.55u; L = 180n

Width and Length of NMOS and PMOS Transistors for CMOS NOR Gate with Drive Strength “4”

Library Name Cell Name Comments / Properties

gpdk180 nMOS W = 6.8u; L = 180n
gpdk180 pMOS W = 5.1u; L = 180n

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Fig 2.1 NOR Gate Schematic

Table 2.2 NOR test bench Design Parameters

Library name Cellview name Properties/Comments

USN NAND Symbol

V0:

analogLib vpulse v1=0, v2=1.8, td=0 tr=tf=1ns, ton=10n,

T=20n

V2:

v1=0, v2=1.8,td=0 tr=tf=1ns, ton=5n,

T=10n

analogLib vdd, vss, gnd Vdd=1.8

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Fig 2.3 Test bench circuit for NOR

[NOTE: Analog Simulation Specs for simulation with Spectre – same as inverter]

Fig Expected NOR Gate Testbench Waveform

Values of Delay for 2 – input CMOS NOR2X1, NOR2X2 and NOR2X4

NOR Type MOSFET Length Width tpLH tpHL tpd

NOR2X1 pMOS 180n 2.55u 5.580E-10 2.338E-10 3.959E-10

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nMOS 180n 0.85u

pMOS 180n 5.1u
NOR2X2 3.915E-10 1.540E-10 2.728E-10
nMOS 180n 1.7u
pMOS 180n 10.2u
NOR2X4 2.850E-10 1.155E-10 2.003E-10
nMOS 180n 3.4u

𝝎𝒑 𝟒𝟎
Device parameters for 2 – input CMOS NOR Gate with =
𝝎𝒏 𝟐𝟎
Library Name Cell Name Comments / Properties
gpdk180 nMOS W = 20u; L = 180n
gpdk180 pMOS W = 40u; L = 180n

𝝎𝒑 𝟒𝟎
Delay Elements for 2 – input CMOS NOR Gate with =
𝝎𝒏 𝟐𝟎
MOSFET Length Width tpLH tpHL tpd
pMOS 180n 40u
3.64E-11 1.55E-10 9.57E-11
nMOS 180n 20u

Layout View of NOR GATE

Fig NOR Gate Layout

Sample Questions

1. What is slack?
Slack' is the amount of time you have that is measured from when an event 'actually
happens' and when it 'must happen'.. The term 'actually happens' can also be taken as
being a predicted time for when the event will 'actually happen'. When something 'must
happen' can also be called a 'deadline' so another definition of slack would be the time

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from when something 'actually happens' (call this Tact) until the deadline (call this
Tdead). Slack = Tdead -Tact. Negative slack implies that the 'actually happen' time is
later than the 'deadline' time..in other words it's too late and a timing violation.you have a
timing problem that needs some attention.
2. What is glitch? What causes it (explain with waveform)? How to overcome it?
The following figure shows a synchronous alternative to the gated clock using a data
path. The flip-flop is clocked at every clock cycle and the data path is controlled by an
enable. When the enable is Low, the multiplexer feeds the output of the register back on
itself. When the enable is High, new data is fed to the flip-flop and the register changes its
state

Outcome Student will be able to create the schematic, verify schematic functionality and
device regions of operation by simulation and build the layout for the same in Cadence
Virtuoso.

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Design 3 - Construct the schematic using Boolean

Expression using CMOS-Logic
(Y = AB+CD+E)’
Objective

Verify the functionality of the expression find out the delay td for some combination of input
vectors.

Design

Library Name Cell Name Comments / Properties

gpdk180 nMOS W = 6u, L = 180n
gpdk180 pMOS W = 8.85u, L = 180n

Fig 3.1 Schematic of Boolean expression using CMOS - logic

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Symbol of Boolean expression using CMOS-logic

FUNCTIONAL SIMULATION:

The pull up and pull down network consist of combination of transistor, where two or more
transistors in series are ON only if all of the series transistors are ON. Two or more transistors in
parallel are ON if any of the parallel transistors are ON. This is illustrated in Figure 2 for nMOS
and pMOS transistor pairs. By using combinations of these constructions, CMOS combinational
gates can be constructed. In general, when we join a pull-up network to a pull-down network to
form a logic gate as shown in Figure 1, they both will attempt to exert a logic level at the output.
When both pull-up and pull-down are OFF, the high impedance or floating Z output state results.
This is of importance in multiplexers, memory elements, and tristate bus drivers. The crowbarred
(or contention) X level exists when both pull-up and pull-down are simultaneously turned ON.
Contention between the two networks results in an indeterminate output level and dissipates
static power. It is usually an unwanted condition.

Table 3.3 Test bench specifications

Library Cell Voltage Time Pulse DC

Name Name Name Period width Voltage
V0(A) 160n 80n
V1(B) 80n 40n
Vdc =
analogLib VPulse V2(C) 40n 20n
1.8V
V3(D) 20n 10n
V4(E) 10n 5n

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Fig 3.3 Test Bench Schematic for Boolean Expression using CMOS-Logic

Fig 3.4 Specifications for Analog Simulation with Spectre

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Fig 3.5 Simulation Window of Boolean expression using CMOS-logic

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Design 4 COMMON SOURCE AMPLIFIER WITH

PMOS CURRENT MIRROR LOAD
Objective

a) Capture schematic of Common Source Amplifier with PMOS Current Mirror Load and find its
transient response and AC response? Measures the Unity Gain Bandwidth (UGB), amplification
factor by varying transistor geometries, study the impact of variation in width to UGB.

b) Draw layout of common source amplifier, use optimum layout methods. Verify for DRC and
LVS, extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.

Design

Vout resistancein drain

Av = − =
Vin resistancein source
r01 || r02
Av =
1
g m1
Av = − g m1 (r01 || r02 )

Fig 3.1 Common Source Schematic

Table 3.1 Common Source Amplifier Device Specifications

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Library name Cell Name Properties/Comments

Model Name = pmos1, pmos2; W= 6u ; L=

gpdk180 pmos
180n

gpdk180 nmos Model Name =nmos1; W= 8.85u ; L= 180n

Table 3.2 Pin Direction

Pin Names Direction

vin vbias Input

vout Output

vdd vss Input

Fig 3.2 Common Source Amplifier Test bench design

Table 3.3 Test bench specifications

Library name Cellview name Properties/Comments
USN cs_amplifier Symbol
analogLib Vdc DC voltage = 3.3V (vdd)
analogLib Vdc DC voltage = 592m V (Vbias_N)
analogLib isin DC current = 100u A (Vbias P)
analogLib Vsin AC Magnitude = 1 V, Amplitude = 10u V, Frequency = 10K Hz
(Vin)
analogLib cap Capacitance = 500f F
AnalogLib Res Resistance = 10u Ohms
gnd

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Fig 3.3 Test Bench Schematic for Common Source Amplifier

Fig 3.4 Specifications for Analog Simulation with Spectre

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Fig 3.5 Expected Waveform for Common Source Amplifier

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Fig 3.6 Layout view of Common Source Amplifier

Sample Questions

1. Why do we gradually increase the size of inverters in buffer design? Why not give
the output of a circuit to one large inverter?
Because it can not drive the output load straight away, so we gradually increase the size
to get an optimized performance.
2. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How
do you avoid Latch Up?
Latch-up is a condition in which the parasitic components give rise to the Establishment
of low resistance conducting path between VDD and VSS with Disastrous results.
3. Give the expression for CMOS switching power dissipation?
CV2
4. What is Body Effect?
In general multiple MOS devices are made on a common substrate. As a result, the
substrate voltage of all devices is normally equal. However while connecting the devices
serially this may result in an increase in source-to-substrate voltage as we proceed
vertically along the series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1.

Outcome Student will be able to create the schematic, verify schematic functionality and
device regions of operation by simulation and build the layout for the same in Cadence
Virtuoso.

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Design 5 – TWO STAGE OPERATIONAL AMPLIFIER

Objective:
A. Capture schematic of two-stage operational amplifier and measure the following:
a. UGB
b. dB bandwidth
c. Gain margin and phase margin with and without coupling capacitance
d. Use the op-amp in the inverting and non-inverting configuration and verify its
functionality
e. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by varying the
stage wise transistor geometries and record the observations.
B. Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in
180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained in
simulation. Use optimum layout methods. Verify for DRC and LVS, extract parasitic and
perform post layout simulations, compare the results with pre-layout simulations. Record the
observations.

Design

Components for building the Differential Amplifier schematic.

Fig 2.1 Differential Amplifier Schematic

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Table 2.1Pins parameters

Pin Names Direction

Idc,V1,V2 Input

Vout Output

vdd, vss, Input

Fig 2.2 Symbol for Differential Amplifier

Fig Opamp Schematic

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Fig 5.2 OPAMP Symbol

Table 5.2 Test Bench Design Parameters

Library name Cellview name Properties/Comments

myDesignLib op-amp Symbol

Define pulse specification as

analogLib vsin AC Magnitude= 1; DC Voltage= 0;

Offset Voltage= 0; Amplitude= 5m;

Frequency= 1K

analogLib vdc, gnd vdd=2.5 ; vss= -2.5

analogLib Idc Dc current = 30u

Figure 5.3 Test Bench Schematic

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Fig 5.4 Analog Simulation with Spectre

Fig 5.5 Expected Testbench Waveform

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Fig 5.6 Expected Layout View

Sample Viva Questions

1) Why do we gradually increase the size of inverters in buffer design? Why not give
the output of a circuit to one large inverter?
Because it can not drive the output load straight away, so we gradually increase the size
to get an optimized performance.
2) What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How
do you avoid Latch Up?
Latch-up is a condition in which the parasitic components give rise to the Establishment
of low resistance conducting path between VDD and VSS with Disastrous results.
3) Give the expression for CMOS switching power dissipation?
CV2
4) What is Body Effect?
In general multiple MOS devices are made on a common substrate. As a result, the
substrate voltage of all devices is normally equal. However while connecting the devices
serially this may result in an increase in source-to-substrate voltage as we proceed
vertically along the series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1.

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Outcome Student will be able to create the schematic, verify schematic functionality and
device regions of operation by simulation and build the layout for the same in Cadence
Virtuoso.

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ASIC Digital Design

General Procedure for Digital Simulation

1. Initialize the cadence tools:
a. Login as ‘Lab’.
b. Open a terminal.
c. Navigate to the folder ‘cadence_db’
d. Navigate to the folder ‘Digital’
e. Run commands:
i. csh
ii. source cshrc
2. Navigate to work directory.
[Note: Navigate to folder where work folder is to be created. Create a new folder. In command
line use ‘mkdir’ instruction.]
3. Create the Verilog files for module and test bench using :
gedit <filename>.v
4. Run command : nclaunch
[Note: Change over to Multi step mode if already not in it.]
5. Navigate in file browser window to the work directory. Compile the file.
6. The complied design is available in ‘worklib’ folder. Elaborate the module in worklib.
7. The elaborated design is available as a module in ‘Snapshots’ folder. Simulate the test bench of
the respective module.
8. Two windows open: Design Browser and console. Go to design browser. Select the module. Click
on Send to waveform icon.
9. Waveform window opens. Change the Simulation time to a desired value*. Run the test bench.
10. Print the generated waveform to a file: File->Print to file
a. Set the path for saving the file.
b. Set the title for the Waveform**.
c. Click ‘OK’.
11. Close ‘NClaunch’ gui and all simulator windows.

General Procedure for Synthesis

1. In command prompt navigate to Digi_synth folder using following command:

cd /cadence_db/Digital/DIGI_SYNTH
2. To carry out synthesis, launch the Encounter tool using command: rc -gui
3. The command window shows command prompt as ‘rc’. Also the Encounter gui is opened.
4. In the rc command prompt run the following commands:
a. To initialize the setup for the synthesis edit the file name (flilename.v) and module name
(eg: module tr_buff) in rcrunfile.tcl.
b. Copy the module file to DIGI_SYNTH folder (which file / program needs to be
synthesized)

The Encounter gui shows the generated module from the design elaboration.

The synthesis result shows the timing analysis and the area of the synthesized design.

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Synthesized RTL is available in a file “OUTPUTHDL”

Create a file named Contraints_sdc.sdc

The timing constraints has three different parts in the constraint file:

a. Clock definition and clock constraints –

Clock definition
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clock"]
Clock rise time
set_clock_transition -rise 0.1 [get_clocks " clk "]
Clock fall time
set_clock_transition -fall 0.1 [get_clocks " clk "]
Uncertainties of Clock
set_clock_uncertainty 1.0 [get_ports " clk "]
b. Input port timing constraints –
Input port delay
set_input_delay -max 1.0 [get_ports " A"] -clock [get_clocks " clk "]
set_input_delay -max 1.0 [get_ports " B"] -clock [get_clocks " clk "]
c. Output port timing constraints –
Output port delay
set_output_delay -max 1.0 [get_ports " sum "] -clock [get_clocks " clk "]

Synthesis and Report/Output Analysis

Step 1: Getting Started

Make sure you close out all the Incisive tool windows first.

Synthesis requires three files as follows,

◦ Liberty Files (.lib)

◦ Verilog/VHDL Files (.v or .vhdl or .vhd)

◦ SDC (System Design Constraint) File (.sdc)

Step 2 : Creating an SDC File

As the Full Adder Program does not contain any Clock, SDC can be skipped as an
Input if you

wish to, else you could include only Area Constraints in form of commands during
synthesis such

as, set_dont_use *XL (Indicating not to use Larger Cells)

Step 3 : Performing Synthesis

The Liberty files are present in the below path,

/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
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The Available technology nodes are 180nm ,90nm and 45nm. In the terminal,
initialise the tools

with the following commands if a new terminal is being used.

- csh

- source /home/install/cshrc

The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.

The Following are commands to proceed,

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib

2. read_hdl {fa.v fa_4bit.v} //Reading multiple Verilog Files

3. elaborate

4. set_top_module four_bit_adder //Differentiating Top & Sub Module

5. set_dont_use *XL //Dont Use Cells with High Driving

Strength

6. synthesize -to_mapped -effort medium //Performing Synthesis Mapping and

Optimization

7. report_timing -unconstrained > counter_timing.rep

// Generates Timing report for worst datapath

and dumps into file

//-Unconstrained is to be given as no timing

constraints are given

8. report_area > counter_area.rep //Generates Synthesis Area report and dumps

into a file

9. report_power > counter_power.rep

//Generates Power Report [Pre-Layout]

10. write_hdl > counter_netlist.v //Creates readable Netlist File.

11. write_sdc > counter_sdc.sdc //Creates Block Level SDC

Commands 1-5 are intended for Synthesis process while 6-10 for Generating reports
and Outputs.

Note 1:-

1. The Cells given in the netlist can be checked in the .lib files for their properties.

2. The Max Operating Frequency does not apply for Purely Combinational Circuit.

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Experiment – 6
4- bit Adder
Aim: To develop the source code for 4-bit Adder by using VERILOG and obtain
the simulation and its test bench for verification, observe the waveform,
synthesize the code with technological library with given Constraints to
generate into a netlist, and tabulate the Area, Power and Delay for the
synthesized netlist and identify critical path.

Objectives:

a) Write Verilog Code for 4-bit adder

b) Verify functionality using Test-bench
c) Synthesize the design targeting suitable library and by setting area and
timing constraints
d) Tabulate the Area, Power and Delay for the Synthesized netlist
e) Identify Critical path

Theory:

4-bit Adder is a combinatorial circuit (not clocked, does not have any memory
and feedback) adding every bit position of the operands in the same time. Thus
it is requiring number of bit-Adders (full adders + 1 half adder) equal to the
number of bits to be added. The 4-bit adder is constructed by cascading full
adders (FA) blocks in series. One full adder is responsible for the addition of
two binary digits at any stage of the ripple carry. The carryout of one stage is
fed directly to the carry-in of the next stage.

Fig-1.1: 4 – bit Adder

Verilog Code Testbench Code

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/* fa.v → Single Bit 3-input Full Adder */ module test_4_bit;

reg [3:0] A;
module full_adder( A,B,CIN,S,COUT); reg [3:0] B; reg C0;
input A,B,CIN; wire [3:0] S; wire C4;
output S,COUT; four_bit_adder dut(A,B,C0,S,C4);
assign S = A^B^CIN; initial begin
assign COUT = (A&B) | (CIN&(A^B)); A = 4'b0011; B=4'b0011;C0 = 1'b0; #10;
endmodule A = 4'b1011;B=4'b0111;C0 = 1'b1; #10;
A = 4'b1111;B=4'b1111;C0 = 1'b1; #10;
/* fa_4bit.v → Top Module for Adding 4- end
bit Inputs */ initial
module four_bit_adder(A,B,C0,S,C4); #50 $finish;
input [3:0] A,[3:0] B,C0; Endmodule
output [3:0] S,C4;
wire C1,C2,C3;
full_adder fa0 (A[0],B[0],C0,S[0],C1);
full_adder fa1 (A[1],B[1],C1,S[1],C2);
full_adder fa2 (A[2],B[2],C2,S[2],C3);
full_adder fa3 (A[3],B[3],C3,S[3],C4);
endmodule

NOTE:
Three Codes are written for implementation of 4-bit Adder
◦ fa.v → Single Bit 3-input Full Adder [Sub-Module / Function]
◦ fa_4bit.v → Top Module for Adding 4-bit inputs
◦ fa_test.v → Test bench code for testing of 4-bit Adder design

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Waveform:

Synthesize Design:

Common SDC Constraints

Operating Conditions Timing

• Set_operating_conditions • create_clock
Wire-load models • create_generated_clock
• Set_wire_load_mode • set_clock_latency
• Set_wire_load_model • set_clock_transition
• Set_wire_load_selection_group • set_disable_timing
Environmental • set_propagated_clock
• set_drive • set_clock_uncertainty
• set_driving_cell • set_input_delay
• set_load • set_output_delay
• set_fanout_load Exceptions
• set_input_transition • set _false_path
• set_port_fanout_number • set _max_delay
Design rules • set _multicycle_path
• set_max-capacitance Power
• set_max_fanout • set _max_dynamic_power
• set_max_transition • set _max_leakage_power
SDC file with .sdc file extension

set_input_delay -max 0.8 [get_ports "A"]

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set_input_delay -max 0.8 [get_ports "B"]

set_input_delay -max 0.8 [get_ports "CO"]
set_output_delay -max 0.8 [get_ports "S"]
set_output_delay -max 0.8 [get_ports "C4"]
Synthesis RTL Schematic of 4-bit Adder:

Note-2: -

1. Tabulate Area, Power and Timing Constraints using any of the SDC
Constraints as instructed.

2. Make sure, during synthesis the Report File Names are changed so that the
latest reports do not overwrite the earlier ones.

RESULT: Verilog code for the 4-bit Adder circuit and its test bench for
verification is written, the waveform is observed and the code is synthesized
with the technological library and is verified.

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Experiment – 7
4-Bit Shift and Add Multiplier
Aim: To develop the source code for 4-bit shift and add multiplier using
Behavioral Modeling and obtain the simulation and its test bench for
verification, observe the waveform, synthesize the code with technological
library with given Constraints to generate into a netlist, and tabulate the Area,
Power and Delay for the synthesized netlist and identify critical path.

Objectives:

a) Write Verilog Code

b) Verify functionality using Test-bench
c) Synthesize the design targeting suitable library and by setting area and
timing constraints
d) Tabulate the Area, Power and Delay for the Synthesized netlist
e) Identify Critical path

Theory:

Binary multipliers are used for multiplication of 2 binary numbers and are
used mainly in signal processing and also in other computationally intensive
applications. Shift and add binary multiplier is a type of sequential multiplier.
Sequential multipliers generate the partial products sequentially and add each
newly generated partial product to the previously accumulated sum. Shift and
add binary multiplier is a type of sequential multiplier. Shift and add multiplier
is similar to multiplication done by paper and pencil. This method adds the
multiplicand X to itself Y times, where Y denotes the multiplier In the case of
binary multiplication, since the digits are 0 and 1, if the multiplier digit is 1, a
copy of the multiplicand is placed in the proper positions; if the multiplier digit
is 0, a number of 0 digits are placed. The 2n-bit product register (A) is
initialized to 0. A 2n-bit multiplicand register with the multiplicand placed in
the right half of the register and with 0 in the left half is used. The algorithm
starts by loading the multiplicand into the B register, loading the multiplier into
the Q register, and initializing the A register to 0. The counter N is initialized to
n. The least significant bit of the multiplier register (Q0) determines whether
the multiplicand is added to the product register. The left shift of the
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multiplicand has the effect of shifting the intermediate products to the left and
right shift prepares the next bit of the multiplier to examine in the following
iteration.

Fig 2.1: First Version of the Multiplier Circuit

Flowchart:

Figure 2.2: Flowchart of Shift and Add Multiplier Algorithm

Source Code:

Verilog Code: Testbench Code:

Timescale 1ns/1ns `timescale ins/lns

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module shift_and_add_binary_multiplier( module shift_add_binary_mu1tip1ier_tb;

clk,rst,A, B, C); parameter m=4, n=4,
parameter m=4, n=4; reg clk, rst;
integer i; reg [m-1:0] A;
input clk, rst; reg [n-l:0] B;
input [m-1:0] A; wire [m+n-l:0]
input [n-1:0] B; shift _and_add_binary_multip1ier uut(clk,
output reg [m+n-1:0] C; rst, A, B, C)
reg [m+n-1:0] A1; initial
reg [n-1:0] B1; begin
always@(posedge clk or posedge rst) clk = 1'b1;
begin forever #4 clk = ~clk;
if (rst) end
begin initial
C=0; begin
end rst = 1;
else #2 rst = 0;
begin A = 4'b1111;
C=0; B = 4'b1111;
A1 [m-1:0]=A; #20 rst = 1;
A1 [m+n-1:m]=0; #2 rst = 0;
B1=B; A = 4'b0011;
for (i=0;i<n;i=i+1) B = 4'b001l;
begin #20 rst = 1;
if (B1[i]==1'b0) #2 rst = 0;
begin A = 4'b1100;
C=C+0; B = 4'b0010;
end #20;
else if (B1[i]==1'b1) end
begin initial
C=C+(Al<<i); begin #l00 $finish;
end end
end endmudule

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end
end
endmodule

Waveform:

SDC file with .sdc file extension

create_clock -name clk -period 1 -waveform {0 0.5} [get_ports “clk”]

set_clock_transition -rise 0.1 [get_clocks “clk”]

set_clock_transition -fall 0.1 [get_clocks “clk”]
set_clock_uncertainty 0.01 [get_ports “clk”]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks “clk”]
set_input_delay -max 1.0 [get_ports "A"] -clock [get_clocks “clk”]
set_input_delay -max 1.0 [get_ports "B"] -clock [get_clocks “clk”]
set_output_delay -max 1.0 [get_ports "C"] -clock [get_clocks “clk”]

Synthesize Design of 4-bit shift and add multiplier circuit:

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RESULT: Verilog code for the 4 bit shift and add multiplier circuit and its test
bench for verification is written, the waveform is observed and the code is
synthesized with the technological library and given constraints and is verified.

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Experiment – 8
32-Bit ALU
Aim: To develop the source code for 32-bit ALU supporting 4-Logical and 4-
Arithmetic operations, using case and if statement for ALU Behavioral Modeling
and obtain the simulation and its test bench for verification, observe the
waveform, synthesize the code with technological library with given Constraints
to generate into a netlist, and tabulate the Area, Power and Delay for the
synthesized netlist and identify critical path.

Objectives:

a) Write Verilog Code

b) Verify functionality using Test-bench
c) Synthesize the design targeting suitable library and by setting area and
timing constraints
d) Tabulate the Area, Power and Delay for the Synthesized netlist
e) Identify Critical path

Theory:

An Arithmetic Logic Unit (ALU) is a digital circuit used to perform arithmetic

and logic operations. It represents the fundamental building block of the
central processing unit (CPU) of a computer. Most of the operations of a CPU
are performed by one or more ALUs, which load data from input registers.

A 32-bit ALU is a combinational circuit taking two 32-bit data words A and B
as inputs, and producing a 32-bit output Y by performing a specified arithmetic
or logical function on the A and B inputs.

Arithmetic Logic Unit (ALU) using these simple logic gates AND, OR, NOT, XOR
and other components. The ALU will take in two 32-bit values, and two control
lines. Depending on the value of the control lines, the output will be the
addition, subtraction, bitwise AND or bitwise OR of the inputs. The Fig. 3.1
shows the block diagram of 32-bit ALU.

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Fig-3.1: 32-bit ALU

Fig-3.2: Logic Diagram of 32-bit ALU

Verilog code:

Source Code – Using Case Statement: Source Code - Using If Statement:

module alu_32bit_case(y,a,b,f); module alu_32bit_if(y,a,b,f);
input [31:0]a; input [31:0]a;

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input [31:0]b; input [31:0]b;

input [2:0]f; input [2:0]f;
output reg [31:0]y; output reg [31:0]y;
always@(*) always@(*)
begin begin
case(f) if(f==3'b000)
3'b000:y=a&b; //AND Operation y=a&b; //AND Operation else if
3'b001:y=a|b; //OR Operation (f==3'b001)
3'b010:y=~(a&b); //NAND Operation y=a|b; //OR Operation else if (f==3'b010)
3'b011:y=~(a|b); //NOR Operation y=a+b; /Addition else if (f==3'b011)
3'b010:y=a+b; //Addition y=a-b; /Subtraction else if (f==3'b100)
3'b011:y=a-b; //Subtraction y=a*b; //Multiply else
3'b100:y=a*b; //Multiply y=32'bx;
default:y=32'bx; end
endcase endmodule
end
endmodule

Testbench code:

module alu_32bit_tb_case; module alu_32bit_tb_if;

reg [31:0]a; reg [31:0]a;
reg [31:0]b; reg [31:0]b;
reg [2:0]f; reg [2:0]f;
wire [31:0]y; wire [31:0]y;
alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f)); alu_32bit_if test(.y(y),.a(a),.b(b),.f(f));
initial begin initial begin
a=32'h00000000; b=32'hFFFFFFFF; a=32'h00000000;
#10 f=3'b000; b=32'hFFFFFFFF; #10 f=3'b000;
#10 f=3'b001; #10 f=3'b001;
#10 f=3'b010; #10 f=3'b010;
#10 f=3'b100; #10 f=3'b100;
end end initial
initial #50 $finish;

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#50 $finish; endmodule

endmodule

Waveform:

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Synthesize Design:

RTL Schematic of 32-bit Floating Point ALU with Pipelining

RESULT: Verilog code for the 32-bit ALU circuit and its test bench for
verification is written, the waveform is observed and the code is synthesized
with the technological library and given constraints and is verified.

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Experiment – 9
Flip-Flop
AIM: To write Verilog code for D, SR, JK Flip-flop, Synthesize the design and
compare the synthesis report.

Objectives:

a) Write Verilog code and testbench for D, SR, JK Flip Flop to check the
functionality.
b) Synthesize the designs and compare the report of its.

a) Flip Flops

i) D Flipflop

Theory:

D flip-flop The D flip-flop is widely used. It is also known as a "data" flip-flop.

The D flip-flop captures the value of the D-input at a definite portion of the
clock cycle (such as the rising edge of the clock). That captured value becomes
the Q output. At other times, the output Q does not change. The D flip-flop can
be viewed as a memory cell, a zero-order hold, or a delay line.

Block diagram:

Truth Table:

Verilog Code Test Bench Code

module DFF( Q,Qbar,D,Clk,Reset); module DFF_tb;
output reg Q; reg D, Clk, Reset; // Inputs
output Qbar; wire Q, Qbar; // Outputs
input D,Clk,Reset; // Instantiate the Unit Under Test (UUT)

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always @(posedge Clk) DFF uut ( .Q(Q), .Qbar(Qbar), .D(D),

begin .Clk(Clk), .Reset(Reset));
if (Reset == 1'b1) //If at reset initial begin
Q <= 1'b0; D = 1'b0; // Initialize Inputs
else Clk = 1'b0;
Q <= D; Reset = 1'b1;
End // Wait 100 ns for global reset to finish
assign Qbar = ~Q; #100;
endmodule // Add stimulus here
Reset = 1'b0;
#20;
forever #40 D = ~ D;
end
always #10 Clk = ~Clk;
endmodule

Constraint File:

create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]

set_clock_transition -fall 0.1 [get_clocks "clk"]

set_clock_uncertainty 0.01 [get_clocks "clk"]

set_input_delay -max 1 [get_ports "Reset"] -clock [get_clocks "clk"]

set_input_delay -max 1 [get_ports "D"] -clock [get_clocks "clk"]

set_output_delay -max 1 [get_ports "Q"] -clock [get_clocks "clk"]

set_output_delay -max 1 [get_ports "Qbar"] -clock [get_clocks "clk"]

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Simulation waveform and Synthesis:

ii) S R Flip Flop

Theory:

It can be seen that when both inputs S = “1” and R = “1” the outputs Q and Q
can be at either logic level “1” or “0”, depending upon the state of the inputs S
or R BEFORE this input condition existed. Therefore the condition of S = R =
“1” does not change the state of the outputs Q and Q. However, the input state
of S = “0” and R = “0” is an undesirable or invalid condition and must be
avoided. The condition of S = R = “0” causes both outputs Q and Q to be HIGH
together at logic level “1” when we would normally want Q to be the inverse of
Q. The result is that the flip-flop loses control of Q and Q, and if the two inputs
are now switched “HIGH” again after this condition to logic “1”, the flip-flop
becomes unstable and switches to an unknown data state based upon the
unbalance.

Logic diagram:

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Truth Table:

Verilog Code Test Bench Code

module SR_FF(S,R,clk,Q,Qbar); module SRFF_tb;
input S,R,clk; reg S, R; reg clk;
output Q,Qbar; // Outputs
reg M,N; wire Q, Qbar;
always @(posedge clk) // Instantiate the Unit Under Test (UUT)
begin SR_FF uut ( .S(S), .R(R), .clk(clk),
M = !(S & clk); .Q(Q), .Qbar(Qbar) );
N = !(R & clk); initial begin
end // Initialize Inputs
assign Q = !(M & Qbar); clk = 1'b0;
assign Qbar = !(N & Q); S =1'b0;
endmodule R=1'b0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
S =1'b1;R=1'b0;
#20 S =1'b0; R=1'b1;
#10 S =1'b0; R=1'b0;
#30 S =1'b1; R=1'b1;

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#200 $finish;
end
always #10 clk = ~clk;
endmodule
Simulation output:

Constraint File:

create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]

set_clock_transition -fall 0.1 [get_clocks "clk"]

set_clock_uncertainty 0.01 [get_clocks "clk"]

set_input_delay -max 1 [get_ports "S"] -clock [get_clocks "clk"]

set_input_delay -max 1 [get_ports "R"] -clock [get_clocks "clk"]

set_output_delay -max 1 [get_ports "Q"] -clock [get_clocks "clk"]

set_output_delay -max 1 [get_ports "Qbar"] -clock [get_clocks "clk"]

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Simulation waveform and Synthesis:

iii) JK Flip Flop

Theory:

Then the JK flip-flop is basically an SR flip-flop with feedback which enables

only one of its two input terminals, either SET or RESET to be active at any one
time thereby eliminating the invalid condition seen previously in the SR flip-flop
circuit. Also when both the J and the K inputs are at logic level “1” at the same
time, and the clock input is pulsed either “HIGH”, the circuit will “toggle” from
its SET state to a RESET state, or visa-versa. This result in the JK flip-flop
acting more like a T-type toggle flip-flop when both terminals are “HIGH”
Although this circuit is an improvement on the clocked SR flip-flop it still
suffers from timing problems called “race” if the output Q changes state before
the timing pulse of the clock input has time to go “OFF”. To avoid this the
timing pulse period ( T ) must be kept as short as possible (high frequency). As
this is sometimes not possible with modern TTL IC’s the much improved
MasterSlave JK Flip-flop was developed

Block and Logic diagram:

Truth Table:

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Verilog Code Test Bench Code

module jkff(J, K, clk, Q, Qm); module JKFF_tb;
input J, K, clk; reg J, K,,clk; // Inputs
output reg Q; wire Q, Qm; // Outputs
output Qm; // Instantiate the Unit Under Test (UUT)
always @(posedge clk) jkff uut ( .J(J), .K(K), .clk(clk), .Q(Q),
begin .Qm(Qm) );
if(J == 0 && K == 0) initial begin
Q <= 0; // Initialize Inputs
else if(J == 1 && K == 0) clk = 1'b0;
Q <= 1; J =1'b0;
else if(J == 0 && K == 1) K=1'b0;
Q <= 0; // Wait 100 ns for global reset to finish
else if(J == 1 && K == 1) #10;
Q <= ~Q; // Add stimulus here
end J =1'b1; K=1'b0;
assign Qm = ~Q; #20 J =1'b1; K=1'b1;
endmodule #10 J =1'b1; K=1'b0;
#30 J =1'b1; K=1'b1;
#30 J =1'b0; K=1'b0;
#200 $finish;
end
always #10 clk = ~clk;
endmodule

Simulation output:

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Constraint File:

create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]

set_clock_transition -fall 0.1 [get_clocks "clk"]

set_clock_uncertainty 0.01 [get_clocks "clk"]

set_input_delay -max 1 [get_ports "S"] -clock [get_clocks "clk"]

set_input_delay -max 1 [get_ports "R"] -clock [get_clocks "clk"]

set_output_delay -max 1 [get_ports "Q"] -clock [get_clocks "clk"]

set_output_delay -max 1 [get_ports "Qbar"] -clock [get_clocks "clk"]

Simulation waveform and Synthesis:

RESULT: Verilog code for D, SR, JK Flip-flop and its test bench for verification
is written, the waveform is observed and the code is synthesized with the
technological library and given constraints and is verified.

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Experiment – 10
Four-bit Synchronous MOD-N counter with Asynchronous reset

Aim: To develop the source code for 4-bit Synchronous MOD-N counter with
Asynchronous reset, verify the functionality using Test bench and Synthesize
the design and compare the synthesis

report.

Objectives:

a) Write Verilog Code

b) Verify functionality using Test-bench
c) Synthesize the design targeting suitable library and by setting area and
timing constraints
d) Tabulate the Area, Power and Delay for the Synthesized netlist
e) Identify Critical path

Theory: MOD-N Counter

Counters are sequential logic devices that follow a predetermined sequence of

counting states triggered by an external clock (CLK) signal. The number of
states or counting sequences through which a particular counter advances
before returning to its original first state is called the modulus (MOD). In other
words, the modulus (or modulo) is the number of states the counter counts and
is the dividing number of the counter.

Modulus Counters, or MOD counters, are defined based on the number of

states that the counter will sequence before returning to its original value.

For example, a 2-bit counter that counts from 002 to 112 in binary, 0 to 3 in
decimal, has a modulus value of 4 ( 00 → 1 → 10 → 11, and return to 00 );
therefore, be called a modulo-4, or mod-4, counter. Note also that it has taken
four clock pulses to get from 00 to 11.

In this example, there are only two bits ( n = 2 ) then the maximum number of
possible output states (maximum modulus) for the counter is 2n = 22 or 4.
However, counters can be designed to count to any 2n states in their sequence
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by cascading together multiple counting stages to produce a single modulus or

MOD-N counter.

Therefore, a "Mod-N" counter will require the "N" number of flip-flops connected
to count a single data bit while providing 2n different output states (n is the
number of bits). Note that N is always a whole integer value. Then we can see
that MOD counters have a modulus value that is an integral power of 2, that is,
2, 4, 8, 16 and so on to produce an n-bit counter depending on the number of
flip-flops used, and how they are connected, determining the type and modulus
of the counter.

Fig-3.1: MOD-N Counter

Fig-3.2: Logic Diagram of MOD-N Counter

Verilog code:

module modN_ctr
#(parameter N = 10, parameter WIDTH = 4)
(input clk, input rstn, output reg [WIDTH-1:0] out);
always @ (posedge clk) begin
if (!rstn) begin
out <= 0;
end else begin
if (out == N-1)
out <= 0;
else
out <= out + 1;
end
end
endmodule

Testbench code:
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module tb;
parameter N = 10;
parameter WIDTH = 4;
reg clk;
reg rstn;
wire [WIDTH-1:0] out;
modN_ctr u0 (.clk(clk), .rstn(rstn), .out(out) );
always #10 clk = ~clk;
initial begin
{clk, rstn} <= 0;
$monitor ("T=%0t rstn=%0b out=0x%0h", $time, rstn, out);
repeat(2) @ (posedge clk);
rstn <= 1;
repeat(20) @ (posedge clk);
$finish;
end
endmodule

Waveform:

Synthesize Design:

RTL Schematic of 4-bit MOD N Counter

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RESULT: Verilog code for the 4-bit Synchronous MOD-N counter circuit and its
test bench for verification is written, the waveform is observed and the code is
synthesized with the technological library and given constraints and is verified.

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Procedure for Physical Design

Physical Design can be done by invoking the tool ―Encounter Digital
implementation‖.
1. Go to Directory /NCO/rclabs/work.
2. Invoke the tool using ―encounter‖ or
―velocity‖. The tool starts as below image:

The terminal window and tool window can be seens as similar to images on next page

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3. Go to the Tool window and click on the File and select Import Design. A
newwindow will open.

4. Select the verilog files, power nets, lef files and view files using load button. A
newwindow ―Load Global Files‖ will open.

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5. Click on the back button and select the ―NCO_globals‖ file and click the
Open button.

6. Click on Auto assign after top cell.

7. Select OK. The tool window will look like image on next page.

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The pink colour blocks are the standard cells. This is floorplan view of the design.

8. Click on Floorplan and select ―Specify Floorplan‖.

Select the Aspect Ratio as per the requirement. Give some dimension in ―Core to left‖,
―Core to right‖, ―Core to top‖,―Core to bottom‖. e.g. give 30 to each. This is to create
the space for Power rings which will be created in power planning. Click OK and the
Tool window will be look like as below.

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The core dimensions are changed.

9. Click on Floorplan and select Automatic Floorplan and select Plan Design. Click
Ok. This will automatically put the Macros if there are any in the design.

10.Next step is to do power planning. Click on power, select power planning and click
onAdd Rings.

11. Select the top and bottom layer as Metal5, Left and Right as Metal6. Set the
width as per the requirement and taking the space between core boundary and I/O
pad considerations. Select the option for offset as ―center in channel‖ and click OK.
The power ring will get created in between the channel. The image on the next
page is showing the power ring created.

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12. The next step in power planning is to create power strips. Select Power,
clickPower Planning and click Add Stripe.

13. For adding the stripes, select metal layer as Metal 6 and chose direction as
vertical(if direction chosen is horizontal, chose metal layer as Metal 5). Click
OK and the design will get the vertical thin strips of type Metal 6.

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14. After the power planning, go to Route and click Special Route. A new
WindowSroute will appear.

15. Click OK with all default settings. This is done to provide power to standard
cells.The horizontal blue coloured metal1 stripes created as a result of Special
Route.

16. For placement, click on place and select place and click on Place Standard Cell.

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17. Click OK on Place window and in physical view the blue coloured standard
cellscan be seen as a result of placement of standard cells.

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18. Before CTS, timing analysis has to be done for any setup violations. Click on
Timing, and select Report Timing. A Timing analysis window will get open.
In the window select the ―Pre-CTS‖ as Design Stage and select the
―Setup‖ as Analysis Type.

19. Click OK to complet the Timing analysis. The timing information will get
display on terminal in tabular form. In the table displayed on the terminal
under
―timeDesign Summary‖, check for any negative value under
WNS(Worst Negative Slack) and TNS(Total Negative Slack). The terminal
will look as the image below and Tool window as on next page.

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The multi-coloured lines visible in the tool window are the connections between
standard cells using metal layers. If any part of this design is Zoom-in, metal layers
can be viewed easily.

Different colours show different metal

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20. If there is any of the negative slack value under WNS or TNS, click Optimize in
Tool window and Select Optimize Design. A new window ―Optimization‖
will get open. Select ―Pre-CTS‖ as Design Stage and ―Setup‖ as optimization
type and click OK. The tool will optimize the design and the optimized timing
results will be displayed over terminal again.

In this case we did not get any negative slack, so this step is skipped here.

21. Go to Clock, click ―Synthesize Clock Tree‖, a new window ―Synthesize

Clock Tree‖ will get open.

22. Click on Gen Spec and a new window ―Generate Clock Spec‖ will open.

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23. From Cells List, Select all clocks starting with ―CLK‖ and click on Add button
to add them to the Selected Cells. Select a name for Output specification.

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24. Click OK. Then specify a name for Results Directory. and click OK. The
toolwindow looks like the image below.

25. Again Perform the Timing by clicking on Timing and selecting Report Timing.
Select ―Post-CTS‖ under Design Stage and do the select ―Set-up‖ as
Analysis Type.

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26. Click Ok to perform the timing. The timing information will be displayed over
theterminal window. Again check for any negative slacks under WNS or TNS.

27. If there is any negative value found for either of WNS or TNS then perform
the Optimization Technique to reduce the negative slack. No negative slack is
found in the terminal image on previous page so this step is skipped here.

28. Timing Analysis for ―Setup‖ as Analysis Type is done. Repeat Step 27
for performing timing for ―Post CTS‖ as Design Stage and ―Hold‖ as Analysis
Type. The tool will show the timing results in the terminal window.

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29. After Timing Analysis is performed, the timeDesign Summary is showing the
negative slack values for both TNS and WNS. Perform the Optimization. Go to
Optimize and click on Optimize Design. Select ―Post-CTS‖ as and ―HOLD‖
as the Optimization Type

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30. Click OK to perform the Optimization and Tool will perform the optimization
and displays the optimized results in the terminal window under timeDesign
Summary. The results of Optimization can be seen on the next page in tabular
form for both Setup and Hold mode. As compare to the Timng Results
performed for Hold mode in Step 30, the design has been optimized and
tabular results shows that all slack values are now positive values and no
more negative values for slack.

31. Perform Routing by clicking Route, and select NanoRoute and then click
Route.A window NaoRoute will open.

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32. Click Ok to Perform Routing. The tool will Perform the Routing and the
Routingstatistics can be seen on terminal window including DRC violations.

33. After routing tool window looks like the below image.

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34. Perform the timing again. Go to Timing, seelct Report Timing and a Timing
Analysis window will get open. Select ―Post-Route‖ as the Design Stage
and
―Setup‖ as Analysis Type. Click Ok. The timing results will be displayed in
terminal window for Set up mode.

Since there is no negative value of slack so design does not require optimization for
Set-up mode in Post-Route stage.

35. Repeat Step 36 for ―Post-Route‖ as Design Stage and ―Hold‖ as the
Analysis Type. Click OK. The timing results can be seen in the terminal
window for hold mode.

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As there is no negative value of slack, the optimization is not require to perform.

Thefinal view of the circuit is as below:

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Demonstration Experiments (For CIE)

Demo 1 - Implementation of 6T-SRAM
Objectives:
a. Schematic Capture and Simulation of 1-bit 6T -SRAM Virtuoso Schematic Editor.
b. Creating Layout of Bit-Cell Using Virtuoso Layout Editor.
Solution – (a): SCHEMATIC CAPTURE:
Following the techniques demonstrated in Lab – 01, Create a New Library using
the option “File → New → Library”, create a New Cell View upon selecting the
newly created library using the option “File → New → Cell View” and instantiate the
required devices using the “Create → Instance” option. The device parameters are
listed in Table – 1.
Width and Length of NMOS and PMOS Transistors
Library Name Cell Name Comments / Properties
gpdk180 nMOS W = 2u; L = 180n
gpdk180 pMOS W = 2u; L = 180n

SRAM BITCELL_SNM SCHEMATIC

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THE SYMBOL OF SRAM_BIT_CELL_SYMBOL

Simulation of Bit Cell:

Procedure to set up stimulus values in ADE L:
● Launch ADE L window: In ADEL window Left side Design variable Right click copy from
Cellview.
● Select “Stimulus Type → Inputs” and the WORD ,VDD and VSS get listed out as shown in
Figure below
● Select WORD Inputs, click on “Enabled” and select “Function → bit”. Mention the value of
dc voltages is 1.8”.
● Select VDD Inputs, click on “Enabled” and select “Function → bit”.Mention the value of dc
voltages is 0”.
● Select VSS Inputs, click on “Enabled” and select “Function → bit”.Mention the value of dc
voltages is 1.8”.
● Select the type of Analysis to be performed on the sram_bit_cell.
● Select the Input and Output Signals to be plotted.
The ADE L window gets updated as shown in Figure

Launch ADE L, select “Setup → Stimuli” as shown in Figure below to give the required

sequence of inputs to pins A and B. The “Setup Analog Stimuli” window.

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● Run the Simulation to check for the functionality of the sram_bit_cell.

● Use YvsY plot [right click on x axis ] (QvsQb) Option in graph to get the butterfly curve on the
graph.

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SENES AMPLIFIER

Figure: sense amplifier schematic

SETUP FOR SRAM_READ_OPERATION:

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Figure – sram_read_operation_test_schematic

Figure – sram_read_operation_result

SRAM_WRITE_OPERATION:

Figure – : sram_read_write_schematic

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Figure – : sram_write_operation_result

Solution – (b): LAYOUT:

Follow the techniques demonstrated in Lab – 01 to open the Layout Editor, import the devices

from the Schematic, place the devices as per the requirement and complete the routing. The

completed layout can be seen as shown in Figure below.

Figure –: Layout for BIT CELL

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