Lecture 6
Lecture 6
CSE 1612
Level#1
2
The basic components of any digital
computer
Digital
Computer
Processor
Control unit
Unit
Micro Internal
Hardwired ALU Registers
programmed Buses
AU LU
Logic design of a digital system
The logic design of a digital system can be divided into two distinct parts.
◦ First part is concerned with the design of the digital circuits that performs the data processing operations.
◦ Second part is concerned with the design of the control circuit that supervises the operations and
determines the sequence in which they are executed.
The relationship between the control logic and the data processor subsystems in a digital system is
shown in Figure.
CU design
Control
Organization
In the hardwired organization, the control logic is implemented with gates and
flip-flops similar to a sequential circuit. It has the advantage that it can be
optimized to produce a fast mode of operation.
Fast Slow
Because of the large number of control signals used in a typical CPU and their
dependence on the particular instruction set being implemented, the design
methods employed in practice are often hard in nature, and therefore cannot
easily be formalized.
Therefore
Sequence Counter
• First, we will explain how the modulo-K sequence counter operates internally.
• If the count enable input is connected to a clock source, the counter cycles
continually through its k-states.
• Two additional input lines and a flip-flop are provided for turning the counter on
and off.
Sequence counter method
Basic operations:
• We will show how to use the modulo-K sequence counter to control the sequence of execution of a
program.
Example : Consider the hypothetical CPU, simple accumulator based CPU before. Assuming that it is
required to execute the set of eight one address instructions listed below, show how to design a simple
control unit to perform the following program using Sequence counter method.
Sequence counter method
Fetch Cycle
1. AR PC
2. Read M Increment PC and decode the instruction
3. PC PC+1
IR DR(OP)
Execution Cycle Transfer the Operand address to memory
4. AR DR(ADR) address Register
5. Read M
6. Execute
Fetch the operand from memory
• We take two memory
cycle(clks) for each read or
write from memory. Perform the Operation specified in the
• We take one memory cycle instruction
(clk) for other operations
Sequence counter method
• Flow chart of program execution for any
of 8 instructions
Sequence counter method
• Flow chart of program execution for any
of 8 instructions
𝐶 ɸ
𝐶 ɸ ,
𝐶 ɸ
𝐶 ɸ
𝐶 ɸ 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ
𝐶 ɸ , 𝐶 ɸ 𝐶 ɸ , 𝐶 ɸ ,
𝐶 ɸ 𝐶 ɸ , 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ
Sequence counter method
• The microperations in this flowchart determine the control signals and control points needed in the CPU.
• The following table lists a suitable set of control signals and their functions.
𝑪𝟗 AC <- AC+DR
𝑪𝟏𝟐 AC <- 𝑨𝑪
For example, C2, which causes a memory read operation to take place, is
defined by the following logic equation:
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Sequence counter method
• Flow chart of program execution for any of 8 instructions
𝐶 ɸ
𝐶 ɸ ,
𝐶 ɸ
𝐶 ɸ
𝐶 ɸ 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ
𝐶 ɸ , 𝐶 ɸ 𝐶 ɸ , 𝐶 ɸ ,
𝐶 ɸ 𝐶 ɸ , 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ 𝐶 ɸ
Task
Design a Hardwired control unit that performs the following
operations:
M[x] AC + M[x]
Solution
1.ADD x --- AC AC + M[x]
2.Store x --- M[x] AC
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Task
Design a Hardwired control unit that performs the following
operations:
1.Store x --- M[x] AC
2.ADD x --- AC AC + M[x]
3.AND x --- AC AC ^ M[x]
4.COMP --- AC 𝑨𝑪
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Task
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Task
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Task
Design a Hardwired control unit that performs the following
operations:
R1 SHR(R2+R3)
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