4740 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 43, NO.

12, DECEMBER 2024

MMM: Machine Learning-Based Macro-Modeling

for Linear Analog ICs and ADC/DACs
Yishuang Lin , Member, IEEE, Yaguang Li , Meghna Madhusudan, Sachin S. Sapatnekar , Fellow, IEEE,
Ramesh Harjani , Fellow, IEEE, and Jiang Hu , Fellow, IEEE

Abstract—Performance modeling is a key bottleneck for analog effectiveness of MOR is mostly restricted to linear circuits and
design automation. Although machine learning-based models it is very difficult to apply MOR on ADC/DACs.
have advanced the state-of-the-art, they have so far suffered An alternative to simulation-based approaches uses data-
from huge data preparation cost, very limited reusability, and
inadequate accuracy for large circuits. We introduce ML-based fitted/trained models, e.g., the early work on polynomial
macro-modeling techniques to mitigate these problems for linear models [4] and support vector machine (SVM) models [5].
analog ICs and ADC/DACs. The modeling techniques are based Recently, the development of neural network technology has
on macro-models, which can be assembled to evaluate circuit significantly advanced the progress of methods in this cate-
system performance, and more appealingly can be reused across gory. Applications of artificial neural networks (ANNs) for
different circuit topologies. On representative testcases, our
method achieves more than 1700× speedup for data preparation AMS circuit modeling include [6], [7], [8]; convolutional neu-
and remarkably smaller model errors compared to recent ML ral networks (CNNs) are used for analog placement solutions
approaches. It also attains 3600× acceleration over SPICE assessment in [9]; and graph convolutional network (GCN)
simulation with very small errors and reduces data preparation methods have been employed for estimating performance in
time for an ADC design from 40 days to 9.6 h. reinforcement learning-based analog transistor sizing [10].
Index Terms—Electronic design automation, machine learning, A customized graph neural network (GNN) technique is
macro modeling, performance modeling. developed for analog circuit performance classification in [11].
In [12], GNN is applied on analog circuit DC voltage
prediction. In [13], neural network-based transistor models are
I. I NTRODUCTION constructed and integrated with symbolic analysis. Overall,
machine learning-based models become a widespread trend
HE LACK of performance models that are simulta-
T neously fast and accurate is a primary reason why
analog/mixed signal (AMS) design automation has not
due to their promising results on fast performance estimation
time and generally good accuracy.
However, challenges also exist for machine learning-based
achieved as much success as its digital counterpart. The
models. The preparation of ML training data relies on cir-
use of SPICE simulations for performance estimation in
cuit simulations, which makes it computationally expensive.
circuit optimization is very limited due to their expensive
Even assuming 20 min for simulating a large circuit (actual
computational cost. In order to overcome this bottleneck,
simulation times could be larger), it takes half a month of
there has been extensive research on fast circuit modeling
simulation time to obtain 1000 data samples. The expensive
techniques. Symbolic analysis [1] and model order reduction
data preparation is exacerbated by the diverse performance
(MOR) [2] are two early approaches, which mathematically
metrics for different analog circuits [e.g., performance met-
derive equations of circuit transfer functions or performance.
rics of operational transconductance amplifier (OTA) include
In [3], symbolic analysis is integrated with graph represen-
gain, bandwidth (BW), and phase margin (PM), while low-
tations. However, the number of symbolic elements grows
dropout regulator (LDO) is evaluated by dropout voltage and
exponentially with respect to the size of circuit and thus
power supply rejection ratio (PSRR)], unlike digital circuits,
restricts symbolic analysis to small circuits. Similarly, the
where the metrics are uniform (power/performance/area). This
implies poor model reusability across analog circuits. A
Manuscript received 20 September 2023; revised 3 January 2024 and 11
April 2024; accepted 11 April 2024. Date of publication 19 June 2024; date
machine learning model trained from OTA is difficult to
of current version 22 November 2024. This work was supported in part by work for LDO. In addition, it is noticed in [7] that the
NSF under Grant CCF-2106725 and Grant CCF-2212346, and in part by accuracy of ANN models drops remarkably when circuit sizes
SRC under Grant GRC-CADT-3013.001. This article was recommended by
Associate Editor G. G. E. Gielen. (Corresponding author: Yishuang Lin.)
or performance range increases.
Yishuang Lin, Yaguang Li, and Jiang Hu are with the Department A few prior efforts attempt to resolve the issue of high-data
of Electrical and Computer Engineering, Texas A&M University, College preparation cost. The work in [6] shows model transferability
Station, TX 77843 USA (e-mail: [email protected]; [email protected];
[email protected]).
from schematic to layout for the same circuit, while the
Meghna Madhusudan, Sachin S. Sapatnekar, and Ramesh Harjani are model for one type of circuit does not apply for a different
with the Department of Electrical and Computer Engineering, University circuit type. In [10], knowledge transfer is restricted among
of Minnesota Twin Cities, Minneapolis, MN 55455 USA (e-mail:
[email protected]; [email protected]; [email protected]).
different process technology nodes of the same circuit design.
Digital Object Identifier 10.1109/TCAD.2024.3416894 The work in [9] explores transfer learning for CNN models.
1937-4151 
c 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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LIN et al.: MMM: MACHINE LEARNING-BASED MACRO-MODELING FOR LINEAR ANALOG ICs AND ADC/DACs 4741

However, it requires much more training data for CNN models b) Accuracy of Circuit Performance Estimation:
than GNN models [11]; moreover, the knowledge transfer MMM achieves less than 1% modeling error
in [11] is restricted between two different topologies of the compared to SPICE, significantly lower than 6%
same type of circuits. In the work of circuit connectivity of ANN, 6% of CCI-NN, 4% of MTL, 4% of
inspired neural network (CCI-NN) [7], some circuit knowledge MOR, 4% of GNN, and 9% of NN-based symbolic
is pre-embeded into ANN models to reduce training samples analysis.
generation cost. In addition to the efforts attempting to reduce c) Runtime Cost of Circuit Performance Estimation:
data preparation cost, multi-task learning (MTL) is applied MMM is 3639×, 1873×, 42×, 2.9×, and 61%×
in [14] to reduce ML model training cost, where multiple tasks faster than SPICE, NN-based symbolic analysis,
are solved jointly. MOR, CCI-NN, and MTL, respectively.
We propose a new approach of sub-circuit level ML- d) ML Model Training Cost: MMM obtains training
based macro-modeling (MMM) with the objectives of largely time reduction of 2462×, 4520×, 5469×, and
reducing ML performance model construction cost via model 18255× compared to ANN, CCI-NN, GNN, and
reuse and improving model accuracy at the same time. NN-based symbolic analysis, respectively.
Although in [13] transistor level ML models can also be To the best of our knowledge, this is the first study
reused, they are too fine-grained and the consequently frequent on ML-based macro-models modeling for linear analog
calls to such models substantially slow down the estimation ICs and ADC/DACs with exploration of deep learning
of circuit level performance. A CCI-NN [7] is composed models.
by a set of sub-NNs, which appear to be similar to our
macro-models, but there is a critical difference: CCI-NN must
train the entire NN for a whole circuit and cannot train sub- II. R ELATED W ORKS
NNs individually. In contrast, each macro-model in MMM is Circuit performance modeling research has a long his-
independently trained. This difference leads to two significant tory [4], [13], [16], [17], [18], [19], [20]. In [13], transistor
consequences. First, the output of a sub-NN in [7] is generally drain-source current and small signal parameters are estimated
not associated with any physical meaning and therefore a sub- by neural networks, whose input features are transistor sizes
NN is very difficult, if not impossible, to be reused in a and terminal voltages. This method cannot scale to large
different type of circuit. Second, CCI-NN is restricted to use circuits as the models are not reusable and require separate
only neural network models while our MMM supports almost training for different circuits. Nonlinear regression model is
any ML models, including random forest (RF) and XGBoost. applied in [16] which could scale from the circuit space to the
As a result, the data preparation cost of CCI-NN is over design space. However, the equation models cannot capture
300× more than that of MMM and MMM achieves smaller higher-order details of the circuit characteristics and thus the
errors than CCI-NN with 2.9× shorter circuit performance fitting error is not satisfied. A variety of modeling methods
estimation time. The experiment part includes multi-stage have also been applied in circuit performance prediction,
amplifiers and ADC/DACs which are constituted with multiple such as symbolic analysis [13], [17], polynomial model [18],
sub-circuits. These representative circuits are widely used in Gaussian process [19], and Bayesian model [20].
circuit modeling works [7], [13]. Case studies for performance Recently, with rapid development of machine learning tech-
metrics unity gain frequency (UGF) and spurious free dynamic niques, a variety of ML-based circuit performance modeling
range (SFDR) are also compared. techniques have been explored. SVM is employed in [5] and
The contributions of this work include the following. [21] for circuit performance prediction in terms of classifi-
1) We propose techniques for building sub-circuit level cation and regression problems. SVM-based approaches are
macro-models that can be reused in performance esti- also applied with interface modeling and assume-guarantee
mation of linear analog ICs and ADC/DACs, which are reasoning for compositional and hierarchical analysis and
two types of common AMS circuits. In addition, we also design in [22], [23], and [24] for larger AMS systems, includ-
consider variable loading effects between sub-circuits in ing non-linear systems and RF systems. In [5], a projection
the MMMs. algorithm is used to assess the quality of the approximation
2) The effectiveness of MMM are validated on multiple model of the same circuit at different levels of hierarchy using
linear analog ICs and ADC/DACs, including cir- the same underlying model and has preferred utilization in
cuits with feedbacks and a circuit with over 20K top-down design flows for system-level and component-level
devices. performance metrics. The work in [7] makes use of ANN to
3) Comparisons are made with recent ML approaches of model circuit performance. In [6], transfer learning is applied
ANN [6], CCI-NN [7], MTL [14], GNN [11], and to transfer the knowledge to different technologies or post-
NN-based symbolic analysis [13] as well as MOR [15] layout design. Although the above works take the advantages
to show the following advantages of MMM. of machine learning techniques, their models are used for flat
a) Training Data Preparation Time: MMM achieves circuits performance evaluation. Thus, a separate model is
data preparation speedup of 1788×, 1791×, 357×, required for different circuits.
1787×, and 885× versus ANN, GNN, CCI-NN, Some works [25], [26], [27], [28], [29] apply hierarchical
MTL, and NN-based symbolic analysis. For an approaches, which decompose large circuits into small ones
8-bit flash ADC design, MMM reduces the data and analyze them individually. The work of [26] uses graph
preparation time from 40 days to 9.6 h. method to decompose large circuits into tree structure and
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4742 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 43, NO. 12, DECEMBER 2024

Our ML model development for macro-models has a

key difference from previous work of flat parameter-to-
performance (P2M) mapping models [6], [7], [11]. For a flat
P2M ML model, its outputs are simply the circuit performance
metrics. For example, the outputs of an ML-based performance
model for OTA can be gain, PM, BW and UGF. In contrast, the
outputs of ML-based macro-models need to be more general
instead of specific performance metrics such that they can be
applied for different circuits. In addition, we need to consider
how to assemble macro-models to form the performance model
for an entire circuit. To these ends, we develop parameters
to output voltages (P2V) ML modeling techniques, who map
circuit parameters to time- and frequency-domain voltages.
Another difference from flat models is that loading effects are
considered in macro-models, as each sub-circuit is impacted by
input and output impedance from other connected sub-circuits.
Fig. 1. Fully differential two-stage OTA composed by a one-stage OTA and
two CSAs. A two-stage VGA composed by a one-stage VGA and two CSAs.
MMM currently can be applied to the following types of
designs.
analyze each leaf node circuit separately. However, as the 1) Linear Analog ICs, Such as OTAs: For these circuits,
loading effect of each leaf node circuit is not considered, the frequency-domain modeling introduced in Section IV
leaf node has different characteristics in different large circuits is able to estimate circuit performance, including gain,
and needs to be analyzed individually. In [27], a large circuit UGF, BW, etc. Besides, for any circuits that can
system is modeled by a module link graph. The graph is be described by a linear time-invariant (LTI) system,
divided into several small graphs, each of which represents a frequency-domain modeling is able to estimate their
small module in the large circuit system. A neural network circuit performance.
corresponding to the graph is built to model the circuit. 2) ADC/DACs Without Feedback: Given a sequence of
Although the interaction between modules is considered by voltages in discrete time steps as the input of a circuit,
adding edges between these graphs, the neural network is our time-domain modeling in Section V can estimate
trained in a flat manner so that the trained neural network the output voltages sequence of the circuit. The circuit
cannot be reused in different circuits. performance estimation method for ADC/DACs without
feedback is shown.
To our knowledge, this is the first systematic study of
III. G OALS , S TRATEGY, AND S COPE OF MMM ML-based hierarchical modeling for AMS circuits with explo-
A macro-model is a model for a sub-circuit that appears in ration of deep learning models. The above test cases provide
one or multiple different circuits as a component. In Fig. 1, the a proof of concept that the method presents a promising
two-stage OTA is composed of a one-stage OTA sub-circuit direction that can be extended to other types of circuits in
and two sub-circuits of common source amplifiers (CSAs). future.
Similarly, a one-stage variable gain amplifier (VGA) and two The proposed MMM framework is structured as follows.
CSAs compose the two-stage VGA. By assembling the macro- 1) Offline Macro-Model Training: Machine learning-based
models of corresponding sub-circuits, the performance of a macro-models are trained for a set of commonly
circuit, e.g., either the two-stage OTA or the two-stage VGA, used sub-circuits. Almost any machine learning engines
can be obtained. Since the CSA appears multiple times in the can be adopted, e.g., neural network and RF. The
two circuits, its macro-model is reused multiple times. labels of training data are obtained through circuit
The broad goal of this work is to develop ML-based simulations.
analog performance modeling techniques that can simultane- 2) Macro-Model-Based Circuit Performance Estimation:
ously achieve high accuracy, fast estimation time, low-model Given a circuit system netlist, its performance estimation
construction cost and high scalability. Our modeling techniques is performed as follows.
serve as guidance for intermediate design steps. With circuit a) Circuit Partitioning and Matching: The given cir-
performance estimated with our techniques, designers can adjust cuit system is partitioned into sub-circuits, whose
or tune design parameter to achieve better designs. We choose ML corresponding macro-models are identified from
techniques as they are intrinsically fast for circuit performance the trained models. The model matching is similar
estimation. In order to enable model reuse across different as searching a dictionary. Given the netlist of a
circuits, we propose ML-based macro-models, which can greatly circuit, corresponding model is searched in the
amortize model construction cost. With this sub-circuit level model database This step is similar to and simpler
approach, ML model size and complexity are usually limited so than technology mapping of digital ICs. Also, the
that both model accuracy and scalability are improved. Since number of sub-circuits in an analog or mixed-
our macro-models are ML-based, they are quite different from signal IC is substantially smaller than the logic
conventional macro-models in early works [30]. cells in a digital IC.

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LIN et al.: MMM: MACHINE LEARNING-BASED MACRO-MODELING FOR LINEAR ANALOG ICs AND ADC/DACs 4743

Fig. 3. Two examples of connection structures: a (a) cascade connection and

a (b) feedback connection.

3) Obtaining the circuit/System Transfer Function by

assembling the macro-models.
4) Circuit Performance Estimation through the circuit
system transfer function.
Both variable loading effect and circuit feedback structure are
considered in this methodology. Although multiple ML models
need to be built in these steps, they all share the same training
data and the model training time is much shorter than the data
preparation time. We use an example of two-stage OTA to
Fig. 2. Overall flow of our proposed MMM framework. Step 1: Offline
macro-model training, Step 2: Circuit partitioning and matching, and Step 3:
illustrate these steps.
Circuit system modeling assembling.
A. ML-Based DC Voltage Modeling
b) Assembling Macro-Models for Circuit Performance For an M-input N-output sub-circuit, an ML model FV
Estimation: This step will be introduced with is built to estimate its DC output voltages given the input
details in Sections IV and V for linear circuits and features of 1) DC input voltages; 2) device sizes; and 3) current
ADC/DACs, respectively. source/voltage bias and loads (resistance and capacitance)
from its surrounding circuits, and can be described by

IV. F REQUENCY-D OMAIN M ODELS FOR L INEAR IC S V O = [VO1 , VO2 , . . . , VON ]T

s-domain transfer function is able to describe the behavior = FV (VI1 , VI2 , . . . , VIM ; S, L) = FV (V I ; S, L) (2)
of a LTI system [30] as
where V I and V O are an M-dimensional vector of DC input
Y(s) (s − z1 )(s − z2 ) · · · (s − zm )
H(s) = =K (1) voltages and an N-dimensional vector of DC output voltages,
X(s) (s − p1 )(s − p2 ) · · · (s − pn ) respectively. S is the vector for transistor sizes and L is a vector
where X(s) and Y(s) are the input and output signals, K is a representing loads and current source/voltage bias. One ML
constant factor, and zi , i = 1, . . . , m and pi , i = 1, . . . , n are model is required for each sub-circuit’s DC voltage modeling.
zeros and poles. The small signal model of many analog ICs With constructed ML-based DC voltage models for all sub-
can be treated as LTI systems at certain DC operating points. circuits, the DC operating point for each sub-circuit can be
As such, the s-domain transfer function of (1) can describe obtained based on the type of sub-circuit connection, including
the circuit behaviors. cascade connection, feedback connection, and a mix of these
We apply the following main steps in our frequency-domain two kinds of connections.
MMM for circuit performance estimation. In Fig. 3(a), cascade connections are illustrated where each
1) DC Voltage Modeling: Given DC input voltages for a rectangle indicates the DC voltage model of a sub-circuit and
sub-circuit, an ML model is built to estimate its DC the superscripts indicate the indices of sub-circuits. The DC
output voltage. In order to obtain the DC operating input/output voltage of all sub-circuits and their DC operating
points for all sub-circuits, the models for all sub-circuits points can be obtained by propagating the given primary DC
of a system are connected together. input voltages at the first sub-circuit through all cascade stages
2) Parametric Transfer Function-Based Macro-Modeling: using the ML models of (2). The ML-based DC voltage models
With the DC operating point obtained in the previous in (2) is also applied on ADC/DACs.
step, the transfer function of each sub-circuit is derived Fig. 4 shows an example of two-stage OTA composed by
in this step. The parameters of each transfer function are a one-stage OTA and a CSA, whose DC voltage models are
(1) (2)
obtained through ML models. represented by FV and FV in Fig. 4(b), respectively. The

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4744 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 43, NO. 12, DECEMBER 2024

Algorithm 1 Feedback Circuit DC Voltage Modeling

Inputs:
(q)
DC voltage models {FVF (·), q = 1, 2, . . . , QF } and
(q)
{FVB (·), q = QF + 1, . . . , QF + QB }
(1)
First DC input voltage VI1 of the first model
Stop criteria 
(1)
Range [Vl , Vu ] of possible value of VI2
Searching resolution δ
(1)
Outputs: Second DC input voltage VI2 of the first model
1: Initialize error E∗ ← (Vu − Vl ), initialize best estimated
(1)∗
voltage VI2 ← Vl
(1)
2: Construct
 a new model F(V̂I2) =
(QF +QB ) (QF +1) (QF ) (1) (1) (1)
FVB ◦ · · · ◦ FVB ◦ FVF ◦ · · · ◦ FVF (VI1 , V̂I2 )
∗
3: while E >  do
4: for i = 0, 1, 2, . . . , δ do
(1)
5: V̂I2 ← Vl + δi × (Vu − Vl )
(1) (1)
6: Estimated ṼI2 = F(V̂I2 )
(1) (1)
7: if abs(V̂I2 − ṼI2 ) <  then
8:
(1)
9: returnV̂I2
(1) (1)
10: else if abs(V̂I2 − ṼI2 ) < E∗ then
(1) (1)
11: E∗ ← abs(V̂I2 − ṼI2 )
(1)∗ (1)
12: VI2 ← V̂I2
13: end if
14: end for
(1)∗ (1)∗
15: Vl , Vu ← VI2 − Vu −V δ , VI2 +
l Vu −Vl
δ
Fig. 4. Two-stage OTA, corresponding DC voltage macro-model connection, 16: end while
and system transfer function modeling. (a) Two-stage OTA schematic. (b) DC
voltage macro-model. (c) Transfer function macro-model.
available. The DC voltage modeling accuracy and runtime for
(1) (1) feedback circuits depend on the searching resolution δ and
one-stage OTA has two inputs and VI1 VI2
and one output
(1) (2) (2) stop criteria . Thus, there is some limitation of the tradeoff
VO1 . Similarly, VI1 and VO1 are input and output of the CSA. between runtime and accuracy. With small stop criteria and
(1) (2)
The models FV and FV have separately generated training high resolution, the modeling process has higher accuracy and
data samples and are trained individually. With the two trained takes more running time.
DC voltage macro-models, the system-level DC voltage model Algorithm 1 shows the steps to determine the DC voltage
constructed in the following formulation: of sub-circuits in a feedback circuit shown in Fig. 3(b).
(2) The symbol ◦ in line 1 of Algorithm 1 stands for model
VO1 = FV(2) (VI1
(2) (2)
, S , L(2) )
composition, where
(2) (1)
= FV (VO1 , S(2) , L(2) ) 
(3) (2) (1)

(1) (3)

(2)

(1) (1)

(2) (1) (1) FVF ◦ FVF ◦ FVF (VI ) = FVF FVF FVF (VI ) .
= FV (FV (V I , S(1) , L(1) ), S(2) , L(2) ) (3)
(1) (1) (1) Please note that composition does not have commutative
where V I = [VI1 , VI2 ] is the DC input voltage vector of property, e.g.,
one-stage OTA. S(1) and L(1) are the vector of device sizes
(3) (2) (1) (1) (2) (3)
and the vector of current source/voltage bias and surrounding FVF ◦ FVF ◦ FVF = FVF ◦ FVF ◦ FVF .
circuits’ loads in one-stage OTA, respectively. S(2) and L(2) (1)
have similar definitions in CSA. The algorithm returns the second DC input voltage VI2 of
The feedback connection of models is shown in Fig. 3(b), the first model. With the obtained DC voltage value, the DC
which QF feedforward stages and QB feedback stages are output voltage of the ith sub-circuit is obtained
  
included. DC operating points for circuits with feedback VO(i) = FV(i) ◦ · · · ◦ FV(1) VI1
(1) (1)
, VI2 .
connections are derived in an iterative process. In Fig. 3(b), a
(Q +Q )
guessed value is assigned to the feedback output VO F B =
(1) B. ML-Based Parametric Transfer Function Macro-Models
VI2 initially. Then, the ML-based sub-circuit DC voltage mod-
els (2) are applied through each stage of the loop iteratively The transfer function (1) can be rewritten as
till the voltage values converge. The convergence is observed a0 + a1 s + · · · + am sm
H(s) = (4)
in all circuits used in our work while a theoretic proof is not 1 + b1 s + · · · + bn sn

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LIN et al.: MMM: MACHINE LEARNING-BASED MACRO-MODELING FOR LINEAR ANALOG ICs AND ADC/DACs 4745

Fig. 5. System with feedback connections among sub-circuits. Each block

indicates a sub-circuit.

where ai , i = 0, . . . , m and bj , j = 1, . . . , n are constant

coefficients. The values of m and n are constants determined
by the circuit topology and are typically less than 20. By
running pole/zero analysis in SPICE simulation, their value
can be obtained. The transfer function macro-model for each
sub-circuit is described by transfer function (4). The transfer
function is parametric as its coefficients are estimated using
ML models instead of being constants. Specifically, an ML
model is built for each coefficient ai or bj using input features
1) DC input voltage of the sub-circuit; 2) device sizes;
and 3) current source/voltage bias and loads (resistance and
capacitance) from its surrounding circuits, i.e.,
a0 , a1 , . . . , am , b1 , . . . , bn
= FC (V I ; S, L)
= [FC0 (V I ; S, L), . . . , FCm+n (V I ; S, L)] (5)
Fig. 6. Flash ADC with its sub-circuits and macro-models. (a) Flash ADC
where FC represents a vector of ML models. Each element schematic. (b) Flash ADC macro-models.
in FC indicates an ML model for one coefficient ai or bj in
the transfer function. S denotes the vector for device sizes, D. Circuit Performance Estimation
L is the vector of loads and current source/voltage bias, and Given a circuit transfer function G(s), its performance
V I is the DC input voltage of the sub-circuit. Please note estimation varies depending on different circuits and we
that DC input voltages of sub-circuits are obtained according illustrate this process using OTA as an example. Since s = jω,
to Section IV-A. Labels of training data are obtained from G(s) can be expressed as
pole/zero analysis through circuit simulations.
In Fig. 4, H (1) (s) and H (2) (s) represent the transfer func- G(jω) = |G(jω)|∠G(jω) (8)
tions of the one-stage OTA and the CSA, respectively, which where |G(jω)| and ∠G(ω) are the amplitude and phase
(1) (2)
are parametric upon ML models FC and FC . angle, respectively. Gain, UGF, BW, and PM are commonly
used performance of OTA and can be obtained by sweeping
C. Circuit System Transfer Function frequency ω and
For a circuit composed by Q cascaded sub-circuits
[Fig. 3(a)] with macro-models H (i) (s), i = 1, . . . , Q, the Gain := 20log|G(j · 0)| dB
system transfer function is given by UGF := ω when |G(j · ω)| = 1
G(s) = H (1) (s)H (2) (s) · · · H (Q) (s). (6) BW := ω when 20log|G(j · ω)| − 20log|G(j · 0)| = −3dB
PM := ∠G(jω) + 180◦ when |G(j · ω)| = 1 (9)
For the two-stage OTA in Fig. 4, its circuit system transfer
function is represented by G(s) = H (1) (s)H (2) (s), as shown in Other circuits which can expressed as LTI systems have similar
Fig. 4(c). performance estimation process.
For a circuit with one feedback loop, whose block diagram
is shown in Fig. 5, its transfer function consists of two parts: V. T IME -D OMAIN M ODELS FOR ADC/DAC S
1) Feedforward transfer function
(Q ) A. Time-Domain Macro-Models
HF (s) = HF(1) (s)HF(2) (s) · · · HF F (s)
2) Feedback transfer function ADCs are composed of sub-circuits, including comparators
(Q +1) (Q +2) (Q +Q ) and an encoder, which are shown in Fig. 6. The sub-circuits
HB (s) = HB F (s)HB F (s) · · · HB F B (s)
The transfer function of the overall circuit is given by [31] of most ADCs can be identified in a similar way. We use a
sine wave at 1 MHz as the input signal for ADC/DACs.
Y (QF ) (s) HF (s) Given an input signal sequence where voltage varies at
G(s) = (1)
= . (7)
X (s) 1 + HF (s)HB (s) discrete time steps, the time-domain macro-model estimates
For a circuit with multiple cascaded paths and feedback loops, the output voltage vector V O,t at current time step t based on
the transfer function can be obtained according to [31]. features, including 1) a vector of input voltage V I,t at time t;

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4746 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 43, NO. 12, DECEMBER 2024

2) a vector of input voltage V I,t− at the previous time step t− ;

3) a vector of output voltage V O,t− at the previous time step
t− ; 4) a vector of device size S; and 5) load vector L. This
can be described as
V O,t = FVT (V I,t , V I,t− , V O,t− ; S, L) (10)
where each element of V I,t or V O,t indicates input/output
voltage of one sub-circuit terminal at time step t. This equation
represents an ML model trained by data from circuit simu-
lation. When the model is constructed, for a given sequence Fig. 7. Illustration of DNL and INL calculation.
of input voltages at discrete time steps, the output voltage
sequences can be obtained from the model. Unlike DC voltage TABLE I
modeling in (2), the voltage in the previous time step is also C IRCUIT T ESTCASES
considered in the time-domain macro-model because it affects
subsequent voltages, e.g., both the voltage in the previous time
step and the accumulated electric charge in the current time
step impact a capacitor voltage.
An example of a flash ADC’s macro models is shown
in Fig. 6(b). In the flash ADC, there are n comparators
(1)
which are modeled by an ML model FVT and one priority
(2)
encoder which is modeled by another ML model FVT . The
(1)
n comparators share the same model FVT because they have
identical topology. Data preparation efficiency has been greatly
improved compared to flat ML models for the use of this
shared macro-model. For the ith comparator, its macro-model’s
(1)
input features includes input voltage VIi,t at time step t as
(1) (1)
well as input voltage VIi,t− and output voltage VOi,t− of the
previous time step t− . In addition, the input features of the
(1)
model also include device size Si and surrounding circuits’
(1)
load Li . The macro-model estimates the output voltage V O,t
at time step t. The macro-model of priority encoder has similar
input features while the difference is that the size of its input
(2) (2)
voltage [V I1,t , . . . , V I1,t ] is significantly greater than the size
of a comparator macro-model’s input feature.
B. ADC/DAC Performance Estimation
For an ADC/DAC without feedback, its output waveform where VLSB = (VFSR /2N ). 0 ≤ i ≤ 2N − 1, Vi denotes the
in discrete time can be obtained through propagating the input voltage for ADC’s ith code (or output voltage for DAC’s
input waveform through the sub-circuits using corresponding ith code). Viideal is the ideal voltage for the ith code. VFSR
macro-models described in Section V-A. Next, a fast Fourier is the full scale range voltage. When sweeping VI , only (2)
transform (FFT) is performed on the waveforms at the output is required to estimate the output voltage because the input
node to obtain the spectrum. Then, the SFDR and signal to voltage is in DC steady state. Fig. 7 illustrates the calculation
noise + distortion ratio (SNDR) performance metrics can be of DNL and INL for a two-bit ADC. V1 is the input voltage
obtained by [31] when the output code changes from 00 to 01. V2 and V3 are
AF defined similarly. VLSB is 0.2V when full scale range voltage is
SFDR = 20 × log
AW 0.8V. The difference between V2 and V1 is 0.75VLSB , which
AF is 0.25VLSB less than VLSB and results in DNL = −0.25. V2
SNDR = 20 × log   1 (11) is 1.75VLSB , which is less than V2ideal = 2VLSB and results in
A2N + A2D 2 INL = −0.25.
where AF represents the amplitude of fundamental component
in the spectrum, and AW , AN , and AD denote the amplitude of
the worst-spur signal, and amplitudes of noise and distortion, VI. E XPERIMENTS
respectively. Table I lists the testcases used to evaluate the approach,
For ADCs, by sweeping the input voltage VI in full scale where SCF is a switched capacitor filter and LDO is a LDO. In
range (or all digital code for DAC) [32], performance metrics this table, linear analog ICs are shown in the upper part and a
of differential nonlinearity (DNL) and integral nonlinearity list of ADC/DACs is shown in the lower part. The designs are
(INL) can be obtained based on a commercial 12-nm process technology. All training
DNL = (Vi − Vi−1 )/VLSB − 1INL = (Vi − Viideal )/VLSB (12) data are obtained through SPICE simulations. The experiments
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LIN et al.: MMM: MACHINE LEARNING-BASED MACRO-MODELING FOR LINEAR ANALOG ICs AND ADC/DACs 4747

TABLE II
M ACRO -M ODEL E RROR C OMPARED TO SPICE 5) Flat PEA: Almost the same as Flat RF while the
difference is that a PEA [11] model is used as the ML
engine.
6) Flat ANN: The performance of an entire circuit is
directly estimated by an ANN model like in [6]. The
number of hidden layers and the number of neurons in
each layer are set as 5 and 256 according to the paper’s
settings, respectively.
7) NN-symb: The previous work [13], which is symbolic
analysis using neural network-based transistor models.
8) CCI-NN: The recent previous work [7] aimed to training
sample reduction. Similar experiment setup is used as
are conducted on a Linux machine with a Xeon E5-2680 V2 provided in [7].
processor, 2.8-GHz frequency, and 256-G memory. 9) MOR: An MOR technique [15], [38], which is only
tested on linear analog ICs.
10) MTL: A MTL technique [14]. For linear circuits, transfer
A. Results of ML-Based Macro-Model Accuracy function coefficients of each sub-circuit are trained using
MTL, where each coefficient is a task. For ADC/DACs,
We study several options of ML engines for the macro-
circuit performance metrics of a circuit system are
models, including RF [33], XGBoost [34], and PEA [11],
trained using MTL, where each performance metric is
which is an extension of GNN from classification to regres-
a task. For MTL, the corresponding networks structure
sion. For PEA, the input data include adjacency matrix,
is shown in Fig. 11, where the first several layers in
node feature matrix and edge feature matrix. The adjacency
the neural networks are PEA layers [11] and are shared
matrix encodes the connection of transistors and other circuit
among multiple tasks. Corresponding parameters of the
components in the netlist. Node feature matrix includes circuit
PEA layers are also shared among multiple tasks. For
components’ parameters, such as transistor sizes and capaci-
each task, multiple fully connected layers are connected
tance values. Edge feature matrix includes connection of each
to the shared PEA layers. These layers are task specific
net, such as the gate type of each transistor in the net. Our
and their parameters are not shared among different
ML models are constructed using ML frameworks, including
tasks.
scikit-learn [35], TensorFlow [36], and PyTorch [37]. Each
Fig. 8 depicts the average performance estimation errors
macro-model is trained and tested for the same sub-circuit
compared with SPICE. The error of one test circuit is the aver-
with 1000 data samples, where 80% are used for training and
age percentage error among all its performance metrics, e.g.,
the other 20% are used for testing. Please note that no test
gain, UGF, BW and PM for OTAs, VGAs, and SCFs. PSRR
data is seen in training. In our proposed method, the models
is the performance metric for LDOs while for ADC/DACs,
are constructed for sub-circuits which are normally small and
performance metrics include SFDR, SNDR, DNL, and INL.
have small dimension size. Also, each model’s outputs are
We use a sine wave at 1 MHz as the input signal for
voltages and transfer function coefficients, which have less
ADC/DACs and apply an FFT at the output signal to obtain
complexity than directly estimating performance metrics. This
spectrum and SFDR as well as SNDR [39], [40], [41]. We
is one benefit for macro-modeling comparing to modeling
can observe that MMM RF and MMM XGBoost achieve
for the entire large circuit and further illustrated in Fig. 9.
the smallest errors, which are less than 1% on average and
Table II shows the comparison of macro-model errors based
significantly smaller than the 9% and 6% average errors from
on different ML engines. The result of each sub-circuit is
NN-symbolic and CCI-NN, respectively. Figs. 9 and 10 also
averaged on all its macro-models. One can see that RF and
show the estimation errors for some specific performance met-
XGBoost are more accurate than PEA while RF is the most
rics for UGF of linear analog ICs and SFDR of ADC/DACs,
accurate among them.
respectively, where similar trends can be observed.
These results partially confirm the observation [7] that the
accuracy of flat ANN performance models tends to degrade for
B. Results of Circuit Performance Estimation Accuracy large circuits or wide performance range. As the ML models of
We compare the following methods. MMM are trained for sub-circuits that have lower complexity
1) MMM RF: This is our proposed approach where macro- than entire circuits, MMM is able to attain significantly higher
models are based on RF. Tree depth and forest size are accuracy.
set as 10 and 20, respectively.
2) MMM XGBoost: Almost the same as MMM RF while
the only difference is that its ML engine is XGBoost. C. Model Construction and Circuit Performance Estimation
3) MMM PEA: Almost the same as MMM RF, but the ML Runtime
engine is regression model of PEA [11]. Circuit performance estimation runtime comparisons for
4) Flat RF: The performance of an entire circuit is directly different methods are provided in Table III. The runtime of
estimated by a RF model. Tree depth and forest size are MMM XGBoost is almost the same as MMM RF and not
set as 10 and 400, respectively. included here. Among the 8 methods being compared, MMM
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4748 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 43, NO. 12, DECEMBER 2024

Fig. 8. Circuit performance estimation error compared with SPICE.

Fig. 9. UGF estimation errors.

Fig. 10. SFDR estimation errors.

RF is the second fastest for performance estimation runtime and runtime. It shows that runtime is about 40× when the
and 2.9× faster than the recent approach CCI-NN [7]. It is also forest size increases from 20 in MMM RF to 400 in flat RF.
42× faster than MOR for linear circuits. Flat ANN is faster Model construction time consists of the time for obtaining
than MMM RF, however, its performance estimation errors are training data as well as model training. The former dominates
significantly larger. MTL is 61× slower than MMM RF as the latter one as many circuit simulations are required to
it has more complicated model structure than RF. Flat RF is prepare training data. Since our macro-models are reused
slower than MMM RF because it requires more decision trees in different circuits, their data preparation time and model
to build model an entire circuit system. The contour plot in training time reported in Tables IV and V are amortized,
Fig. 12 illustrates the relation between tree depth, forest size e.g., the time is scaled by 1/k if the model is reused for k

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LIN et al.: MMM: MACHINE LEARNING-BASED MACRO-MODELING FOR LINEAR ANALOG ICs AND ADC/DACs 4749

TABLE IV
C OMPARISONS OF DATA P REPARATION T IME

Fig. 11. Model structure of neural networks with MTL.

TABLE III
C OMPARISONS OF P ERFORMANCE E STIMATION T IME

TABLE V
C OMPARISONS OF M ODELING T RAINING T IME

different hierarchical circuits, which results in extra runtime.

The model construction time of MMM XGBoost is similar
to MMM RF and not included due to space limit. For model
training time, MTL is much slower than MMM RF because
MTL uses more complicated model structure and ADC/DACs
do not benefit from model reuse. The models of Flat ANN
Fig. 12. Tradeoff between performance estimation runtime, tree depth, and
forest size for two-stage OTA. are built according to the settings in [6] and trained using the
Adam optimization algorithm [42]. MTL is faster than Flat
ANN because the first several layers in the neural networks of
circuits in all of our testcases. The advantage of our proposed MTL are shared among multiple tasks and they only need to
MMM RF on model construction time is huge which shows be trained once. The models in MTL are trained with multiple
orders of magnitude speedup comparing with other methods. gradient descent algorithm.
In particular, the data preparation time of our MMM RF
is 357× less than CCI-NN [7], which has a similar goal
as ours. MMM RF can reduce the data preparation time D. Tradeoff Between Runtime and Estimation Error
from about 40 days to 9.6 h, for the largest case of 8-bit The tradeoff between training data preparation time and
flash ADC. This significant speedup in runtime is a result of circuit performance estimation error among linear analog ICs
model construction and training strategy in our method. Each is compared in Fig. 13. Comparing to other methods, most test
macro-model is built and trained independently for each sub- cases from our MMM RF are closer to the lower-left corner,
circuit in our method, which naturally facilitates model reuse. corresponding to lower-data preparation time and performance
However, in the work [7], the entire neural network must be estimation error. Similarly, the tradeoff between ML model
trained for the whole circuit. Thus, unlike our approach the training time and performance estimation error is shown in
neural network for each sub-circuit in [7] cannot be reused in Fig. 14, which demonstrates the advantage of our MMM RF

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4750 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 43, NO. 12, DECEMBER 2024

Fig. 16. Tradeoff between training data set size and performance estimation
error for three-stage VGA.

Fig. 13. Tradeoff between training data preparation time and circuit Similarly, multiple hyperparameter settings are setup for dif-
performance estimation error for linear analog ICs. ferent neural networks in order to obtain multiple CCI-NN [7]
results. Our MMM RF shows an evident dominant against
the other two methods in terms of the tradeoff between
performance estimation runtime and estimation errors.

E. Results on Model Training Efficiency

The tradeoff between performance estimation error and
the number of training samples for our MMM RF and
CCI-NN [7] is shown in Fig. 16. It can be observed that MM
RF consistently achieves smaller estimation errors than CCI-
NN across different training data sizes.

VII. C ONCLUSION
Although machine learning-based models has advanced
the state-of-the-art for fast analog performance estimation,
existing approaches are mostly flat models that suffer from
huge model construction cost and low reusability. This work
Fig. 14. Tradeoff between ML model training time and circuit performance
estimation error for linear analog ICs. introduces machine learning techniques in macro-model level
to address the problems for linear analog ICs and ADC/DACs.
Experimental results on circuits with up to 20K devices show
that our approach can reduce model construction cost by three
orders of magnitude compared to recent ML techniques. At
the same time, it achieves significantly smaller errors and is
three orders of magnitude faster than circuit simulation.
In future research, we will extend the macro-modeling
techniques for ADC/DACs with feedback and nonlinear analog
ICs, and study how to automatically partition a circuit system
into sub-circuits for macro-models.

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4752 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 43, NO. 12, DECEMBER 2024

Sachin S. Sapatnekar (Fellow, IEEE) received Jiang Hu (Fellow, IEEE) received the B.S. degree
the B.Tech. degree from the Indian Institute of in optical engineering from Zhejiang University,
Technology, Bombay, Mumbai, India, in 1987, the Zhejiang, China, in 1990, the M.S. degree in physics
M.S. degree from Syracuse University, Syracuse, in 1997 and the Ph.D. degree in electrical engineer-
NY, USA, in 1989, and the Ph.D. degree from ing from the University of Minnesota in 2001.
the University of Illinois, Champaign, IL, USA, in He is a Professor with the Department of
1992. Electrical and Computer Engineering, Texas A&M
He teaches with the University of Minnesota, University, College Station, TX, USA. His research
Minneapolis, MN, USA, where he holds a interests include EDA, computer architecture, and
Distinguished McKnight University Professorship hardware security.
and the Henle Chair. Dr. Hu received the Best Paper Awards at DAC
Dr. Sapatnekar has received 12 Best Paper Awards (including two ICCAD 2001, ICCAD 2011, MICRO 2021, and ASPDAC 2023. He served as the
10-year Retrospective Most Influential Paper Awards), the SRC Technical General Chair for the ACM International Symposium on Physical Design
Excellence Award, and the SIA University Research Award. He is a Fellow 2012 and the Technical Program Co-Chair for the ACM/IEEE Workshop on
of the ACM. Machine Learning for CAD 2023.

Ramesh Harjani (Fellow, IEEE) received the B.S.

degree in electrical engineering from the Birla
Institute of Technology and Science—Pilani, Pilani,
India, in 1982, the M.S. degree in electrical engineer-
ing from the Indian Institute of Technology, Delhi,
New Delhi, India, in 1984, and the Ph.D. degree
in electrical engineering from Carnegie Mellon
University, Pittsburgh, PA, USA, in 1989.
Prior to joining the University of Minnesota,
Minneapolis, MN, USA, he was with Mentor
Graphics Corp., San Jose, CA, USA. He is the
Edgar F. Johnson Professor with the Department of Electrical and Computer
Engineering, University of Minnesota. He co-founded Bermai Inc., Palo Alto,
CA, USA, a startup company developing CMOS chips for wireless multimedia
applications in 2001. He has been a Visiting Professor with Lucent Bell
Labs, Allentown, PA, USA, and the Army Research Labs, Adelphi, MD,
USA. His research interests include analog/RF circuits for wired and wireless
communications.
Dr. Harjani received the L.K. Maheshwari Foundation Distinguished
Alumnus Award from his Alma Mater, the Birla Institute of Technology and
Science, Pilani, in April 2020. He received the Best Paper Awards at the 2018
IEEE European Solid-State Devices and Circuits Conference in 2018, the 1998
GOMACTech Conference, the 1989 International Conference on Computer-
Aided Design, and the 1987 IEEE/ACM Design Automation Conference. He
received the National Science Foundation Research Initiation Award in 1991.
His research group was the winner of the SRC Design Challenge in 2000 and
2003. He was the Technical Program Chair for the IEEE Custom Integrated
Circuits Conference 2012 and 2013, the Chair of the IEEE Circuits and
Systems Society Technical Committee on Analog Signal Processing 1999 and
2000, and a Distinguished Lecturer of the IEEE Circuits and Systems Society
2001 and 2002. He was an Associate Editor for IEEE T RANSACTIONS ON
C IRCUITS AND S YSTEMS PART II from 1995 to 1997, the Guest Editor for the
I NTERNATIONAL J OURNAL OF H IGH -S PEED E LECTRONICS AND S YSTEMS
and for Analog Integrated Circuits and Signal Processing in 2004 and for
the IEEE J OURNAL OF S OLID -S TATE C IRCUITS from 2009 to 2011. He
was a Senior Editor for the IEEE J OURNAL ON E MERGING AND S ELECTED
T OPICS IN C IRCUITS AND S YSTEMS from 2011 to 2013. He has given several
plenary and keynote lectures at IEEE conferences.

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