SIDDAGANGA INSTITUTE OF TECHNOLOGY, TUMAKURU-572103

(An Autonomous Institute under Visvesvaraya Technological University, Belagavi)

Technical Seminar Report on

“Advancements in Image Sensor Architectures Using

Stacked Device Technologies”

submitted in partial fulfillment of the requirement for the award of the

degree of
BACHELOR OF ENGINEERING
in
ELECTRONICS & COMMUNICATION ENGINEERING
Submitted by

PRAMOD H N (1SI21EC117)

under the guidance of

Dr. K V Suresh
Professor and Head
Department of E&CE
SIT, Tumakuru-03

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

2024-25
 SIDDAGANGA INSTITUTE OF TECHNOLOGY, TUMAKURU-572103
(An Autonomous Institute under Visvesvaraya Technological University, Belagavi)
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

CERTIFICATE

This is to certify that, Pramod H N (1SI21EC117) has successfully completed Techni-

cal seminar titled “ Advancements in Image Sensor Architectures Using Stacked Device
Technologies” in the partial fulfillment for the award of degree of Bachelor of Engineering
in Electronics & Communication Engineering of Siddaganga Institute of Technology, an
autonomous institute under Visvesvaraya Technological University, Belagavi during the
academic year 2024-25.

Names of the Evaluators Signature with date

1.
2.

Head of the Department

Dept. of E&CE
SIT,Tumakuru-03
 Course Outcomes

CO 1 : Identify the recent topic in the area of Embedded systems, Microelectronics,

Communication Engineering or Signal processing.
CO 2 : Select a peer reviewed publication from a reputed research literature.
CO 3 : Comprehend and prepare a technical report on the selected topic in their area of
interest.
CO 4 : Present the technical seminar individually, demonstrating effective communication
and ethics to continuously involve in the lifelong learning process.

Course Articulation Matrix

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PSO1 PSO2
CO-1 3 2 2
CO-2 3 2 3 2 1 1 1 2
CO-3 3 3 3 3 1 2 2 2 2
CO-4 3 2 2 2 2 1 2 2 2 2
Average 3 2 3 3 2 2 1 2 2 2 2

Attainment level: - 1: Slight (low) 2: Moderate (medium) 3: Substantial (high)

POs: PO1: Engineering Knowledge, PO2: Problem analysis, PO3: Design/Development
of solutions, PO4: Conduct investigations of complex problems, PO5: Engineering tool
usage, PO6: Engineer and The World, PO7: Ethics, PO8: Individual and Collabora-
tive team work, PO9: Communication, PO10: Project management and Finance, PO11:
Lifelong learning
Abstract
The growing demand for high-performance imaging solutions across fields such as auto-
motive safety, mobile devices, and industrial inspection has driven rapid advancements in
image sensor technologies. Traditional planar image sensor designs are reaching funda-
mental physical and performance limits, necessitating innovative approaches to meet the
increasing expectations for resolution, speed, dynamic range, and power efficiency. This
seminar explores the critical role of stacked device technologies in the evolution of image
sensor architectures, highlighting their importance in enabling next-generation imaging
applications.

The primary objective of this work is to provide a comprehensive overview of how three-
dimensional (3D) stacking techniques—such as pixel-level and circuit-level stacking—have
revolutionized image sensor performance. Key technologies discussed include through-
silicon vias (TSVs), hybrid bonding, and wafer-to-wafer stacking, as well as the integra-
tion of advanced analog and digital circuits. By examining recent research trends and
practical implementations, this study demonstrates how stacking enhances sensor capa-
bilities, optimizes form factors, and overcomes traditional trade-offs between resolution,
sensitivity, and speed.

The implementation aspect focuses on the design challenges and opportunities presented
by stacked architectures, including thermal management, interconnect strategies, and sig-
nal integrity. Practical case studies are highlighted to showcase how stacking enables
innovations such as high dynamic range imaging, low-light performance, and real-time
image processing. This study ultimately emphasizes the transformative impact of stacked
device technologies on the future of image sensors, positioning them as critical enablers
for intelligent imaging systems in an increasingly connected world.

i
Contents
Abstract i

1 Introduction 1
1.1 Literature Survey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Analysis Of Methodology 5
2.1 Front-Illuminated and Back-Illuminated Structures . . . . . . . . . . . . . 5
2.2 Stacked Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Advanced Sensor Architectures . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Movie Recording With More Than Megapixels . . . . . . . . . . . . . . . 6
2.4.1 Double-Column ADC Architecture . . . . . . . . . . . . . . . . . . 7
2.4.2 Three-Layer Stacked CMOS Image Sensor With DRAM . . . . . . 8
2.4.3 Chip-on-Wafer (CoW) Technology for Large Optical Format . . . . 9
2.5 Pixel-Parallel Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.1 Cu–Cu Connections in Stacked Image Sensors . . . . . . . . . . . . 10
2.5.2 Stacked Pixel Circuit Extensions . . . . . . . . . . . . . . . . . . . 11
2.5.3 Pixel-Parallel ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.4 Pixel-Parallel Photon Counter . . . . . . . . . . . . . . . . . . . . . 11
2.6 Extension of Sensing Capabilities . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 Spatial Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7.1 Temporal Contrast Sensing . . . . . . . . . . . . . . . . . . . . . . 13
2.7.2 Invisible-Light Imaging . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8 Intelligent Vision Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Analysis Of Results 24
3.1 Sensor Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Application Demonstrations . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Comparison With Previous Designs . . . . . . . . . . . . . . . . . . . . . . 25
 3.4 Trend Analysis and Scalability . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Energy Efficiency and Practical Relevance . . . . . . . . . . . . . . . . . . 26

4 Conclusion 27

Bibliography 27
Chapter 1
Introduction
Image sensors play a crucial role in modern digital imaging applications, ranging from con-
sumer electronics to industrial and automotive sectors. Since the development of charge-
coupled devices (CCDs) in 1969, solid-state image sensors have undergone significant
advancements, leading to their widespread adoption in digital cameras, video recording
devices, and machine vision systems. Over the past two decades, CMOS (Complemen-
tary Metal-Oxide-Semiconductor) image sensors have replaced CCDs as the dominant
technology due to their lower power consumption, faster readout speeds, and improved
integration capabilities.
The increasing demand for high-performance imaging in smartphones, security cameras,
autonomous vehicles, and industrial automation has driven continuous innovation in
CMOS image sensor technology. A major breakthrough in this field was the introduction
of back-illuminated (BI) image sensors, which addressed the limitations of conventional
front-illuminated (FI) structures by improving light sensitivity and optimizing pixel ar-
rangement. The adoption of BI structures has enabled further advancements, particularly
in the development of stacked CMOS image sensors, which enhance imaging performance
by integrating logic circuits and signal processing elements directly onto separate layers.
Stacked image sensor architectures leverage wafer-bonding and advanced wafer-thinning
techniques to achieve compact, high-performance designs. This approach allows for the in-
tegration of highly parallel column-parallel analog-to-digital converters (ADCs), enabling
high-resolution and high-frame-rate imaging. Furthermore, pixel-pitch Cu–Cu connec-
tions facilitate pixel-parallel digitization, further improving sensor efficiency. The evolu-
tion of stacked CMOS sensors has also led to the integration of edge computing function-
alities, allowing real-time image processing and AI-based decision-making directly on the
sensor chip.
This report provides a comprehensive review of recent advancements in stacked CMOS
image sensors, focusing on their architectural evolution, improved sensing capabilities,
and the integration of AI-driven edge computing. The subsequent sections explore vari-

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25
ous sensor configurations, advanced pixel circuit implementations, extended sensing func-
tionalities such as spatial depth and contrast sensing, and emerging AI-integrated vision
sensors. Through these advancements, stacked CMOS image sensors continue to redefine
the future of digital imaging, offering superior performance, enhanced functionality, and
broader application potential.

1.1 Literature Survey

CMOS image sensors have undergone significant advancements over the past few decades,
evolving from basic active pixel sensors to highly sophisticated back-illuminated and
stacked architectures. These developments have improved sensitivity, resolution, and
power efficiency, making CMOS sensors a preferred choice for various imaging applica-
tions.

Advancements in Back-Illuminated CMOS Image Sensors Back-illuminated (BSI)

CMOS sensors have been a major bBack-illuminated (BSI) CMOS sensors have been a
major breakthrough, improving photon collection efficiency and reducing noise. Early
works such as Pain [1] and Iwabuchi et al. [2] demonstrated the feasibility of back-
illuminated CMOS sensors in mixed SOI/bulk CMOS technologies. Pain [1] discussed
design challenges in achieving sufficient sensitivity and dynamic range in early BSI pro-
totypes, while Iwabuchi et al. [2] implemented SOI substrates to reduce parasitic ca-
pacitance and enable faster charge transfer. Later, Wuu et al. [3] and Rhodes et al.
[4] showcased mass-production techniques for manufacturable BSI CMOS image sensors.
Wuu et al. [3] presented a novel wafer thinning and bonding technique to achieve reliable
backside illumination, and Rhodes et al. [4] reported on scalable BSI process integration
compatible with high-volume manufacturing lines. Further refinements, such as those by
Wakabayashi et al. [5] and Sukegawa et al. [6], introduced higher pixel densities and
improved color sensitivity. Wakabayashi et al. [5] optimized micro-lens alignment and
introduced new materials for light guiding structures, while Sukegawa et al. [6] improved
the quantum efficiency of each color channel using deep trench isolation and new CFA
technologies. More recently, Krauss [13] explored the integration of Raspberry Pi and
Arduino to enhance real-time imaging applications. Krauss [13] demonstrated a low-cost
edge computing platform for image acquisition and processing using BSI sensors, enabling
applications in robotics and IoT.

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25
Stacked CMOS Image Sensors Stacked CMOS image sensors have significantly im-
proved sensor architecture by enabling independent optimization of pixel and logic layers.
Studies by Suzuki et al. [10] and Haruta et al. [11] demonstrated the benefits of in-
tegrating DRAM within a stacked sensor architecture. Suzuki et al. [10] implemented
high-speed memory directly beneath the pixel array, allowing for ultra-fast burst shooting
and reduced motion blur, while Haruta et al. [11] focused on vertical interconnect tech-
niques that reduce form factor and enable complex logic integration. Later advancements,
such as those by Oike et al. [12], focused on optimizing global shutter capabilities and
minimizing noise. Oike et al. [12] developed a dual-gain pixel readout scheme and im-
plemented novel noise-canceling circuits, achieving high-fidelity capture even in dynamic
scenes.

High-Speed and High-Dynamic-Range CMOS Image Sensors For applications

requiring high frame rates and extended dynamic ranges, various innovations have been
introduced. Yoshihara et al. [9] proposed seamless mode-changing architectures, while
Nitta et al. [8] explored column-parallel ADC architectures to enhance high-speed readout
and low-noise performance. Yoshihara et al. [9] developed a hybrid mode image sensor
capable of switching between linear and logarithmic response modes, facilitating both
HDR and low-light imaging. Nitta et al. [8] integrated high-resolution ADCs directly on
columns, improving frame readout speeds and lowering temporal noise, which is critical
for scientific and industrial imaging.

Advancements in Image Sensor Architectures Using Stacked Device Technolo-

gies Further work by Wakabayashi et al. [5] and Suzuki et al. [10] introduced CMOS
sensors with extremely high-speed readout, supporting machine vision applications. Wak-
abayashi et al. [5] refined the readout circuitry to support over 1000 fps while minimizing
read noise. Suzuki et al. [10] enhanced memory bandwidth and timing control to enable
consistent high-speed frame delivery, essential for applications like automated inspection
and motion analysis.

1.2 Summary
This literature survey explores the advancements, design principles, and applications of
CMOS image sensors (CIS), highlighting their advantages over CCD sensors, such as
low power consumption, high-speed operation, and system-on-chip (SoC) integration. It

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25
covers CMOS sensor architecture, including active pixel sensor (APS) designs like 3T, 4T,
and 5T structures, and their impact on noise reduction, sensitivity, and dynamic range.
Technological advancements such as backside illumination (BSI), stacked sensors, and
global shutter technology are discussed for their role in enhancing low-light performance
and reducing motion artifacts. The survey also examines CIS applications in smart-
phones, automotive vision, medical imaging, and industrial automation, emphasizing
high-speed and AI-driven enhancements. Finally, emerging trends like neuromorphic vi-
sion, quantum-dot-enhanced imaging, and 3D imaging technologies are explored, provid-
ing insights into the evolution, challenges, and future directions of CMOS image sensors.

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Chapter 2
Analysis Of Methodology
Image sensors are currently used for a wide variety of applications. Since the invention
of charge-coupled devices (CCDs) in 1969, solid-state image sensors have expanded into
various consumer markets, including compact video cameras and digital still cameras.
CMOS image sensors, which became the mainstream solid-state image sensors in the
mid-2000s, have continued evolving based on CCD technologies.
Beyond consumer electronics, the demand for image sensors is rapidly expanding into
security network cameras, machine vision for factory automation, and automotive cameras
for driver-assistance and autonomous systems. A significant breakthrough in CMOS image
sensor technology was the successful development of back-illuminated (BI) image sensors,
which have enabled the development of stacked structures for image sensors, as shown in
Fig. 2.1.

2.1 Front-Illuminated and Back-Illuminated Struc-

tures
In traditional front-illuminated (FI) structures, reducing pixel size was challenging be-
cause incident light had to be collected by a photodiode through a narrow gap surrounded
by metal wires. The introduction of BI structures significantly improved sensitivity and
provided flexibility in metal wiring, making it a preferred approach for image sensors.
These advancements were made possible due to wafer-bonding and highly uniform wafer-
thinning technologies.

2.2 Stacked Device Architecture

Image sensors have gradually evolved toward stacked structures, where logic circuits are
integrated directly onto substrate wafers. This stacking process allows for highly parallel
analog-to-digital converters (ADCs) and greater integration of signal processing elements,
independent of the sensor process customized for pixel photodiodes. This development
has significantly transformed image sensor architectures, enabling high-pixel-resolution

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25
and high-frame-rate imaging through column-parallel ADCs.

2.3 Advanced Sensor Architectures

Recent advances in sensor architectures focus on enhancing pixel performance through
pixel-pitch Cu–Cu connections, which facilitate pixel-parallel digitization. These connec-
tions are crucial for achieving better pixel resolutions. Additionally, new sensor technolo-
gies extend sensing capabilities to include spatial depth, temporal contrast sensing, and
invisible light imaging.
A major innovation in this field is the integration of vision sensors with edge artificial
intelligence (AI) accelerators, allowing real-time processing at the sensor layer. These
developments indicate a continued shift toward intelligent image sensors with greater
processing power.

Figure 2.1: Evolution of stacked CMOS image sensor architectures [1]

2.4 Movie Recording With More Than Megapixels

Movie recording requires a frame rate of at least 30 or 60 frames per second (fps), even
as the number of pixels is increasing from the 2M pixel high-definition (HD) to 8M pixel
4K format. Furthermore, higher frame-rate operations, such as 120, 240, or even 1000
fps, allow for slow-motion replays. The development of high-performance CMOS image
sensors has significantly improved frame rates and pixel resolution.
Since the introduction of the column-parallel ADC architectures in 1997 [8], frame rates
have been improved by increasing the number of parallel ADCs and enhancing ADC
operations [9, 10, 13]. The stacked structure contributes significantly to frame rate im-

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25
provements by allowing optimal process technologies to be applied to both sensor pixels
and peripheral logic circuits [7, 11, 12].
The fabrication of image sensors requires multiple ion-implantation processes to form
photodiodes and transistors with minimal junction leakage. However, the logic circuit
fabrication process demands low-resistance and high-speed transistors. While three or
four wiring layers are typically sufficient for pixels, logic circuits require approximately
ten layers. Stacking technology helps mitigate these conflicting requirements by separating
sensor pixels and logic circuits across different layers.

2.4.1 Double-Column ADC Architecture

Most CMOS image sensors comprise a pixel array, thousands of ADCs organized in a
column-parallel structure, and logic circuitry. Through-silicon vias (TSVs), as shown
in Fig.2.2, connect the pixel columns to ADCs in a highly parallel manner. The first
stacked CMOS image sensor, presented in 2013, split the analog and digital parts of the
column ADCs into top and bottom chips, respectively. In 2015, the double-column ADC
architecture was introduced, where the column ADCs were fully moved to the bottom
chip. This achieved a frame rate of 120 fps with 16M pixels.

Figure 2.2: Implementations of stacked CMOS image sensors: (a) Connections by TSVs
between photodiodes and logic circuits, (b) First stacked CMOS image sensor, (c) Double-
column ADC architecture [1]

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.3: Implementations of stacked CMOS image sensors: (a) TSV connections be-
tween photodiodes and logic circuits, (b) first stacked CMOS image sensor, (c) double-
column ADC architecture [1]

The sensor chip was fabricated using a 90-nm custom process for photodiodes and NMOS
logic, while the logic chip used a 65-nm standard CMOS process. As the ADCs were
independent of the sensor chip, they could be highly integrated. Redundant parallel
ADCs also improved noise characteristics by averaging multiple analog-to-digital (AD)
conversions, as illustrated in Fig.2.3 .

2.4.2 Three-Layer Stacked CMOS Image Sensor With DRAM

Increasing pixel count and parallel ADCs results in a higher data output. In 2017, a
three-layer stacked CMOS image sensor was developed to record slow-motion videos at
960 fps, as depicted in Fig. 2.4. TSVs connected the layers, and data from parallel ADCs
were buffered in the second-layer DRAM. This sensor enabled full-HD resolution at 960
fps by buffering digital data through a 102-Gbit/s bus.

When capturing a movie at 30 fps, the readout speed changes to 960 fps upon detecting
rapid motion or user triggers. Up to 63 full-HD frames can be stored in DRAM and
outputted during subsequent movie capture.

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.4: Three-layer stacked CMOS image sensor with DRAM for high-frame-rate
video capture [1]

2.4.3 Chip-on-Wafer (CoW) Technology for Large Optical For-

mat

Stacked CMOS image sensors are generally fabricated using wafer-on-wafer (WoW) bond-
ing. However, WoW is suboptimal for large optical formats, as sensor and logic chip sizes
must match. The alternative CoW bonding process, illustrated in Fig. 2.5, optimizes
area efficiency by allowing logic chip sizes to differ from the sensor.
A CoW-bonded stacked CMOS image sensor was introduced in 2016 to achieve a global-
shutter image sensor for broadcast cameras with a super-35-mm optical format. Two
diced 65-nm logic chips with parallel ADCs and microbumps were stacked on a large
custom sensor chip. Microbumps with a 40 µm pitch created around 38,000 connections.
This sensor enabled 480 fps imaging with 8M pixels.
Fig. 2.7 presents performance trends in large optical-format image sensors, where a full-35-
mm format sensor with 50M pixels reached 250 fps by 2021. The WoW process achieves
high performance by increasing parallel ADCs and SRAM buffers, while CoW balances
cost and performance. Recent advancements include a 3.6-inch, 127M-pixel image sen-
sor with four stacked logic chips, aiming for higher productivity through improved chip
placement throughput.
Stacked CMOS image sensor technology has revolutionized high-speed imaging by en-
abling higher frame rates, reduced noise, and better integration of processing units.

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.5: Area efficiencies of WoW and CoW bonding processes for a large optical-
format image sensor [1]

Double-column ADC architectures, three-layer stacking with DRAM, and CoW bond-
ing have significantly contributed to advancements in digital imaging, facilitating super
slow-motion recording and large optical-format imaging. Future developments focus on
improving chip stacking efficiency and further enhancing image sensor performance.

2.5 Pixel-Parallel Architectures

In the previous section, sensor architectures using stacked devices were shown to mainly
improve the frame rates based on column-parallel ADC architectures. This section presents
advances based on the pixel-parallel architecture using fine-pitch Cu–Cu connections.

2.5.1 Cu–Cu Connections in Stacked Image Sensors

The connections between the sensor and the logic layers have been changed from TSVs to
hybrid-bonded Cu–Cu connections, as shown in Fig. 2.8(a). In the TSV configuration, the
signal lines are delivered to the logic layer at the periphery of the pixel array. In contrast,
Cu–Cu connections can be integrated directly under the pixels, allowing an increase in
the number of linkages. The recent trends regarding Cu–Cu connection pitches are shown
in Fig.2.8(b).

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.6: Stacked CMOS image sensor using CoW bonding process for large optical
format [1]

2.5.2 Stacked Pixel Circuit Extensions

Many techniques have been proposed to enhance pixel performance, such as increasing full
well capacity (FWC) and realizing additional functions like the global shutter. Figure 2.9
shows the pixel configurations for single and dual conversion gains.
A stacked pixel circuit extension with dual conversion gain was proposed, achieving a
dynamic range of 83.8 dB with a low noise of 0.8 e− rms.

2.5.3 Pixel-Parallel ADC

Since the proposal of pixel-parallel digitization in 2001, stacked image sensors with pixel-
parallel Cu–Cu connections have been presented. A 4.1M-pixel stacked image sensor with
array-parallel ADC architecture was introduced in 2017, followed by a stacked image
sensor with 1.46M pixel-parallel ADCs in 2018. The pixel-parallel ADC architecture has
been realized with Mpixel resolution.

2.5.4 Pixel-Parallel Photon Counter

Photon-count imaging, also called quanta imaging, has been proposed as a promising
technology for noiseless readouts and high dynamic range (HDR). A photon-counting
image sensor using single-photon avalanche diodes (SPADs) has been developed.
A SPAD photon-counting image sensor with a dynamic range of 124 dB was reported in

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.7: Performance trends in large optical-format image sensors [1]

2021. The BI SPAD pixel array is stacked on a bottom chip with readout circuitry via
pixel-parallel Cu–Cu connections.

2.6 Extension of Sensing Capabilities

The latest developments in stacked SPAD sensors have demonstrated pixel sizes of 0.8 µm,
enabling enhanced performance with small pixel configurations. Stacked device technolo-
gies have significantly enhanced sensor architectures, not only improving image quality
but also expanding sensing functionalities. These advancements include spatial depth
sensing, temporal contrast sensing, and invisible-light imaging, in addition to previously
introduced dynamic range and global-shutter functions.

2.7 Spatial Depth

The use of stacked device structures with Cu–Cu hybrid bonding has made substantial
progress in Single-Photon Avalanche Diode (SPAD) technology, reducing the SPAD pixel
pitch to less than 10 µm. A Back-Illuminated (BI) SPAD pixel array with full trench
isolation (FTI) and Cu–Cu bonding has been developed to increase photon detection
efficiency (PDE) and reduce optical crosstalk for small pixel pitches.
As illustrated in Figure 2.17, the BI-stacked SPAD structure places all pixel transistors on
the bottom chip, leaving the SPAD pixel array fully exposed to incident light. This con-
figuration suppresses crosstalk and enhances near-infrared (NIR) spectral measurement

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Figure 2.8: (a) Cu–Cu hybrid bonding structure in stacked image sensors. (b) Trends in
Cu–Cu connection pitches [1]

sensitivity. The 10 µm-pitch SPAD pixel, featuring a 7 µm-thick silicon layer, achieves a
PDE above 31.4% at 850 nm and 14.2% at 940 nm, with a dark count rate (DCR) below
2 cps/µm2 at 60◦ C.
A 189×600 SPAD direct time-of-flight (ToF) sensor for automotive LiDAR applications
was reported in 2021. The sensor utilizes a BI-stacked SPAD array, where pixel front-end
circuits are implemented on the bottom chip, achieving a distance accuracy of 30 cm over
a range of up to 200 m under 117k lux sunlight conditions.

2.7.1 Temporal Contrast Sensing

Event-based vision sensors (EVSs) detect individual-pixel temporal contrast changes ex-
ceeding a preset threshold, enabling frame-free, high-speed machine vision. The BI-
stacked EVS structure significantly reduces pixel sizes while maintaining high resolution,
achieving a 4.86-µm pixel pitch in a 1280×720 array reported in 2020.
As depicted in Figure 2.18, the sensor uses an asynchronous delta modulation (ADM)
technique to extract contrast changes efficiently. The BI-stacked EVS achieves a maximum
event rate of 1.066 billion events per second, with a power consumption of 35 nW per
pixel and 137 pJ per event. Its high temporal precision enables advanced applications
such as structured light pattern decoding in 3D depth sensing.
Figure 2.19 showcases the BI-stacked EVS chip and its application potential, including

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Figure 2.9: Pixel circuit configurations for single and dual conversion gains [1]

Figure 2.10: Pixel circuit configurations of voltage-domain global shutter stacked via
pixel-parallel Cu–Cu connections [1]

low-light scene capture and decoding temporally modulated structured light patterns for
depth estimation.
As shown in Figure 2.20, the trend of reducing pixel pitch in EVSs has led to sub-5 µm
pixels, enabling megapixel resolutions and practical deployments in real-time machine
vision applications.

2.7.2 Invisible-Light Imaging

Stacked device technology has also facilitated invisible-light imaging through hybrid in-
tegration with non-Si photodetectors such as InGaAs, Ge-on-Si, and organic photocon-
ductive films. InGaAs sensors, in particular, are well-suited for short-wavelength infrared
(SWIR) applications in industrial, scientific, and security fields.

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.11: Circuit configuration of the pixel-parallel ADC [1]

Figure 2.24 illustrates the InGaAs image sensor fabrication process, where a 5-µm pixel
photodiode array (PDA) is connected to a readout integrated circuit (ROIC) using Cu–
Cu bonding. This approach replaces traditional flip-chip bumps, enabling fine-pitch pixel
scaling. As a result, InGaAs sensors achieve high-definition SWIR imaging with applica-
tions in inspection and security monitoring, even under foggy conditions.

2.8 Intelligent Vision Sensor

Within the Internet of Things (IoT) market, applications such as retail, smart cities, and
other similar domains increasingly demand camera products with AI processing capabili-
ties. Edge devices with AI processing help address challenges associated with cloud-based
computing systems, such as latency, cloud communication, processing costs, and privacy
concerns. The market demand for smart cameras with AI capabilities includes require-
ments such as small size, low cost, low power consumption, and ease of installation.
However, conventional CMOS image sensors only output the raw data of captured im-
ages. Therefore, developing a smart camera with AI processing requires the integration
of multiple ICs, including an image signal processor (ISP), convolutional neural network
(CNN) processing, DRAM, and other components.
A stacked CMOS image sensor comprising 12.3M pixels and a DSP dedicated to CNN

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.12: Chip implementation of pixel-parallel ADC. (a) Chip micrograph. (b)
Rolling-shutter image. (c) Global-shutter image [1]

computations was reported in 2021. This sensor features an integrated solution that
performs complete image capture and transfers data to a CNN inference processor, as
shown in Figure 2.25. The system operates at 120 frames per second (fps) and includes
on-chip CNN processing using a 4.97 TOPS/W DSP. The processing block consists of an
ISP for CNN input preprocessing, a DSP subsystem optimized for CNN processing, and
an 8MB L2 SRAM for storing CNN weights and runtime memory.

Fig.2.24 presents examples of CNN inference results using MobileNet v1, demonstrating
similar performance to TensorFlow. The intelligent vision sensor can run a complete CNN
inference process on the sensor itself, outputting both raw image data and CNN inference
results in the same frame via the MIPI interface. Additionally, the sensor supports the
output of CNN inference results solely through the SPI interface, enabling a small camera
system with reduced power consumption and lower cost.

The embedded CNN inference processor allows users to program their AI models into
memory and reprogram them as required by the specific conditions of deployment. For
example, when installed at a facility entrance, it can count visitors; when placed on a store
shelf, it can detect stock shortages; and when mounted on a ceiling, it can perform heat
mapping of store visitors. Intelligent vision sensors are anticipated to provide low-cost
edge AI solutions with flexible AI models for various applications.

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.13: Photon-counting image sensor. (a) Chip configuration. (b) Simplified pixel
circuit [1]

2.9 Summary
The proposed methodology leverages stacked device technologies to enhance vision sen-
sor capabilities in depth sensing, temporal contrast detection, and invisible-light imaging.
The BI-stacked SPAD sensor improves near-infrared (NIR) spectral response and depth
accuracy for automotive LiDAR. Event-based vision sensors (EVS) enhance temporal con-
trast detection using asynchronous delta modulation, enabling high-speed machine vision
applications. Additionally, stacked device integration with InGaAs and Ge-on-Si photode-
tectors enables high-resolution short-wavelength infrared (SWIR) imaging for industrial
and security applications. Intelligent vision sensors with embedded AI processing provide
efficient edge AI solutions for applications like visitor counting, stock monitoring, and
heat mapping, reducing dependency on cloud computing.

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.14: Timing diagram for photon-counting with subframe extrapolation [1]

Figure 2.15: Measured results of photon-counting. (a) Dynamic range and SNR. (b)
Captured HDR image. (c) Captured image with motion-artifact suppression [1]

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.16: SPAD device structures. (a) FI SPAD. (b) BI-stacked SPAD [1]

Figure 2.17: BI-stacked SPAD with direct ToF depth sensor [1]

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.18: Pixel block diagram of the event-based vision sensor [1]

Figure 2.19: BI-stacked EVS and examples of its applications: (a) Chip micrographs; (b)
Application examples demonstrating low-light sensitivity and 3D structured light decod-
ing. [1]

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.20: Trend of pixel pitch in EVSs, demonstrating the evolution toward smaller
pixels enabled by stacked device technologies [1]

Figure 2.21: Fabrication process of InGaAs image sensors using Cu–Cu bonding [1]

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.22: Trend in contact pitch of flip-chip bump and Cu–Cu bonding as well as
application examples of InGaAs sensors [1]

Figure 2.23: System diagram of the intelligent vision sensor [1]

Figure 2.24: Measured results of CNN inference [1]

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Figure 2.25: Evolution and future prospects of stacked CMOS image sensors [1]

Dept.of E&CE, S.I.T.,Tumakuru-03 23

Chapter 3
Analysis Of Results
The proposed back-illuminated (BI) stacked Event-Based Vision Sensor (EVS) was eval-
uated in terms of its temporal precision, pixel size, resolution, power efficiency, and prac-
tical applicability in real-time scenarios. The results indicate that the sensor significantly
advances event-based imaging technologies by achieving high-speed, low-power operation
with compact pixel design.

3.1 Sensor Performance Evaluation

The sensor employs a 4.86-µm pixel pitch with a total resolution of 1280×720 pixels.
Unlike traditional frame-based sensors, the EVS responds to changes in light intensity
asynchronously, allowing it to generate data only when events occur at individual pixels.
This characteristic makes the sensor highly responsive and efficient, especially in dynamic
environments.
In terms of raw performance, the sensor is capable of generating up to 1.066 billion
events per second (Geps), while consuming just 35 nW per pixel. The energy required for
processing each event is 137 pJ, making it ideal for power-constrained applications. It also
offers a row-level timestamp resolution of 1 µs, allowing for extremely precise temporal
measurements.

• Pixel Pitch: 4.86 µm

• Resolution: 1280×720

• Event Rate: Up to 1.066 Geps

• Power Consumption: 35 nW/pixel

• Energy per Event: 137 pJ

• Temporal Resolution: 1 µs

These results validate the sensor’s ability to perform under real-time constraints while
maintaining low power consumption and high event throughput.

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25

Table 3.1: Comparison with Previous EVS Architectures

Year Pixel Pitch Resolution Event Rate

2017 9.0 µm 640×480 300 Meps
2019 7.5 µm 1024×768 600 Meps
2020 4.86 µm 1280×720 1066 Meps

3.2 Application Demonstrations

As shown in Figure 2.19, the sensor was tested in a variety of environments to assess its
robustness and versatility. One demonstration involved capturing scenes at light levels
as low as 1 lux, where the sensor accurately responded to contrast changes. This shows
that the BI structure, combined with the ADM technique, supports high sensitivity even
in low-light conditions.
Another test case involved decoding temporally modulated structured light patterns, a
technique used for 3D depth sensing. The sensor’s ability to resolve fine temporal changes
allowed it to interpret structured light patterns with remarkable clarity and speed. This
feature is highly advantageous for applications in robotics, autonomous navigation, and
depth mapping.

3.3 Comparison With Previous Designs

To assess the improvements introduced by this sensor, its specifications were compared
with prior EVS designs. Notably, earlier sensors had a larger pixel pitch (typically 7–9
µm), lower resolution, and less efficient power profiles.
The above table illustrates the steady progression in EVS development and highlights
how the introduction of BI-stacked architecture has enabled finer pixel resolution without
compromising speed or energy efficiency.

3.4 Trend Analysis and Scalability

The pixel pitch trend shown in Figure 2.20 indicates that with stacked sensor technology,
EVSs are becoming increasingly compact and capable of achieving megapixel-class reso-
lutions. As integration technologies like Cu–Cu hybrid bonding continue to mature, even
smaller pixel pitches can be expected.
Furthermore, the use of BI-stacked architecture allows logic circuitry to be separated from

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Advancements in Image Sensor Architectures Using Stacked Device Technologies 2024-25
the photodiode layer. This opens up new possibilities for integrating edge AI accelerators,
in-pixel memory, and real-time data processing within the same chip stack.

3.5 Energy Efficiency and Practical Relevance

From an energy perspective, the sensor demonstrates exceptional efficiency. With just 137
pJ required per event, it is significantly more efficient than frame-based sensors, which
typically consume more power even when no motion occurs in the scene.
This efficiency is especially useful for applications in surveillance, mobile robotics, and
wearable devices, where battery life is a critical constraint. Additionally, because the
sensor only transmits event data (not full frames), it reduces the need for high-bandwidth
communication and minimizes memory usage.

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Chapter 4
Conclusion
The development and evaluation of the BI-stacked EVS presented in this report demon-
strate significant advancements in the field of high-speed, low-power machine vision. By
employing a compact 4.86-µm pixel pitch and ADM readout, the sensor achieves a high
resolution of 1280×720 pixels and an impressive event throughput of 1.066 billion events
per second, all while maintaining a low power consumption of 35 nW per pixel.
The sensor’s ability to detect fine temporal contrast changes with a resolution of 1 µs
enables it to operate effectively in dynamic and low-light environments. Practical demon-
strations such as structured light decoding and low-illumination scene capture further
validate its real-world applicability. Compared to previous EVS architectures, the pro-
posed design offers superior performance in terms of resolution, pixel density, and energy
efficiency.
The stacked device architecture not only enhances sensing performance but also enables
future integration with edge processing units, AI accelerators, and advanced 3D depth
sensing technologies. As the demand for real-time, intelligent vision systems grows in
applications such as robotics, surveillance, and autonomous systems, sensors like the one
discussed in this report are expected to play a pivotal role.
In conclusion, the BI-stacked EVS architecture represents a promising solution for next-
generation vision systems, offering a balance of speed, accuracy, compactness, and energy
efficiency that traditional frame-based sensors cannot achieve.

27
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