Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology

ISSN No- 2584-2706

4 Bit Signed Multiplier Implemented on

FPGA
Ansuman Kumar Sinha
Vikash Ranjan
Rajat Gupta
Nisha Chauhan

Abstract- The importance of hardware provide in contrast to general-purpose

accelerators for arithmetic operations has CPUs. The design and FPGA
been highlighted by the growing need for implementation of a 4-bit signed multiplier
high-performance and low-power digital with two's complement representation is
systems. In embedded systems and digital the main topic of this work. It supports
signal processing (DSP), multipliers are both positive and negative numbers.
essential parts. The design and FPGA A fundamental yet significant building
implementation of a 4-bit signed multiplier piece for low-power and educational
with two's complement representation are applications is the 4-bit signed multiplier.
presented in this paper. The architecture Effective synthesis, simulation, and
optimizes efficiency and resource verification of the design are possible with
utilization by combining partial product hardware description languages like as
generation and adding approaches. Verilog Verilog. On a Xilinx FPGA platform, this
HDL is used for implementation on a work illustrates a full design path that
Xilinx FPGA, and the synthesis results are includes architecture, implementation,
examined in terms of power, time, and simulation, and synthesis. The final design
area. is assessed for speed, functional
correctness, and resource usage, offering
Introduction valuable information on effective
Multipliers are essential parts of digital multiplier design techniques for
systems and are frequently utilized in reconfigurable hardware.
image processing, control systems, and
digital signal processing (DSP). Enhancing Motivation
the total performance of these systems, Arithmetic operations, particularly
particularly in embedded and real-time multiplication, are essential to many
applications, depends on the effective applications in contemporary digital
design and implementation of multipliers. systems, including image processing,
The need for small, high-speed, power- digital signal processing (DSP),
efficient arithmetic units has increased cryptography, and artificial intelligence.
dramatically as digital systems becoming Multiplication is one of these resources.
more complicated. Multiplier implementations, especially in
Field-Programmable Gate Arrays (FPGAs) resource-constrained embedded devices.
offer designers a versatile foundation for Even though commercial FPGAs come
building unique arithmetic circuits, with digital signal processing (DSP)
enabling them to maximize performance blocks that are capable of effectively
according to particular application needs. performing multiplications, it may not
Time-sensitive computations require always be the best option to rely only on
parallelism and hardware-level these blocks. It becomes necessary to
acceleration, which FPGA-based systems manually develop and implement

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Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology
ISSN No- 2584-2706

multipliers utilizing basic logic parts in creation of a signed 4-bit multiplier with
various applications, such as low-power representation based on two's complement.
embedded systems, bespoke processor Verilog Hardware Description Language
design, and educational settings. This (HDL) is used to build the design.
method offers more control and insight Acceptance of Signed Numbers:
into the underlying architecture in addition Inputs of signed integers between -8 and
to enabling optimization in terms of area +7 are accepted by the multiplier. In an 8-
and power. bit signed result, it manages sign extension
An excellent case study for investigating and appropriate output representation.
low-bit-width arithmetic logic architecture Functional testing and simulation:
is a 4-bit signed multiplier. It is To make sure the multiplier works with all
particularly pertinent to systems that deal potential input combinations, a test bench
with fixed-point arithmetic, as well as to is made. Model Sim and other simulation
researchers and students who are just tools are used to verify accuracy.
starting to work with FPGA-based systems Synthesis and Hardware Evaluation:
and digital logic. Using Verilog to Vivado or Xilinx ISE are used to
implement a 4-bit signed multiplier from synthesize the design. Evaluation of
scratch and synthesizing it on an FPGA hardware resource consumption (LUTs,
allows for practical learning and a deeper flip-flops), maximum running frequency,
comprehension of resource management in and power estimation are all part of post-
reconfigurable logic, two's complement synthesis analysis.
arithmetic, and hardware-level Relevance to Education and Research:
computation. This project aims to investigate low-bit-
Furthermore, when fine-grained control width arithmetic unit design and serve as a
over timing and power is needed or when teaching tool in academia. It acts as a
FPGA DSP blocks are already taken or starting point for the building of
unavailable, bespoke multiplier designs are increasingly intricate multipliers and
quite helpful. In order to set the arithmetic logic units (ALUs).
groundwork for scaling up to more
complicated arithmetic designs in bigger Proposed Methodology
systems, this study intends to demonstrate The entire design process of a 4-bit signed
how even a tiny and seemingly simple multiplier is covered by the suggested
arithmetic unit, such as a 4-bit signed technique, from conceptualization to
multiplier, can be optimized and hardware implementation and analysis.
implemented efficiently. The design is created with Verilog HDL
and uses two's complement arithmetic to
Scope of Multiplier accommodate signed numbers.
This project's main goal is to use Field- Below is a summary of the methodology's
Programmable Gate Array (FPGA) main stages:
technology to design, develop, and analyse
a 4-bit signed multiplier. The project's Analysing requirements and
scope is well-defined to provide useful specifications
insights into hardware-level arithmetic Two 4-bit signed inputs (from -8 to +7)
design while preserving a targeted and and an 8-bit signed output (from -64 to
controllable framework. +63) are supported per the design criteria.
The following are important topics All input combinations must yield accurate
covered in the scope: results, and the multiplier must handle
operand signs correctly.
Design and Execution:
Design of Algorithms

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Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology
ISSN No- 2584-2706

The algorithm relies on signed are utilized.

multiplication of two's complement.
Finding each input's sign is one step in the Pre-processing and Sign Handling
process. Utilizing bitwise AND operations The system determines the overall sign of
to generate partial products. Controlling the outcome by comparing the sign bits of
sign extension will maintain the desired inputs A and B, which are represented in
outcome. two's complement form.
Employing adders (behaviouralmodelling In the event that partial product creation is
or ripple carry) to sum partial products. required, operands are transformed to
Making any necessary adjustments to the positive via two's complement inversion.
finished work for sign correction.
Partial Product Generation Each partial
Modelling in HDL product is conditionally shifted according
Verilog HDL is used to implement the to its bit position in the multiplier, and four
multiplier. The design approach is partial products are produced by ANDing
hierarchical and modular, encompassing: each bit of one operand with all bits of the
Handling input signs partially producing a other operand.
product Logic for multi-bit addition
output register for finished goods. Including Partial Items
Behavioural addition logic or ripple-carry
Literature Review logic are used to sum the shifting partial
It has long been known that multipliers are products.
crucial parts of image processing, control During summation, intermediate carry
systems, and digital signal processing handling guarantees that every bit is
(DSP). Optimizing multiplier designs to appropriately accounted for.
improve performance in terms of speed, Output Interface
area, and power efficiency has been the • Product: The outcome of A × B is
subject of numerous studies. An overview represented as an 8-bit signed output.
of pertinent works that support the creation • For stability and precise timing analysis,
and application of signed multipliers on the output is registered and synchronized
FPGA platforms is provided in this survey with the system clock.
of the literature.

System Architecture Block Diagram

Using two's complement representation,
the architecture of the suggested 4-bit Below is a high-level breakdown of the
signed multiplier is made to precisely Signed Multiplier.
multiply two signed 4-bit inputs. On
FPGA hardware, the system is designed to
manage sign extension, partial product
production, and final result summing while
striking a compromise between functional
accuracy and resource efficiency.

Interface for Input

Operands: A and B, two signed 4-bit
inputs with values between -8 and +7.
Control Signals: For output
synchronization and sequential operation,
a clock signal and an optional reset signal

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Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology
ISSN No- 2584-2706

Experimental Results

Input Input Expected Actual

Operation Status
A B Output Output

0101 0011 1000

Addition 1000 (+8) Pass
(+5) (+3) (+8)

0100 1100
Addition 0000 (0) 0000 (0) Pass
(+4) (-4)

1001 0011 1010 (-

Subtraction 1010 (-10) Pass
(-7) (+3) 10)

0110 1101 1001

Subtraction 1001 (+3) Pass
(+6) (-3) (+3)

1010 0010 111100 (- 111100

Multiplication Pass
(-6) (+2) 12) (-12)

0111 0111 110001 110001

Multiplication Pass
(+7) (+7) (+49) (+49)

Component Used Both simulation tools and hardware

Input Registers verification (such as an FPGA or
Sign Extension Unit microcontroller environment) were used to
Adders, Comparators create a number of test cases in order to
FPGA Resource confirm the proposed 4-bit signed
Input Register

 Hold the 4-bit signed operands calculator's performance and functionality.

(multiplicand and multiplier). The calculator's design supported addition,
 Usually in 2's complement subtraction, and multiplication, and it
format to support signed could take 4-bit signed binary inputs in
arithmetic. two's complement format.

Half Adders and Full Adders are used A. Examples of Test Cases
to add partial products. For every operation, 256 possible input
In some architecture, Carry Save combinations (16 × 16) were investigated.
Adders (CSA) or Ripple Carry Adders For clarity, sample test scenarios are
(RCA) is used to improve performance. shown in Table 1:
It is perfect for high-speed, low-power
Implementation utilizes LUTs (Look- applications.
Up Tables), Flip-Flops, Multiplexers, Although they used somewhat more
and possibly DSP slices (if available on resources, the Wallace Tree and Booth
the target FPGA). implementations outperformed the simple
Synthesis and simulation tools include array multiplier in terms of speed.
Xilinx Viv ado, model Sim, or Quartus. Despite having the simplest architecture,

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Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology
ISSN No- 2584-2706

the array multiplier had the highest delay basic user interface, which could be
and the lowest operating frequency. hardware-based (keypad and display)
or software-based (guild panel or
Future Work command-line tool).
Although the 4-bit signed calculator's F. Error Handling and Diagnostic
current implementation effectively and Features
accurately completes simple arithmetic the calculator can be made more
operations, there are a number of ways that robust and dependable by adding
this project could be expanded and improved error detection and repair
improved: procedures (e.g., for overflow, invalid
inputs, divide-by-zero, etc.).
A. Increasing the Bit Widths G. Implementation of FPGA and ASIC
scaling the calculator to include 8-, The design can even be manufactured
16-, or even 32-bit signed operations as an ASIC for instructional kits or
is one quick addition. As a result, it embedded processor co-processors, or
would be more applicable to intricate it can be further evaluated and refined
calculations and embedded systems in for synthesis on various FPGA
the real world. Additionally, higher bit platforms.
widths necessitate more resilient
management of carry propagation and Conclusion
overflow. The design, implementation, and
B. Assistance with Extra Activities evaluation of a 4-bit signed calculator that
Future versions can incorporate can carry out simple arithmetic operations
support for division, modulo, bitwise using two's complement format were
logic (AND, OR, XOR), and shift reported in this work. The calculator's
operations (logical and arithmetic). accuracy in addition, subtraction, and
These would increase the calculator's multiplication was confirmed through
use in logical and arithmetic extensive testing using a range of input
computations. combinations. The outcomes validated
C. Floating-Point Arithmetic Integration efficient overflow detection, correct
Although it would require more handling of signed values, and accurate
complicated hardware implementation functionality.
and resource consumption, adding Because of its quick operating speed and
support for floating-point numbers minimal resource consumption, the system
(such as IEEE 754) could be a useful is appropriate for embedded and
improvement for scientific and instructional applications. Additionally, by
engineering applications. employing basic digital logic design ideas,
this project lays the groundwork for more
D. Low Power and Area Optimization intricate arithmetic logic units.
to maximize performance in power- Overall, the suggested design strikes a
constrained situations, such as IoT compromise between usefulness and
devices, power-efficient design simplicity, and it can be expanded to
strategies like clock gating, operand accommodate more features like floating-
isolation, or the use of approximation point operations, wider bit widths, and
computing techniques could be more advanced error handling in future
investigated. work.
E. Accessibility and User Interface
The calculator could be made more Reference
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instructional purposes by developing a of Digital Logic with Verilog Design,

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Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology
ISSN No- 2584-2706

McGraw-Hill, 2009. This book serves as a practical guide to

Xilinx Inc., Artix-7 FPGA Datasheet, Verilog HDL, offering insights into
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M. Morris Mano, "Digital Design," 5th Alan V. Oppenheim and Ronald W.
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coverage of digital design principles, DSP, including the use of multipliers in
including arithmetic circuits, which are signal processing applications.
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design.
G. S. Yadav, R. P. Sharma, "Design and
FPGA Design and Implementation: Implementation of 4-Bit Multiplier Using
Xilinx, "Vivado Design Suite User Guide: VHDL," International Journal of
Synthesis (UG901)," Xilinx, 2020. Engineering and Advanced Technology
This user guide offers detailed instructions (IJEAT), Volume 9, Issue 1, October
on using Xilinx Vivado for FPGA design 2019.
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practices. designing multipliers using HDL,
Verilog HDL: providing a valuable comparison for
methodology.
Samir Palnitkar, "Verilog HDL: A
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and Synthesis," 2nd Edition, Prentice Hall.

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