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com Description

Design Guide: TIDA-010240

Scalable Multi-Pack Smart Battery Charger
Reference Design

Description Features
This reference design is a smart high-efficiency • Provides a complete drop-in battery charging
charger design for dual smart battery packs of up to system for charging and communication with two
100 Watt hours (Wh) implemented as 1S–5S Lithium- smart Lithium-Ion batteries
ion (Li-ion) batteries in a parallel configuration. • Supports 1S–5S packs with charge currents of up
To achieve this an onboard MCU manages the to 16-A per battery
communication and safety features needed for the • Onboard MCU for charge control and upstream
charging system to interface with a battery pack communication with system host
designed to the Smart Battery Data Specification • Onboard MCU communicates with smart battery
Revision 1.1 (SBD 1.1). This communication allows gauges to read charging information and monitor
the MCU to initialize two independent battery charger alerts
ICs to the correct charging parameters, as well as
inhibit charging when the batteries are outside of safe
Applications
specifications. This design also demonstrates a high- • Oxygen concentrator
efficiency system power MUX for selecting between • CPAP machine
the input adapter and efficient discharge of the two • Multiparameter patient monitor
smart batteries simultaneously. These features make • Dialysis machine
this reference design highly applicable for portable
medical devices, such as oxygen concentrators.

Resources
TIDA-010240 Design Folder
BQ25731 Product Folder
LM7480-Q1, LM74700-Q1 Product Folder
MSP430FR2475, PCA9546A Product Folder

Ask our TI E2E™ support experts

Input Protection/
Priority MUX
To BQ Input

0.002  0.002

CSD17581Q3A CSD17581Q3A CSD17581Q3A
DC_Adapter (12V–19V) 30-V NFET 3.8 m
DC_IN SYS_PWR SYS_PWR
30-V NFET 3.8 m 30-V NFET 3.8 m

LM74800-Q1 TLV9051 SYS_CURR

Host Interface(I2C) INA213
TLV9051 SYS_CURR_AVG
MSP430FR2475
PCA9546A
MCU for charge control and CHG_Interface(I2C)
I2C/SMBus MUX
host communication

NTC Pin BQ40Z50-R2

CHG_Interface Li-Ion Guage

0.005 
CSD17551Q3A CSD17551Q3A 1S-5S Li-Ion
DC_IN 0.005 BAT_A
30-V NFET 9 m 30-V NFET 9 m
30-V NFET 9 m

30-V NFET 9 m
CSD17551Q3A

CSD17551Q3A

30-V NFET 3.8 m

CSD17581Q3A

BQ25731 LM74700-Q1
1S–5S Li-Ion Charger
Buck-Boost BAT ORing/
CHG_Interface Priority MUX

CSD17581Q3A
30-V NFET 3.8 m SYS_PWR
30-V NFET 3.8 m
CSD17581Q3A

CHG_Interface
BQ25731
1S–5S Li-Ion Charger LM74800-Q1
Buck-Boost
30-V NFET 9 m

30-V NFET 9 m
CSD17551Q3A

CSD17551Q3A

NTC Pin BQ40Z50-R2

CHG_Interface Li-Ion Guage

0.005  0.005 
CSD17551Q3A CSD17551Q3A 1S–5S Li-Ion
DC_IN BAT_B
30-V NFET 9 m 30-V NFET 9 m

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1 System Description
All portable equipment carried in aircrafts – including life-critical medical equipment such as portable ventilators,
electrocardiogram devices (ECGs), and continuous positive-airway-pressure (CPAP) machines – are subjected
to safety restrictions implemented by the Transportation Security Administration (TSA). Lithium batteries with
more than 100 watt-hours (Wh) are generally not permitted in carry-on luggage, and any exceptions to this
rule lie at the discretion of airlines and require prior approval. This disruption is not ideal for passengers who
require these devices out of medical necessity. With the capabilities of Li-ion battery charging technology today,
medical instrument manufacturers can alleviate this patient burden. To satisfy travel restrictions while also
doubling the backup time of the equipment, two 100-Wh batteries can be implemented in the system design.
This configuration will also require fewer spare batteries, increasing convenience for the end user during travel.
This design guide details the implementation of two BQ25731 chargers managed by an onboard MCU to achieve
these requirements for airline travel.
2 System Overview
2.1 Block Diagram

Input Protection/
Priority MUX
To BQ Input

0.002  0.002

CSD17581Q3A CSD17581Q3A CSD17581Q3A
DC_Adapter (12V–19V) 30-V NFET 3.8 m
DC_IN SYS_PWR SYS_PWR
30-V NFET 3.8 m 30-V NFET 3.8 m

LM74800-Q1 TLV9051 SYS_CURR

Host Interface(I2C) INA213
TLV9051 SYS_CURR_AVG
MSP430FR2475
PCA9546A
MCU for charge control and CHG_Interface(I2C)
I2C/SMBus MUX
host communication

NTC Pin BQ40Z50-R2

CHG_Interface Li-Ion Guage

0.005 
CSD17551Q3A CSD17551Q3A 1S-5S Li-Ion
DC_IN 0.005 BAT_A
30-V NFET 9 m 30-V NFET 9 m
30-V NFET 9 m

30-V NFET 9 m
CSD17551Q3A

CSD17551Q3A

30-V NFET 3.8 m

CSD17581Q3A

BQ25731 LM74700-Q1
1S–5S Li-Ion Charger
Buck-Boost BAT ORing/
CHG_Interface Priority MUX

CSD17581Q3A
30-V NFET 3.8 m SYS_PWR
30-V NFET 3.8 m
CSD17581Q3A

CHG_Interface
BQ25731
1S–5S Li-Ion Charger LM74800-Q1
Buck-Boost
30-V NFET 9 m

30-V NFET 9 m
CSD17551Q3A

CSD17551Q3A

NTC Pin BQ40Z50-R2

CHG_Interface Li-Ion Guage

0.005  0.005 
CSD17551Q3A CSD17551Q3A 1S–5S Li-Ion
DC_IN BAT_B
30-V NFET 9 m 30-V NFET 9 m

Figure 2-1. TIDA-010240 Block Diagram

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2.2 Design Considerations

2.2.1 Power Multiplexing Circuit Design Parameters
Figure 2-2 illustrates the input and battery MUX circuit schematic.

IN_ISNS_N
IN_ISNS_P
RVP Protected Supply for Battery Chargers
VIN_FLT VIN_PROT
VIN Screw Terminal Adapter/Battery MUX Output
VIN_FLT
Input Voltage Range
11-19 V Input Pi filter
CSD17581Q3A VIN_PROT CSD17578Q3A CSD17578Q3A
8A Max
Vin Vin L1 MUX_PWR
J1 Vin Q1 Q2 Q11
2 R1
1,2,3 7,8 7,8 1,2,3 1,2,3 7,8
1 160nH 0.002
5,6, 5,6, 5,6,
C7
D1 C8 63V

4
C9 C10 C11 C12 U1 100nF 47uFMUX_PWR
GND 1.5nF 22V 22µF 22µF 50V 100V
50V 35V 35V 0.1uF C15 10 12
VS C
50V GND
Input Jack with PS_ID Pin 0.1uF
Diode protection for 11 8 GND
CAP HGATE
Vin 22V Adapter input, with
J12 GND Pi Filter 1 9
DGATE OUT
V+ 3
2 13
S A RTN
1 PS_ID
R103 3
OV set at 22 V VSNS
V- 2 0
ON @ 22V=1.23/(68.1/(1.15k+68.1)) R6
PJ-098H 4
OFF @ 20.2V=1.13/(68.1/(1.15k+68.1)) 1.15k SW
TP5
5
OV
GND TP_SM_1MM
6 7
EN/UVLO GND
R8 C139 R87
68.1 50V 5.97k LM74800
0.1uF
GND
UV/OV_SET TP6

TP_SM_1MM
GND R88 C154
715 50V
0.1uF UV set at 11.5 V
ON @ 11.5V=1.23/(715/(5.97k+715))
OFF @ 10.56V=1.13/(715/(5.97k+715))

VBAT_B GND
VBAT_B CSD17581Q3A Q3

1,2,3 7,8
5,6, C85
C22 U5 1µF
4

35V 35V
33uF 6 5
ANODE GATE
C24
50V 1 4 GND
VCAP CATHODE
GND 0.1uF

3 2
EN GND

LM74700QDBVRQ1
Ideal Diode ORR of Batteries
GND
Adapter/Battery MUX Output
VBAT_A Q4 CSD17581Q3A BattORR BattORR Q5 CSD17578Q3A
VBAT_A MUX_PWR
1,2,3 7,8 7,8 1,2,3
5,6, C28 5,6,
100nF
4

100V
C27 R84
50V 50.0k GND 3 Q21 2 C29
0.1uF 63V
U7 47uF
1

BC817-16LT1G
10 12 D10
VS C
GND C31 50V
50V 11 8 GND
0.1uF CAP HGATE
1 9
DGATE OUT
2 13
A RTN
VIN_FLT
TP7 3 HGATE current injection limiting
VSNS
R20 R = ((16.8 V + 15V)/600uA)
TP_SM_1MM
5.97k 4 Currently Set at 600uA, R = 53k
SW
TP8 R109 UV/OV_SET 5
OV
TP_SM_1MM 0 BattORR
TP9 6 7
R21 EN/UVLO GND
TP_SM_1MM
715 LM74800

GND
OV = Inverse of VIN LM74800 UVLO
OFF @ 11.5V=1.23/(715/(5.97k+715))
GND
ON @ 10.56V=1.13/(715/(5.97k+715))

Figure 2-2. Input and Battery MUX Circuit Schematic

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2.2.2 Input Connections and Filter

The reference design board includes a screw terminal (J1) for input connections to a power supply. This board
was tested with supplies ranging from 12 V to 19 V, but can function with inputs of 11 V to 22 V. The design also
includes a barrel jack connector (J12) for easy connection to existing adapters. There is also a common PI filter
at the input of this board for EMI filtering.
Calculate the corner frequency for a PI filter using Equation 1.

1
Fc = (1)
2π × LC

In this case, L1 = 160 nH and C10, C11 = 22 μF, resulting in a corner frequency of about 85 kHz.
2.2.3 Reverse Polarity Protection
For reverse polarity protection (RVP) the LM74800 (U1) monitors the voltage across Q1. When the reverse
voltage across Q1, monitored with the A and C pins, exceeds –4.5 mV, the device turns off Q1 using the DGATE
pin. This circuit acts a high-efficiency replacement for a Schottky diode.
2.2.4 Battery Charger Input
After the reverse polarity protection, a 2-mΩ sense resistor is added to monitor the overall system input current.
After this sense resistor, a VIN_PROT rail is defined. The VIN_PROT rail acts as an always on supply from the
input with reverse polarity protection. This rail directly powers the BQ25731 charger devices.
2.2.5 Battery Ideal Diode-OR

To discharge the two independent batteries in the design, an ideal diode-ORing circuit is used. In this circuit, Q3
and Q4 are driven by U5 and U7 to regulate the FET forward voltage drop to 20 mV. This allows for the efficient
discharge of both batteries at the same time, while also preventing current from traveling from one battery to the
other. This circuit also allows for passive battery pack voltage balancing to occur in the system by drawing more
current from the battery with a higher voltage. Equation 2 shows an example calculation of battery discharge
current based on voltage and equivalent series resistance (ESR). For this example, it is assumed that BAT_A is
at 16.8 V and has an ESR of 50 mΩ, BAT_B is at 16.6 V and also has an ESR of 50 mΩ, and the system is
drawing 8 A.

ILOAD = IBATA + IBATB

VLoad = VBATA − VAf − IBATA × ESRBATA

VLoad = VBATB − VBf − IBATB × ESRBATB

VBATA − VAf − IBATA × ESRBATA = VBATB − VBf − IBATB × ESRBATB

16.8 V − 20 mV − IBATA × 50 mΩ = 16.7 V − 20 mV − IBATB × 50 mΩ

IBATA = IBATB + 2.0, wℎere IBATB ≥ 0 (2)

In this example, BAT_A supplies 2 A more current that BAT_B until the higher current discharge causes the
voltage differential between the batteries to be reduced.
2.2.6 Input and Battery Switchover Mechanics
This design provides an input and battery MUX that prioritizes the input adapter in all cases where the
adapter voltage exceeds the UVLO setting of U1. When the UVLO threshold is triggered, the input adapter
is disconnected from the system and the batteries are connected to power the system load. This prevents the
batteries from discharging while an input adapter is present.
This threshold is set by the resistor divider consisting of R87 and R88. For U1 (input adapter connection) the
UVLO thresholds are 1.13 V falling for turn off, and 1.23 V rising for turn on. For U7 (battery connection) the OV
pin is connected to the same divider and the thresholds operate inversely. These thresholds are 1.13 V falling for

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turn on, and 1.23 V rising for turn off. In the schematic this voltage is connected to the net labeled UV/OV_SET.
In the current schematic the switchover from input adapter to battery is triggered when VIN reaches 10.56 V and
the switchover from battery to input adapter is triggered when VIN reaches 11.5 V.
Equation 3 shows an example of the resistor divider calculation:

1.23 V
Battery to Input Adapter Transition = R88
R87 + R88

1.13 V
Input Adapter to Battery Transition = R88
R87 + R88

R87 = 5.97 kΩ, R88 = 715 Ω

1.23 V
Battery to Input Adapter Transition = 715 Ω = 11.5 V
5.97 kΩ + 715 Ω

1.13 V
Input Adapter to Battery Transition = 715 Ω = 10.56 V (3)
5.97 kΩ + 715 Ω

2.2.7 LM74800 (U1) HGATE

The HGATE design for U1 includes two back-to-back NFETs (Q2 and Q11). Q11 was added to the design to
prevent any current from flowing from the batteries to the VIN_FLT rail when the batteries are connected to the
system. When only Q2 is placed and (V_SYS > VIN_PROT + 0.8 V) a current is conducted through the body
diode of Q2. This allows a current loop to form between the output of both BQ25731 devices and the input of the
BQ25731 devices.
2.2.8 Battery LM74800 HGATE
Adjustments were made to the HGATE design of U7 to reduce the turn on time of Q5. This reduction is made
by increasing the gate current delivered to Q5 from 55 μA to 600 μA. To increase the HGATE current that can
be delivered by U7, a circuit including D10, Q21, and R84 was added. This circuit amplifies the source current
of the HGATE pin by driving an NPN transistor (Q21) that is connected between the charge pump output (CAP,
U7 pin 11) and the gate of Q5. A series resistance (R84) is also added to this path to limit the current injection.
Diode (D10) is also added between the gate of Q5 and HGATE (U7 pin 8) to allow the HGATE pin to sink current
when turning the FET off. Equation 4 provides an example calculation for the HGATE current injection limit. The
charge pump of the LM74800 provides an output of VS + 13.2 V. In this case VS is connected to the output of
the batteries and is assumed to be 16.8 V. The charge pump can supply a maximum current of 2.4 mA. The
current design has the injection current set to be 600 μA, but this current can be increased by reducing R84.
Example 1.

V +V
R84 = VS I CHGPUMP
gate

Example 2.

R84 = 16.8600
V + 13.2 V
μA = 50.0 kΩ

R84 = 16.82.0
V + 13.2 V
mA = 15.0 kΩ (4)

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2.2.9 BQ25731 Design Considerations

Figure 2-3 illustrates the BQ25731 component selection.
C33 C34 C35 C36 C37 C38 C39
0.01uF 10uF 10uF 10uF 10uF 10uF 10uF

GND

C40 C41
C42 C43 33uF 33uF
10uF 10uF 35V 35V
Q6 Q7 Q8 Q9 VBAT_A
VIN_PROT CSD17578Q3A CSD17578Q3A CSD17578Q3A CSD17578Q3A
R23
GND
R24 4.7µH R25 0.005
7,8 1,2,3 1,2,3
0.047uF
7,8
C45 C46 C47 C48 C44

5,6,
L2 0

5,6,
7,8
0.005

7,8
C49 C50 C51 C52 C53 C54 C55 C57 C58 3 Q10 C59
5,6,
0.047uF C56
5,6,
33uF 33uF 33uF 47uF
10uF 10uF 10uF 10uF 10nF 1000pF 4 330pF C60 C61 4 10uF 10uF 35V 2 1uF

4
35V 35V 35V 35V 50V 50V 330pF 1 5-6-7-8 0.1uF

1,2,3
R26 R27 R28 R29

1,2,3
U9
4.99 R30 56 10 10
C62 VDDA_A C63 GND
4.99 R31
GND C64 GND 7 GND C65
VDDA

4
56
VIN_PROT 150pF 30 25 150pF SISS27ADN-T1-GE3
C66 C67 C68 C69 BTST1 BTST2 0.068uF
0.01uF
10uF 10uF 10uF 10uF 32 23 50V
35V 35V 35V 35V C71 SW1 SW2
C70 GND SRP_A SRN_A
0.033uF 0.033uF R32 29 26 GND
LODRV1 LODRV2
1.0
GND 31 24 C72 C73
HIDRV1 HIDRV2
GND GND VBUS_A 18nF 18nF
1 22 50V 50V
VBUS VSYS
ACP_A ACN_A
C74 ACN_A 2 21
470nF ACN BATDRV
GND GND
50V ACP_A 3 20 SRP_A
ACP SRP B
GND 19 SRN_A
SRN
C75 REGN_A C76
28
REGN BAT_A Screw Terminal
ILIM 6 VDDA_A
33pF ILIM_HIZ 2.2uF 16.8V MAX
VDDA_A BAT_A
R33 4A MAX
REGN_A C77 4700pF R34 40.2k 16 17 C78 GND
R35 VDDA_A COMP1 COMP2 R36
15.0k 2
10 3.3V 680pF R37 0 1
C79 GND R38 PROCHOT_A 11 C80 15pF GND 33k
PROCHOT C81
1uF 10.0k 3.3V 18 33uF C82 C83 J2
CELL_BATPRESZ 4 CELL 10uF 10uF D5
CHG_A_SCL 13 35V
SCL
GND
GND R39 CHG_A_SDA 12 8 IADPT_A R40
10.0k SDA IADPT 100k
CHG_OK_A 4 9 IBAT_A
CHRG_OK IBAT C84 R42
5 10 PSYS_A 100pF 191k GND
OTG/VAP PSYS
C86 R43
15 100pF 100k GND
CMPOUT R44
3.3V 33
Thermal_Pad 30.1k
14 27
CMPIN GND
BQ25731RSN
2

D6 GND
150060VS75000 GND
Green
1

R46 GND
220
3

CHG_OK_A 1 Q12
NX3020NAKW,115
2

GND

Figure 2-3. BQ25731 Component Selection

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2.2.10 BQ25731 Component Selection

Components for the BQ25731 Charge Controllers were selected to be as flexible as possible for this reference
design. For a more detailed guide on component selection specific to your design, see the Detailed Design
Procedure section in the BQ25731 I2C 1- to 5-Cell Buck-Boost Battery Charge Controller with USB-C PD 3.0
OTG Output data sheet.
2.2.11 ILIM Circuit
For this design a circuit was added to limit the system current to 8 A. This is most impactful when the device is
being used with a 12-V car adapter and can pull the battery voltage below the input threshold of the system. This
circuit includes the INA213B to amplify the current across a 2-mΩ sense resistor. This INA213B has a gain of 50
V/V so an input of 8 A results in an 800-mV output.
3.3V
R7
200k
3.3V
C18 R9 C19
100nF 75k
6.3V
100nF
6.3V GND ILIM

5
3
+ 1.0V <=ILIM <=2.6V
GND 1 ILIM
4 -
R12 (0A <=ICHG <=8A)/2
IN_ISNS TLV9051IDBVR
2
100k U3

GND
R13
fc = 159Hz
200k
C23

10nF
6.3V

Figure 2-4. Current-Limit Circuit

To convert this signal into a usable voltage for the ILIM pin of the BQ25731 devices, an op amp configured as
a difference amplifier was used. The voltage on the BQ25731 ILIM pin is converted to charge current based on
Equation 5.

V ILIM_HIZ = 1 V + 40 × IDPM × Rac (5)

where
• IDPM is the target input current limit
• Rac is the 5- or 10-mΩ resistor chosen for the BQ25731
Rf
R1
V1
–
Vout
V2 +
R2
Rg

Figure 2-5. Difference Amplifier

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For the difference amplifier when:

Vout = V2 − V1 (6)

where
• R1 = R2 = Rf = Rg, Vout = V2 − V1

To correctly set the BQ25731 charge current, set the ILIM pin at 1.0 V with 8 A of system current and 1.8 V with
0-A system current. Limit the charge current for each of the 2 charger devices to between 0 A and 4 A.
Set V2 at 1.8 V in this case. With V2 at 1.8 V, the voltage at the amplifiers positive input is equal to V2/2, which
is 0.9 V. This voltage then needs to be created with the system 3.3-V rail and a resistor divider to match the
calculated set point. This was implemented with a R7 and R9 as shown in the schematic above.

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2.2.12 MCU and I2C Bus Design Considerations

Figure 2-6 shows the MSP430FR2475, TPS62177, PCA9546A MCU and I2C bus schematic.
MSP Programming Header Upstream Facing I2C Port Downstream Facing I2C Port
3.3V
3.3V MSP_Tool J4 3.3V 3.3V 3.3V 3.3V
2 1 SBW_TDIO
R71 4 3
Unused SPI Header TP1 TP2
0 6 5 R72 R45 R65 UCB1SDA R73 R74 UCB0SDA
47.0k 4.30k 4.30k 4.30k 4.30k I2C Bus Tie if Needed
8 7 SBW_TCK J11
10 9 1 2 UCA1CLK J5 J7
12 11 SBW_TDIO UCA1SOMI 3 4 UCA1SIMO 1 MSP_UCB1_SDA 1 MSP_UCB0_SDA MSP_UCB1_SDA R107 MSP_UCB0_SDA
14 13 2 MSP_UCB1_SCL 2 MSP_UCB0_SCL MSP_UCB1_SCL R108 MSP_UCB0_SCL
0
C141 HTSW-102-07-G-D 3 3 0
SBH11-PBPC-D07-ST-BK 25V UCB1SCL UCB0SCL
1100pF GND PEC03SAAN PEC03SAAN
GND TP3 TP4
GND GND 3.3V
GND
3.3V

C142 C143 I2C MUX (MSP -> Chargers+Gauges) R75 R76 R77 R78 R79 R80 R81 R82
U11
10V 0.1uF U12 4.30k 4.30k 4.30k 4.30k 4.30k 4.30k 4.30k 4.30k
10uF 10V 32
DVCC R93
29 Xout MSP_UCB1_SCL 12 3 CHG_A_SCL
P2.0/XOUT R94 SCL SC0
20 30 Xin MSP_UCB1_SDA 0 13 2 CHG_A_SDA
VREG P2.1/XIN SDA SD0
GND 11 MSP_I2C_Master_RST 0
P2.2/SYNC/ACLK/COMP0.1
MSP_SYS_CURR 7 14 MSP_P2.3 15 5 CHG_B_SCL
P1.0/UCB0STE/TA0CLK/A0/VEREF+ P2.3/TA2.0/CAP0.2 A0 SC1
IN_ISNS 8 17 UCA1CLK 3.3V 16 4 CHG_B_SDA
P1.1/UCB0CLK/TA0.1/COMP0.0/A1 P2.4/UCA1CLK/CAP1.1 A1 SD1
MSP_UCB0_SDA 9 18 UCA1SOMI 11
P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/VEREF- P2.5/UCA1RXD/UCA1SOMI/CAP1.2 A2
MSP_UCB0_SCL 10 19 UCA1SIMO 8 BAT_A_SCL
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 P2.6/UCA1TXD/UCA1SIMO/CAP1.3 SC2
PS_ID_CMP 3 25 MSP_P2.7 7 BAT_A_SDA
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ P2.7/UCB1STE/CAP3.0 SD2
VIN_LOW 4 R83
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
SAFETY_A 5 22 STATUS_LED0 4.30k GND 10 BAT_B_SCL
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 P4.0/TA3.1/CAP2.1 R69 SC3
SAFETY_B 6 23 STATUS_LED1 MSP_I2C_Master_RST 1 9 BAT_B_SDA
P1.7/UCA0STE/SMCLK/TDO/A7 P4.1/TA3.0/CAP2.2 RESET SD3
P4.2/TA3CLK/CAP2.3
24 MSP_P4.2 0
MSP_P3.0 12 3.3V 17
P3.0/TA2.2/CAP0.0 EP
MSP_P3.1 16 1 SBW_TDIO 14 6
P3.1/UCA1STE/CAP1.0 RST/NMI/SBWTDIO VCC GND
MSP_UCB1_SDA 27 2 SBW_TCK
P3.2/UCB1SIMO/UCB1SDA/CAP3.2 TEST/SBWTCK
MSP_P3.3 13 PCA9546ARGVR
P3.3/TA2.1/CAP0.1
MSP_P3.4 15 C144 C145
P3.4/TA2CLK/COMP0OUT/CAP0.3
MSP_P3.5 26 16V 16V GND
P3.5/UCB1CLK/TB0TRG/CAP3.1
MSP_UCB1_SCL 28 31 1uF 0.1uF
P3.6/UCB1SOMI/UCB1SCL/CAP3.3 DVSS
MSP_P3.7 21 33
P3.7/TA3.2/CAP2.0 PAD

GND
MSP430FR2475TRHBR
GND
1 2
Unused MSP Pin Breakout
J13
Y1 Battery Safety Pin Bias
1 MSP_P2.3
Battery Communication Pins Header
2 MSP_P2.7 3.3V 3.3V 3.3V
MSP_P3.0 J6
Xout

3
Xin

4 MSP_P3.1 1 2
5 MSP_P3.3 CHG_A_SCL 3 4 BAT_A_SCL
C146 C147 6 MSP_P3.4 R22 R41 CHG_A_SDA 5 6 BAT_A_SDA
50V 50V 7 MSP_P3.5 1.13k 1.13k CHG_B_SCL 7 8 BAT_B_SCL GND
12pF 12pF 8 MSP_P3.7 CHG_B_SDA 9 10 BAT_B_SDA
9 MSP_P4.2 SAFETY_A SAFETY_B SAFETY_A 11 12 SAFETY_B
10
TSW-106-07-G-D
800-10-010-10-001000 R91 R92
GND 54.9k 54.9k
GND

GND GND

3.3V 3.3V
3.3V Input Selection
3.3V Power supply for EVM
VIN_PROT 3.3V_Buck
J8 U13 L4 3.3V Buck 3.3V_Buck J9 3.3V 3.3V

2
1 1
2 2
VIN SW
9 2 D11 D9
3 10uH 150060VS75000 150060VS75000
V_SYS 3 10 TSW-102-07-G-S Green Green

1
EN VOS
PEC03SAAN
3.3V_Buck 7
PG
8 5
SLEEP FB
C148 C149 C150 C151 C152 C153 R90 R86
25V 25V 25V 6 25V 25V 25V 220 220
AGND
10uF 10uF 1uF 10uF 10uF 1uF
LED for development LED for development
1
GND
4 11 TP12 TP13 TP14 TP15 TP16 TP17
NC DAP

3
TPS62177DQCR STATUS_LED1 1 Q18 STATUS_LED0 1 Q20
5011 5011 5011 5011 5011 5011 NX3020NAKW,115 NX3020NAKW,115

2
GND
GND

GND GND

Figure 2-6. MSP430FR2475, TPS62177, PCA9546A MCU and I2C Bus Schematic

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2.2.13 MSP430FR2475
The MSP430FR2475 was chosen for this application because of its low cost, two eUSCI_B channels supporting
I2C, eight 12-bit ADC channels, and small footprint. The two eUSCI_B I2C channels allow for two independent
interfaces, one between the MCU and Host controller, and one between the MCU and downstream devices such
as the battery chargers and gauges included in the smart battery packs.
2.2.14 I2C Bus Overview
The I2C bus for this design was broken into two separate communication channels. One of these channels
uses the UCB0 peripheral to communicate with an upstream host. This allows for data and control registers
to be maintained in the MSP430 that can be read from or written to by the system host. This peripheral also
allows for a hardware I2C address to be assigned in the firmware, providing a system that can be configured to
communicate directly with a host that is using existing hardware and firmware.
The other I2C channel using UCB1 acts as a downstream facing port to control the charging system for this
design. The PCA9546A I2C MUX is used to interface directly with multiple downstream devices using the same
address. This uses all four channels of the PCA9546A to communicate with two BQ25731 devices at address
0x6B, and two gauges at address 0x16, as is outlined by the Smart Battery Data Specification 1.1.
2.2.15 MSP430 Connectors
This reference design includes an MSP Programming header that is compatible with TI’s MSPFET device for
programming and debugging. Headers are also included for UCA1(J11), UCB0(J5), and UCB1(J7) to enable
direct connection to the communication interfaces used by this design. Header J6 has also been added to allow
for connection of the smart battery communication and safety signal pins.
2.2.16 MSP430 Power Supply
The onboard MSP430 is powered by the TPS62177 device , a high-efficiency synchronous step-down DC/DC
converter. The input of this converter is selected by J8, and can either be powered by V_SYS or VIN_PROT.
This also allows for the converter to be easily supplied by an external source by connecting it directly to pin 2 of
J8. The output of this converter is 3.3 V and is used to supply the MSP430, op amps, and comparators in the
design. The device also has a sleep pin that is not currently being used, but can be enabled in later designs.
2.2.17 Sensing Circuits
This reference design includes multiple sensing circuits that enable the MCU to monitor multiple items in the
system. This includes input current and voltage, system current and voltage, input voltage comparator, and a
Power Supply ID (PS_ID) comparator.

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2.2.18 Current Sensing

Two INA213B devices are used for current sensing in this design. The INA213 is a current-shunt monitor design
for both high- and low-side current measurements. Both of these devices are supplied by 3.3 V, referenced
to ground, and provide a gain of 50 V/V. U2 measures the current across the 2-mΩ sense resistor R1, which
provides an input current measurement for both the system rail and battery charge currents. U4 measures the
current across the 2-mΩ sense resistor R2, which provides a measurement of the current on the system output
rail.
3.3V 3.3V
C21 C13

System Current Sense Amplifier 100nF Input Current Sense Amplifier 100nF

3
6.3V IN_ISNS 6.3V SYS_ISNS
SYS_ISNS_N R10 5 GND IN_ISNS_N R3 5 GND
4.99 V+ 6 SYS_ISNS 4.99 V+ 6 IN_ISNS
C20 4 V- C14 4 V-
8A = 800mV
SYS_ISNS_P R11 0.01uF U4 IN_ISNS_P R4 0.01uF U2
8A = 800mV
4.99 1 INA213BIDCKR 4.99 1 INA213BIDCKR
2

2
GND GND

3.3V C25

System Current Sense Buffer 100nF

fc = 159Hz 6.3V SYS_IFLT
5

SYS_ISNS R14 3 GND

+
100k 1 SYS_IFLT
4
-
U6
2

C26 TLV9051IDBVR
10nF
16V

GND GND

Select Channel For MSP ADC

3.3V C30
SYS_IFLT R104
System Average Current Sense Buffer
fc = 0.159Hz 0
R105
100nF SYS_IAVG MSP_SYS_CURR
6.3V SYS_IAVG 0
5

SYS_ISNS R19 3 GND SYS_ISNS R106

+
100k 1 SYS_IAVG 0
4
-
U8
2

C32 TLV9051IDBVR
6.3V
10uF

GND GND

Figure 2-7. Current Sensing Schematic

There are also two current-sense buffers that are used to filter the system current rail. The buffer including
U6 includes a low-pass filter with a corner frequency of 159 Hz. This provides the MCU with an accurate
measurement of the system current while mitigating high-frequency noise. The buffer including U8 includes a
low-pass filter with a corner frequency of 0.159 Hz. This provides the MCU with an average current signal over
about 6 seconds.
The MCU only has one ADC pin available for current sensing so a 0-Ω resistor was added in series with each
of these outputs to provide the ability to manually select between which current sense output is delivered to the
MCU.

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2.2.19 Voltage Sensing

There are three voltage dividers in the system that allow the MCU to monitor V_SYS, VIN_FLT, and PS_ID. The
V_SYS and VIN_FLT dividers output a scaled voltage based on the input to the dividers. Figure 2-8 shows the
scaled voltage. All three of the dividers also include a Schottky barrier diode to provide overvoltage protection to
the MCU.
3.3V
3.3V

R5

2
100k
D3
PS_ID 3 BAS40-04-7-F

R85

1
17.8k

GND GND

V_SYS VIN_FLT
19.2V = 2.90V
3.3V 3.3V
19.2V = 2.05V 16.8V = 2.54V
16.8V = 1.79V 12.0V = 1.81V
12.0V = 1.28V R15 10.0V = 1.51V R96
2

2
22.6k 100k
D2 D4
SYS_VSNS 3 BAS40-04-7-F IN_VSNS 3 BAS40-04-7-F

R17 R99
1

1
2.70k 17.8k

GND GND GND GND

Figure 2-8. Voltage Sensing Schematic

The PS_ID pin is made available here as well. This type of pin is commonly included in barrel jack input adapters
and provides a specific voltage based on the voltage and current capability of the adapter.

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2.2.20 Input Comparators

Two comparators are included to monitor VIN_FLT and PS_ID. These signals can be used to provide interrupt
generation for the MCU when a specific type of adapter has been inserted or if an input adapter voltage
threshold has been met. The TLV7031 nano-power, low-voltage comparator is used to provide a small footprint
and low power draw while waiting for input events. Because these devices are powered by the battery when no
input adapter is present, the ultra-low quiescent current of 315 nA is a key design feature.
Comparator for JACK PS_ID PIN

3.3V C16

100nF
6.3V
VH = 1.51V R16
VL = 1.47V 100k

2
U14 GND
PS_ID 4 TLV7031DPWR
Vcc 1 PS_ID_CMP TP10
5 Vee
TP_SM_1MM

3
R89
82.5k
GND
R95
3.57M
GND

Comparator for Input Voltage Detection

3.3V C157

100nF
6.3V
VH = 1.51V R97
VL = 1.47V 100k
2

U15 GND
IN_VSNS 4 TLV7031DPWR
Vcc 1 VIN_LOW TP11
5 Vee
TP_SM_1MM
3

R100
82.5k
GND
R101
3.57M
GND

Figure 2-9. Input Capacitor Schematic

The voltage setting and hysteresis for these comparators can be calculated and adjusted according to
Equation 7.

R100
VTH = VCC ×
R97 R101 + R100

R100 R101
VTL = VCC ×
R97 + R100 R101

82.5 kΩ
VTH = 3.3 V × = 1.51 V
100 kΩ 3.57 MΩ + 82.5 kΩ

82.5 kΩ 3.57 MΩ
VTL = 3.3 V × = 1.47 V (7)
100 kΩ + 82.5 kΩ 3.57 MΩ

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2.2.21 Software Flow Chart

Figure 2-10 illustrates the software flow chart.

Definition of Status Registers, device

addresses, register addresses, and variables

Declaration of I2C state machine and

functions needed to implement the I2C
drivers

Device initialization functions (GPIO, Clock,

UCB0, UCB1)
Enter polling loop while AC_Present

AC_Present = True?
I2C command from Host Interrupt Trigger Set variables to zero
and check which target devices are present
Poll every 5 s

Read relevant data from available

Execute Host command and update status
downstream devices.
registers
Update status registers
AC adapter insertion or removal

Convert requested charge data to

compatible format and write to charge
controllers
Enter/Exit Low Power Mode. This will pause
or restart the polling cycles

Write charging information to downstream

devices

Figure 2-10. Software Flow Chart

2.3 Highlighted Products

2.3.1 BQ25731
The BQ25731 is a synchronous buck-boost battery charge controller to charge a 1- to 5-cell battery from a
wide range of input sources including USB adapter, high voltage USB-C Power Delivery (PD) sources, and
traditional adapters. It offers a low component count, high efficiency solution for space constrained, 1- to 5-cell
battery charging applications. During power up, the charger sets the converter to a buck, boost, or buck-boost
configuration based on the input source and battery conditions. The charger seamlessly transits between the
buck, boost, and buck-boost operation modes without host control.
2.3.2 LM7480-Q1
The LM7480-Q1 ideal diode controller drives and controls external back to back N-channel MOSFETs to emulate
an ideal diode rectifier with power path ON and OFF control and overvoltage protection. The wide input supply
of 3 V to 65 V allows protection and control of 12-V and 24-V supply rails. An integrated ideal diode controller
(DGATE) drives the first MOSFET to replace a Schottky diode for reverse input protection and output voltage
holdup. With a second MOSFET in the power path the device allows load disconnect (ON and OFF control)
and overvoltage protection using HGATE control. The device features an adjustable overvoltage cutoff protection
feature.

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2.3.3 LM74700-Q1
The LM74700-Q1 is an automotive AEC Q100 qualified ideal diode controller which operates in conjunction with
an external N-channel MOSFET as an ideal diode rectifier for low-loss reverse polarity protection with a 20-mV
forward voltage drop. The wide supply input range of 3.2 V to 65 V allows control of many popular DC bus
voltages such as 12-V and 24-V battery systems. The device controls the GATE of the MOSFET to regulate the
forward voltage drop at 20 mV. The regulation scheme enables graceful turn off of the MOSFET during a reverse
current event and ensures zero DC reverse current flow. Fast response (< 0.75 µs) to Reverse Current Blocking
makes the device suitable for systems with output voltage holdup requirements during ISO7637 pulse testing as
well as power fail and input micro-short conditions.
2.3.4 MSP430FR2475
The MSP430FR247x microcontrollers (MCUs) are part of the MSP430™ MCU value line portfolio of ultra-low-
power low-cost devices for sensing and measurement applications. MSP430FR247x MCUs integrate a 12-bit
SAR ADC and one comparator. The MSP430FR247x MCUs support an extended temperature range from –40°C
up to 105°C, so higher temperature industrial applications can benefit from the FRAM data-logging capabilities
of the devices. The TI MSP430 family of low-power microcontrollers consists of devices with different sets of
peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is
optimized to achieve extended battery life in portable measurement applications. The MCU features a powerful
16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The
digitally controlled oscillator (DCO) allows the MCU to wake up from low-power modes to active mode in less
than 10 µs (typical).
2.3.5 PCA9546A
The PCA9546A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair
fans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels
can be selected, determined by the contents of the programmable control register. An active-low reset ( RESET)
input allows the PCA9546A to recover from a situation in which one of the downstream I2C buses is stuck in
a low state. Pulling RESET low resets the I2C state machine and causes all the channels to be deselected, as
does the internal power-on reset function. The pass gates of the switches are constructed such that the VCC pin
can be used to limit the maximum high voltage, which will be passed by the PCA9546A. This allows the use of
different bus voltages on each pair, so that 1.8-, 2.5-, or 3.3-V parts can communicate with 5-V parts without any
additional protection. External pullup resistors pull the bus up to the desired voltage level for each channel. All
I/O pins are 5.5-V tolerant.

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3 Hardware, Testing Requirements, and Test Results

The key performances of TIDA-010240 were tested in a TI lab, the equipment used, test processes, and results
are described in this section.
Table 3-1 lists the TIDA-010240 board connections.
Table 3-1. TIDA-010240 Board Connections
Connector Description
J1 Input Supply connector (VIN)
J2 Battery A power connector
J3 Battery B power connector
J4 MSPFET Programming header
J5-1 MSP-MUX SCL
J5-2 MSP-MUX SDA
J5-3 GND Connection
J7-1 Host-MSP SDA
J7-2 Host-MSP SCL
J7-3 GND Connection
J6-1 BQ25731 Device A SCL
J6-2 Battery Pack A SCL
J6-3 BQ25731 Device A SDA
J6-4 Battery Pack A SDA
J6-5 BQ25731 Device B SCL
J6-6 Battery Pack B SCL
J6-7 BQ25731 Device B SDA
J6-8 Battery Pack B SDA
J6-9 3.3-V Connection
J6-10 GND Connection
J8-1 VIN +
J8-2 3.3-V Buck Converter Supply
J8-3 VSYS +
J9-1 3.3-V Buck Converter Output
J9-2 System 3.3-V Rail
J9-3 MSPFET 3.3-V pin
J10 System Output Connector (VSYS)

3.1 Hardware Requirements

Table 3-2 shows the equipment used for testing.
Table 3-2. Equipment Used for Testing
Equipment Rating Description
DC Power Supply 12 V to 20 V, 8 A Power supply representing 19-V wall adapter input
Electronic Load (E-Load) 160 W Electronic load used to simulate the system load up to 160
W
Smart Batteries Up to 4S, 2P Li-ion Smart battery packs for charge, discharge and
communications testing
Oscilloscope Tektronix DPO 2024B
Multimeter Agilent 34401A
Logic Analyzer Logic analyzer used for communication monitor
USB2ANY USB2ANY device used for generating host commands

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3.2 Test Setup

Table 3-3 shows the connections to the TIDA-010240 board for testing.
Table 3-3. TIDA-010240 Board Connections for Testing
Connector Description
J1 Connected to DC Power supply (12 V to 20 V)
J2 Battery A + and – connections
J3 Battery B + and – connections
J10 Connected to > 160-W E-Load
J4 MSPFET Connected for software monitoring
J5-1 Logic Analyzer SCL monitoring downstream
J5-2 Logic Analyzer SDA monitoring downstream
J5-3 Logic Analyzer GND Connection
J7-1 Host-MSP SDA connection for USB2ANY
J7-2 Host-MSP SCL connection for USB2ANY
J7-3 GND Connection for USB2ANY
J6-1 BQ25731 Device A SCL
J6-2 Battery Pack A SCL
J6-3 BQ25731 Device A SDA
J6-4 Battery Pack A SDA
J6-5 BQ25731 Device B SCL
J6-6 Battery Pack B SCL
J6-7 BQ25731 Device B SDA
J6-8 Battery Pack B SDA
J8 J8-2 jumper to J8-3. Ties VSYS to 3.3-V buck input
J9 J9-1 jumper to J9-2. Ties 3.3-V buck to 3.3-V system rail

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3.3 Test Results

This section describes the test procedures used to verify the functionality of this design. Test results for Charge
Current Limiting, Battery ORRing, and Adapter or Battery Switchover are shown, and the procedures used
during the testing are discussed.
All tests run in this section follow the connections in Table 3-3, unless otherwise stated.
3.3.1 Adaptive Charge Current Limiting
The reference design has an ILIM circuit used for limiting the total input current of the system to 8 A (described
in Section 2.2.11). The test detailed in this sections confirms the functionality of this adaptive current limiting
circuit.
For this test DMMs are connected in series with the positive terminals of both batteries to measure the charge
current of each. The system load current is set using the E-Load in CC mode. The input current is monitored
on the DC power supply input. The connected battery pack voltages are approximately 14.5 V. After setup, the
board is powered up with the 19-V supply.
Table 3-4. Adaptive Charge Current Limiting Data
Battery A Charge Battery B Charge
Input Current (A) System Current (A) ILIM Voltage
Current (A) Current (A)
5.38 0 3.00 2.99 1.54
5.79 1 2.60 2.78 1.46
6.11 2 2.24 2.40 1.34
6.75 4 1.52 1.63 1.26
7.39 6 0.75 0.80 1.13
8.09 8 0.00 0.00 0.99

3.3.2 Battery ORing System

This design discharges the batteries through ideal diodes. This results in a discharge current proportional to the
battery voltage until the batteries are discharged to an even voltage. Battery A measured 14.429 V and Battery B
measured 13.858 V at the beginning of the test. Multimeters were hooked up in series with the positive terminals
of the batteries to measure discharge current. The E-Load was set to draw a 5-A constant current from the
system rail (the DMMs used for testing were only rated for 3 A each).
Table 3-5. Battery ORing Data
Battery A Discharge Battery B Discharge
System Current (A) Battery A Voltage (V) Battery B Voltage (V)
Current (A) Current (A)
5 3.11 12.425 1.91 12.407
2 1.33 13.34 0.68 13.28

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3.3.3 Circuit Switchover From Adapter to Battery

This test is designed to demonstrate the adapter-to-battery switchover capabilities of the design. The test is run
with 19 V on the input supply. The E-Load is then connected to the system rail and draws a constant current
of 8 A. The input supply is then removed and the VIN, VSYS, and VBAT rails are monitored for the switchover
timings. The test is then repeated while replacing the 19-V input supply with a 13-V supply to mimic a car
charging adapter.
In Figure 3-1 through Figure 3-4, VIN is measured by CH1 (Blue), VBAT is measured by CH2 (Red) and, VSYS
is measured by CH3 (Green). For these captures all channels are based at 0 V with no offset to better illustrate
the switchover mechanism.
Figure 3-1 shows the 19 V to battery switchover with a time division of 200 μs. The minimum voltage at VSYS is
9.21 V. The approximate switchover timing is 10 μs and the VSYS rail has increased to 12.87 V by 20 μs after
the switchover event.

Figure 3-1. 19 V to Battery Switchover 200-μs Time Division

Figure 3-2 shows the 19 V to battery switchover with a time division of 20 μs. The minimum voltage at VSYS is
9.28 V. The approximate switchover timing is 10 μs and the VSYS rail has increased to 11.82 V by 10 μs after
the switchover event.

Figure 3-2. 19 V to Battery Switchover 20-μs Time Division

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Figure 3-3 shows the 12 V to battery switchover with a time division of 100 μs. The minimum voltage at VSYS is
9.12 V. The approximate switchover timing is 10 μs and the VSYS rail has increased to 12.73 V by 20 μs after
the switchover event.

Figure 3-3. 12 V to Battery Switchover 10-μs Time Division

Figure 3-4 shows the 12 V to battery switchover with a time division of 20 μs. The minimum voltage at VSYS is
9.31 V. The approximate switchover timing is 10 μs and the VSYS rail has increased to 10.63 V by 10 μs after
the switchover event.

Figure 3-4. 12 V to Battery Switchover 20-μs Time Division

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4 Design and Documentation Support

4.1 Design Files

4.1.1 Schematics
To download the schematics, see the design files at TIDA-010240.
4.1.2 BOM
To download the bill of materials (BOM), see the design files at TIDA-010240.
4.2 Documentation Support

1. Texas Instruments, BQ25731 I2C 1- to 5-Cell Buck-Boost Battery Charge Controller with USB-C PD 3.0
OTG Output data sheet
2. Texas Instruments, LM7480-Q1 Ideal Diode Controller with Load Dump Protection data sheet
3. Texas Instruments, LM74700-Q1 Low IQ Reverse Battery Protection Ideal Diode Controller data sheet
4. Texas Instruments, MSP430FR247x Mixed-Signal Microcontrollers data sheet
5. Texas Instruments, PCA9546A Low Voltage 4-Channel I2C and SMBus Switch with Reset Function data
sheet
4.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
4.4 Trademarks
TI E2E™ and MSP430™, and are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.

5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (June 2022) to Revision A (June 2022) Page

• Removed text in the System Overview section.................................................................................................. 2

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