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VLSI Verification Methodologies: Digital Assignment - 1

The document outlines the verification of the I2C Master-Slave protocol, detailing the inputs and outputs for both the Master and Slave modules. It describes the objectives of verification, including checking start/stop conditions and error handling, and presents a Directed Testbench Verification Methodology with various test scenarios. The verification environment includes components like a testbench top, clocking and reset block, and a scoreboard for data comparison.

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Satyadeep K
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16 views5 pages

VLSI Verification Methodologies: Digital Assignment - 1

The document outlines the verification of the I2C Master-Slave protocol, detailing the inputs and outputs for both the Master and Slave modules. It describes the objectives of verification, including checking start/stop conditions and error handling, and presents a Directed Testbench Verification Methodology with various test scenarios. The verification environment includes components like a testbench top, clocking and reset block, and a scoreboard for data comparison.

Uploaded by

Satyadeep K
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSI Verification Methodologies

Digital Assignment – 1

Topic:
I2C Master-Slave Protocol Verification

Submitted By:
Shreyas Joshi - 24MVD0097
Satya Deep K - 24MVD0093

Submitted to:
Dr. Jayakrishnan P.
I2C Master Module:

Inputs:
1. clk - Clock signal
2. rst - Reset signal
3. Host Interface (Commands & Data):
− address[6:0] - I2C slave address
− start - Start condition
− read - Read operation
− write - Write operation
− write_multiple - Multiple write mode
− stop - Stop condition
− valid - Command valid signal
− data_tdata[7:0] - Data to send
− data_tvalid - Data valid signal
− data_tlast - End of transaction indicator
− data_tready - Ready to receive data
4. I2C Interface (From Bus):
− scl_i - Serial clock input
− sda_i - Serial data input
5. Configuration Inputs:
− prescale[15:0] - Clock prescaler
− stop_on_idle - Stop transaction on idle

Outputs:

1. Host Interface:
− ready - Command ready signal
− data_tready - Ready to accept data
− data_tdata[7:0] - Received data
− data_tvalid - Data valid signal
− data_tlast - End of received transaction
2. I2C Interface (To Bus)
− scl_o - Serial clock output
− sda_o - Serial data output
3. Status Signals
− busy - I2C master busy flag
− bus_control - Master controlling the bus
− bus_active - Bus is active
− missed_ack - Acknowledgment missing

I2C Slave Module:


Inputs:
1. clk - Clock signal
2. rst - Reset signal
3. Host Interface (Commands & Data):
− release_bus - Release control of the bus
− data_tdata[7:0] - Data to transmit
− data_tvalid - Data valid signal
− data_tlast - End of transaction indicator
− data_tready - Ready to receive data
4. I2C Interface (From Bus):
− scl_i - Serial clock input
− sda_i - Serial data input
5. Configuration Inputs:
− enable - Enable slave operation
− device_address[6:0] - I2C slave address
− device_address_mask[6:0] - Mask for address matching

Outputs:

1. Host Interface:
− data_tready - Ready to accept data
− data_tdata[7:0] - Received data
− data_tvalid - Data valid signal
− data_tlast - End of received transaction
2. I2C Interface (To Bus):
− scl_o - Serial clock output
− sda_o - Serial data output
3. Status Signals:
− busy - I2C slave busy flag
− bus_address[6:0] - Current address on the bus
− bus_addressed - Slave has been addressed
− bus_active - I2C bus is active
Verifying the I2C Master and I2C Slave modules
Objectives:
• To check I2C Master start and stop conditions, address, read and write operations.
• To check I2C Slave response to addresses, acknowledge receipts, and read and
write handling.
• To verify whether Error like missed ACK signal is handled properly.

We will use Directed Testbench Verification Methodology with multiple test cases to
accomplish the above the objectives.

Verification Environment:
Testbench Layout Description
Testbench top Will instantiate the I2C Master and I2C Slave modules
Clocking and Reset block To generate system clock and reset signals
Monitor block transactions on SCL and SDA will be observed.
Scoreboard (with reference Compares expected vs. actual data for verification
model if available)
Generator Sends different I2C transactions (Read, Write, Start,
Stop, etc.)
Transactions/Mailboxes To hold the transactions between the DUT and
Testbench
Interface For test driver and DUT communication.

Test Scenarios:
We will be testing the design for the below tests:
• Primary Tests:
− Clock & Reset - to check if clk and rst work correctly.
− Bus Idle Check - to ensure I2C lines (scl_i, sda_i) are high when idle.
− Start/Stop Condition - to verify correct generation of Start & Stop conditions.
− Read & Write Test - to test write and read a single byte correctly
• Functional Tests:
− Read or Write - Test multiple byte transfers with/without repeated start
− Address Handling - Check master sending various addresses, slave responding
correctly.
• Error Handling:
− ACK Handling - Simulate slave not acknowledging a transaction.

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