Digital Logic Design

Sequential Circuits

Dr. Basem ElHalawany

Combinational vs Sequential
inputs X Combinational outputs Z
Circuits

A combinational circuit:
• At any time, outputs depends only on inputs
• Changing inputs changes outputs
• No regard for previous inputs
• No memory (history)
Combinational vs Sequential
inputs X Combinational outputs Z
Circuits
present state next state
Memory

A sequential circuit:
• A combinational circuit with feedback through memory
• The stored information at any time defines a state
• Outputs depends on inputs and previous inputs
• Previous inputs are stored as binary information into memory
• Next state depends on inputs and present state
Types of Sequential Circuits
• Two types of sequential circuits:
• Synchronous: The behavior of the circuit
depends on the input signal at discrete
instances of time (also called clocked)
• Asynchronous: The behavior of the circuit
depends on the input signals at any instance
of time and the order of the inputs change
• A combinational circuit with feedback
Synchronous Sequential Circuits
inputs X Combinational outputs Z
Circuits
present state next state
Flip-Flops

clock

• Synchronous circuits employs a synchronizing signal called clock

(a periodic train of pulses; 0s and 1s)
• A clock determines when computational activities occur
• Other signals determines what changes will occur
Synchronous Sequential Circuits
inputs X Combinational outputs Z
Circuits
present state next state
Flip-Flops

clock

• The storage elements (memory) used in clocked sequential

circuits are called flip-flops
• Each flip-flop can store one bit of information 0,1
• A circuit may use many flip-flops; together they define the circuit state

• Flip-Flops (memory/state) update only with the clock

Storage Elements (Memory)
• A storage element can maintain a binary state (0,1)
indefinitely, until directed by an input signal to switch state
• Main difference between storage elements:
• Number of inputs they have
• How the inputs affect the binary state
• Two main types:
• Latches (level-sensitive)
• Flip-Flops (edge-sensitive)
• Latches are useful in asynchronous sequential circuits
• Flip-Flips are built with latches
Latches
• A latch is binary storage element
• Can store a 0 or 1
• The most basic memory
• Easy to build
• Built with gates (NORs, NANDs, NOT)
SR Latch (Active High)
SR Latch (Active High)

• Two states: Set (Q = 1) and Reset (Q = 0)

• When S=R=0, Q remains the same, S=R=1 is not allowed!
• Normally, S=R=0 unless the state need to be changed (memory?)
• State of the circuit depends not only on the current inputs, but also
on the recent history of the inputs
S’ R’ Latch (Active Low)
S’ R’ Latch (Active Low)

• Similar to SR latch (complemented)

• When S=R=1, Q remains the same
• S=R=0 is not allowed!
SR Latch with Clock

• An SR Latch can be modified to control when it changes

• An additional input signal Clock (C)
• When C=0, the S and R inputs have no effect on the latch
• When C=1, the inputs affect the state of the latch and
possibly the output
How can we eliminate the undefined state?
D Latch
S • Ensure S and R are never
equal to 1 at the same
time
• Add inverter
• Only one input (D)
R • D connects to S
• D’ connects to R
• D stands for data
• Output follows the input
when C = 1
• Transparent
• When C = 0, Q remains
the same
Graphic Symbols for Latches

clk

• A latch is designated by a rectangular block with inputs on the left and

outputs on the right
• One output designates the normal output, the other (with the bubble)
designates the complement
• For S’R’ (SR built with NANDs), bubbles added to the input
 Problem with Latches
• A latch is a level sensitive device.
• Problem: A latch is transparent; state keep changing as
long as the clock remains active
• Due to this uncertainty, latches can not be reliably used
as storage elements.
Flip Flops
• A flip-flop is a one bit memory similar to latches
• Solves the issue of latch transparency
• Latches are level sensitive memory element
• Active when the clock = 1 (whole duration)
• Flip-Flops are edge-triggered or edge-sensitive
memory element
• Active only at transitions; i.e. either from 0  1 or 1  0
level

positive (rising) edge negative (falling) edge

Flip Flops

clk clk

• A flip flop can be built using two latches in a master-

slave configuration
• A master latch receives external inputs
• A slave latch receives inputs from the master latch
• Depending on the clock signal, only one latch is active at
any given time
• If clk=1, the master latch is enabled and the inputs are latched
• if clk=0, the master is disabled and the slave is activated to
generate the outputs
SR Flip Flop
• Built using two latches
(Master and Slave)
• C = 1, master is active
• C = 0, slave is active
• Q is sampled at the
falling edge
• Data is entered on the
rising edge of the clock
pulse, but the output
does not reflect the
change until the falling
edge of the clock pulse.
Graphic Symbols for Flip Flops

• A Flip Flop is designated by a rectangular block with inputs on the

left and outputs on the right (similar to latches)
• The clock is designated with an arrowhead
• A bubble designates a negative-edge triggered flip flops
 Other Flip Flops JK Flip Flop
• JK Flip Flop can be built with SR latches as shown
• Used to force the forbidden state SR =11 to produce a 4th allowed state
(Toggle/Complement)

• J sets the flip flop (1)

• K reset the flip flop (0)
• When J = K = 1, the output is complemented
Other Flip Flops
JK Flip Flop

• D = J Q’ + K’ Q
• J sets the flip flop (1)
• K reset the flip flop (0)
• When J = K = 1, the output is complemented
Other Flip Flops (cont.)
T Flip Flop

• T (toggle) flip flop is a complementing flip flop

• Built with a JK or D flip flop (as shown above)
• T = 0, no change,
• T = 1, complement (toggle)
• For D-FF implementation, D = T  Q
 Functional Table & Characteristic Table
• Tables that define the operation of a flip flop in a tabular form
•Next state is defined in terms of the current state and the inputs
• Q(t) refers to current state (before the clock arrives)
• Q(t+1) refers to next state (after the clock arrives)

• Example: (D Latch)

A characteristic equation defines the operation of a flip

flop in an algebraic form
 Functional Table & Characteristic Table
• JK
 Functional Table & Characteristic Table
• T
Direct Inputs

• Some flip-flops have asynchronous inputs to set/reset their states

independently of the clock.
• Preset or direct set, sets the flip-flop to 1
• Clear or direct reset, set the flip-flop to 0
• When power is turned on, a flip-flop state is unknown; Direct inputs are
useful to put in a known state
• Figure shows a positive-edge D-FF with active-low asynchronous
reset.
 Analysis & Design
of Synchronous Sequential
Circuits
Analysis of Sequential Circuits
• Analysis is describing what a given circuit will do
• The behavior of a clocked (synchronous) sequential
circuit is determined from the inputs, the output, and the
states of FF

Steps:
• Obtain state equations
• FF input equations
• Output equations
• Fill the state table
• Put all combinations of inputs and current states
• Fill the next state and output
• Draw the state diagram
Example 1
Analyze this circuit?
• Is this a sequential
circuit? Why?
• How many inputs?
• How many outputs?
• How many states?
• What type of
memory?
Example 1 (cont.)

D Flip Flop (review)

Characteristic Tables and Equations

Q(t) D Q(t+1)
0 0 0
D Q(t+1)
0 1 1
0 0 Q(t+1) = D
1 0 0
1 1
1 1 1
Example 1 (cont.)
State equations:
DA = AX + BX
DB = A’ X
Y = (A + B) X’
Substitute (to get N.S.):
A(t+1) = DA = AX + BX
B(t+1) = DB = A’ X

State table:
Example 1 (cont.)
State table (2D):
Example 1 (cont.)
State table: State diagram:
Example 2
Analyze this circuit?
• Is this a sequential
circuit? Why?
• How many inputs?
• How many outputs?
• How many states?
• What type of
memory?
Example 2 (cont.)

JK Flip Flop (review)

Characteristic Tables and Equations

J K Q(t+1)
0 0 Q(t)
0 1 0
Q(t+1) = JQ’ + K’Q
1 0 1
1 1 Q’(t)
Example 2 (cont.)
State equations:
JA = B, KA = B X’
JB = X’, KB = A  X
by substitution:
A = JAA’ + KA’A
= A’ B + A B’ + A X
B = B’ X’ + A B X + A’ B X’
Design of Synchronous
Sequential Circuits
• The design of a clocked sequential circuit starts
from a set of specifications and ends with a logic
diagram (Analysis reversed!)
• Building blocks: flip-flops, combinational logic
• Need to choose type and number of flip-flops
• Need to design combinational logic together with
flip-flops to produce the required behavior
• The combinational part is
• flip-flop input equations
• output equations
Design of Synchronous
Sequential Circuits
Design Procedure:
• Obtain a state diagram from the word description
• State reduction if necessary
• Obtain State Table
• State Assignment
• Choose type of flip-flops
• Use FF’s excitation table to complete the table
• Derive state equations
• Obtain the FF input equations and the output equations
• Use K-Maps
• Draw the circuit diagram
Example 1
Problem: Design of A 3-bit Counter
Design a circuit that counts in binary form as follows
000, 001, 010, … 111, 000, 001, …
Example 1 (cont.)
Step1: State Diagram

- The outputs = the states

- Where is the input?
Example 1 (cont.)
Step2: State Table

No need for state assignment

here
Example 1 (cont.)
Step2: State Table T–FF excitation table

We choose T-FF

0
Example 1 (cont.)
Step3: State Equations
Example 1 (cont.)
Step4: Draw Circuit

TA0 = 1
TA1 = A0
TA2 = A1A0
Excitation Table
D–FF excitation table
T–FF excitation table

JK–FF excitation table