Sequential

q Logic
g
‰ Combinational circuits: output is only a function of
current input values.
‰ Sequential circuits: outputs depend on not only current
Chapter 7. Designing Sequential input values, but also preceding input values. It remembers
L i Ci
Logic Circuits
i the histor
history of the ssystem.
stem

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

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Sequential Circuits Sequential Circuits

Sequential
q Logic
g Timing Metrics
‰ setup time (tsu): the time that data inputs (D) must be valid before clock transition
transition.
‰ Two storage mechanisms: ‰ hold time (thold): the time data input must remain valid after the clock edge.
9 Positive feedback ‰ propagation delay (tc-q): Data at D input is copied to Q output after a worst case
9 Charge based propagation delay (with reference to the clock edge)
edge).
‰ Registers: used to hold the system state
9 positive edge triggered
9 negative
ti edge
d ttriggered
i d clock
clock

Inputs
p Outputs
p tsu thold time
Combinational
Logic
Current Next In data
stable
State State
tcc-qq time

Out output output

clock stable
t bl stable
Block diagram of a finite-state machine (FSM)
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd time
Sequential Circuits Sequential Circuits
 Timing Metrics System Timing Constraint #1
‰ Why do we have setup time (tsu) and hold time (thold) requirements for ‰ Minimum clock period T required for proper operation of sequential
registers: If input data to register is not stable (e.g. there are glitches) before
circuit (due to requirement of setup time):
and after clock rising edge, it is very difficult to predict what input value (0 or 1)
p at clock rising
will be latched to output g edge.
g → Signalg uncertainty,
y, Not good!
g T ≥ tc-q + tplogic + tsu
Wh
Where: tplogic: worstt case propagation
ti delay
d l off th
the llogic
i
tcd: contamination delay, minimum propagation delay of logic
9 Reason: After current clock edge, the slowest signal for next state should
clock be stable at least tsu before next clock edge.
clock

tsu thold time

glitches (unstable)
In
Inputs Combinational Outputs
Logic
time Next
e t
Current
State State
Out output Output=??
(uncertain) T (clock period)
stable
t bl
time clock
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Sequential Circuits Sequential Circuits

System Timing Constraint #1 System Timing Constraint #2

‰ How to understand: T ≥ tc-q + tplogic + tsu ? ‰Timing requirement due to hold time of register:
‰ Example: Assume tc-q=10min, tplogic=45min, tsu=20min, first clock rising tcdreg + tcdlogic ≥ thold
edge arrives at 8am.If T=1hour, setup time requires next state should arrive Where: tcdreg: minimum propagation delay (contamination delay) of register.
register
i t iinputt 20 minutes
i t before
b f nextt clock
l k rising
i i edge
d (9(9:00am),
00 ) ii.e. b
before
f tcdlogic: minimum
i i propagation
ti ddelay
l ((contamination
t i ti d delay)
l ) off th
the
8:40am. However, due to delay (tc-q+tplogic=10+45=55min), next state arrives combinational logic.
register input at 8:55am. → too late. It violates setup time requirement. If 9 Reason: After current clock edge, the fastest signal for next state should
T>Tc-q+tplogic+tsu=75min, such violation will not occur. not arrive input D before thold to change current values of input D.

Inputs Combinational Outputs Inputs Outputs

8:55am Combinational
Logic
Next Logic
Current Current Nextt
N
State State State
8:10am 8am State
T (clock period)
T (clock period)
© Digital Integrated Circuits2nd
clock 8am 9am © Digital Integrated Circuits2nd clock
Sequential Circuits Sequential Circuits
 System Timing Constraint #2 Static vs Dynamic Storage
‰ How to understand: tcdreg + tcdlogic ≥ thold ?
‰ Assume tcdreg=10min, tcdlogic=15min, thold=30min, first clock rising edge ‰ Static storage
arrives at 8am. Hold time requires current register inputs stay unchanged
ƒ ppreserve state as long g as the p
power is on
until
til 8:30am.
8 30 H
However, signal
i l passes th
through
h register
i t and d combinational
bi ti l
logic, becomes next state and appears at register input at 8:25am, i.e., ƒ have positive feedback (regeneration) with an
new next-state will change the current register input value at 8:25am. → internal connection between the output and the input
too early, it violates hold time requirement!
ƒ useful when updates are infrequent (clock gating)
‰ Dynamic
y storage
g
ƒ store state on parasitic capacitors
ƒ only y hold state for short periods
p of time ((milliseconds))
Inputs Combinational Outputs ƒ require periodic refresh
Logic ƒ usually y simpler,
p , so higher
g speed
p and lower p power
Current N t
Next
State State
T (clock period)
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Sequential Circuits Sequential Circuits

Latches vs Flipflops
p p Sequential
q Definitions
‰ Latches (level-sensitive) ‰ Static versus dynamic storage
ƒ level sensitive circuit that passes inputs to Q when the ƒ static uses a bistable element with feedback (regeneration) and
clock
l k iis hi
high
h ((or llow)) - transparent
t t mode
d thus preserves its state as long as the power is on
ƒ input sampled on the falling (or rising) edge of clock is ƒ static is preferred when updates are infrequent (clock gating)
held stable when clock is low ((or high) g ) - hold mode ƒ dynamic stores state on parasitic capacitors so only holds the
‰ Flipflops (edge-triggered) state for a period of time (milliseconds) and requires periodic
ƒ edge sensitive circuits that sample the inputs on a clock refresh
transition ƒ dynamic is usually simpler (fewer transistors)
transistors), higher speed
speed, lower
– positive edge-triggered: 0 → 1 power
– negative
g edge-triggered:
g gg 1→0 ‰ Latch versus flipflop
ƒ built using latches (e.g., master-slave flipflops cascading ƒ latches are level sensitive with two modes: transparent - inputs
a positive and negative latch) are passed to Q, and hold - output stable.
ƒ fliplflops are edge sensitive that only sample the inputs on a clock
transition

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Sequential Circuits Sequential Circuits
 Latch versus Register Latches
‰ IIn our text:
t t ‰ Positive latch: transparent high - passes D input to Q
ƒ a latch is level sensitive
output when clock is high
ƒ a register is edge-triggered
‰ There are many different naming conventions
‰ Negative latch: transparent low - passes D input to Q
ƒ For instance, many books call edge-triggered elements flip-flops output when clock is low.
Positive Latch Negative Latch
ƒ This leads to confusion however
9 Register (positive edge-triggered):
9 Latch (positive): stores data In Out In Out
when clock is high (Clk=1) stores data when clock rises D Q D Q
G G
(
(Clk=0→1) )
CLK CLK
D Q D Q

Clk clk clk

Clk
In In
Clk Clk
Out Out
D D
Out Out Out Out
stable follows In stable follows In
Q Q
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Sequential Circuits Sequential Circuits

Characterizing Timing Latch--Based Design

Latch

tD 2 • N latch is transparent • P latch is transparent

Q
when φ = 0 when φ = 1
φ
D Q D Q

N P
Clk Clk Logic
Latch Latch

tC 2 Q tC 2 Q

Register Latch Logic

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Sequential Circuits Sequential Circuits
 Review: The Regenerative Property Bistable Circuits
Vi1 Vo1 Vi2 Vo2 ‰ The cross-coupling of two Vi1
inverters results in a
bistable circuit (a circuit with Vi2
two stable states)
cascaded inverters
‰ Have to be able to change the stored value by making A
A If the gain in the transient (or B) temporarily unstable by increasing the loop gain to
region is larger than 1, a value larger than 1
C
only A and B are stable z done by applying a trigger pulse at Vi1 or Vi2
operation points. C is a
z the width of the trigger pulse need be only a little larger than the
metastable operation total propagation delay around the loop circuit (twice the delay of
B point. an inverter)
Vi1 = Vo2
‰ T o approaches used
Two sed
‰ A bistable circuit has two stable states. In absence of any z cutting the feedback loop (mux based latch)
triggering,
gg g, the circuit remains in a single
g state and thus z overpowering the feedback loop (as used in SRAMs)
remembers a value.
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Sequential Circuits Sequential Circuits

Writing into a Static Latch MUX--Based Latches

MUX
‰ Change the stored value by cutting the feedback loop
Negative
g latch Positivee latch
Positi
Use the clock as a decoupling signal, (transparent when CLK= 0) (transparent when CLK= 1)
that distinguishes between the transparent and opaque states
CLK f db k
feedback feedback
CLK

Q D D Q
1 Q 0
CLK
CLK
D D 0 D 1

CLK
Forcing the state CLK CLK
Converting into a MUX (can implement as NMOS-only)
Q = Clk ⋅ Q + Clk ⋅ In Q = Clk ⋅ Q + Clk ⋅ In

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Sequential Circuits Sequential Circuits
 TG MUX Based Latch Implementation PT MUX Based Latch Implementation
‰ Positive latch based on transmission gate multiplexers: ‰ Multiplexer-based
M lti l b d NMOS llatch
t hb
by using
i NMOS
NMOS-onlyl pass ttransistors
i t
for multiplexers:
clk
9 Reduced clock load, but threshold drop at output of pass transistors
so reduced noise margins and performance.
Q 9 It also causes static power in 1st inverter, because maximum input
!clk g to inverter is VDD-VTn, and PMOS device of inverter is never
voltage
fully turned off.
D
input sampled input sampled
clk (transparent mode) (transparent mode)

clk !Q
clk clk
D Q
D Q
!clk !clk

clk feedback ! lk
!clk feedback
(hold mode) (hold mode)
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Sequential Circuits Sequential Circuits

Latch Race Problem Constructing Flip-

Flip-flop from Latches Using
‰ Signall race problem
Si bl off llatches:
t h If iinputt signal
i l kkeep changing
h i Master--Slave Two-
Master Two-stage Design
(e.g. glitches) when clk=1, it may cause uncertainty on the ‰ Edge-triggered flip-flops can be constructed by cascading two
signal
s g a be
beingg latched.
a c ed level-sensitive latches using master-slave two-stage design.
‰ Ex: Positive edge-triggered flip-flop by cascading 2 positive
B latches with opposite clocks
B B’ 9 When clk=0,
clk=0 master latch is transparent
transparent, QM=Q,
=Q but slave
stage is hold, QM cannot pass to Q;
9 When clk=0→1, master latch is hold, slave stage is

clk transparent, QM value latched at the end of clk=0 phase is

passed to Q, Q=QM|clk=0→1=D|clk=0→1→rising edge triggered.
9 When clk
clk=11, master latch is hold
hold, D cannot change QM and Q Q.
Which value of B is stored?
clk
Two-sided clock constraint
T ≥ tc-q + tplogic + tsu
Thigh < tc-q + tcdlogic
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Sequential Circuits Sequential Circuits
 Master Slave Based ET Flipflop MS ET Implementation
‰ Positive edge-triggered
edge triggered register with master-slave
master slave configuration: ‰ Master-slave positive edge-triggered register using multiplexers
cascading a negative latch (master) with a positive latch (slave). 9 When clk=0, T1: on, T2: off, D is sampled to QM, T3: off, T4: on, I5 and I6
9 When clk=0, master stage is transparent, D input is passed to QM, slave hold the state of slave latch.
stage is in hold mode
mode, keeping its previous value by feedback
feedback. 9 When clk=0→1,
clk 0 1 T1: off,
off T2: on,
on I2 and I3 hold state of QM. T3: on,
on T4: off,
off
9 When clk=0→1, master is hold, slave is transparent, QM remains the QM is copied to output Q.
value of D right before clock rising edge, and its value is passed to Q. Master Slave
9 QM is constant when clk=1 → Q makes only 1 transition per cycle.
cycle
D Q
I2 T2 I3 I5 T4 I6 Q
0 clock
QM
1 Q I1 I4 T3
1 clk D T1
D 0 QM
D clk
clk
clk
Slave
Master QM clk
clk = 0 transparent
p hold
! lk
!clk
clk = 0→1 hold transparent Q
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Sequential Circuits Sequential Circuits

MS ET Implementation Slave
MS ET Timing
g Properties
p
Master
‰ Assume propagation delays of inverter and TG are tpd_inv
and tpd_tx, that the contamination delay is 0, and that the
inverter delay to derive !clk is 0
I2 T2 I3 I5 T4 I6 Q ‰ Set-up time - time before rising edge of clk that D must be
QM valid
tsu=3 * tpd_inv + tpd_tx
I1 T1 I4 T3
D ‰ Propagation delay - time for QM to reach Q
tc-q=tpd_inv + tpd_tx
clk
‰ Hold time - time D must be stable after rising edge of clk -
thlod=0
master transparent master hold
slave hold slave
l t
transparent
t
clk

! lk
!clk
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Sequential Circuits Sequential Circuits
 Set--up Time Simulation
Set Set--up Time Simulation
Set
‰ PSPICE setset-up
up time simulation: we progressively skew the input with ‰ PSPICE setset-up
up time simulation: we progressively skew the iput with
respect to the clock edge until the circuit fails. respect to the clock edge until the circuit fails.
9 Case #1: skew=210ps: correct value of input D is sampled (Q remains 9 Case #2: skew=200ps: incorrect value of D propagates to Q (Q
at VDD)
VDD). changes to 0)0).
3
3
Q
2.5
25
2.5
tsetup = 0.21 ns
2 QM I2 out tsetup = 0.20 ns
2
1.5 D clk 1.5 D clk

Volts
Volts

1 Q
1

V
V

0.5 0.5
I2 out
0 0
QM
works correctly
-0.5 -0.5 fails
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
Time (ns) Time (ns)
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Sequential Circuits Sequential Circuits

Propagation Delay Simulation Reduced Load MS ET FF

‰ PSPICE propagation ti delay
d l simulation
i l ti ‰ Clock load per register is important since it directly impacts the
9 propagation delay: time from 50% point of CLK edge to 50% point of Q power dissipation of the clock network.
output ‰ Transmission-gate register design: clock load of 8 transistors
9 tc-q(lh)=160ps, tc-q(hl)=180ps. (ignoring inverters for clock)
3 ‰ Can reduce the clock load (at the cost of robustness) by
CLK making the circuit ratioed: eliminate feedback transmission
2.5
gate by directly cross-coupling the inverters.
2 clk !clk
tc-q(LH) = 160 p
psec
Q I1 I3
1.5 D QM
T1 T2 Q
Volts

D
1 tc-q(LH) tc-q(HL) = 180 psec
V

tc-q(HL) I2 I4
reverse
0.5 !clk clk conduction
z to switch the state of master, T1 must be sized to overpower the
0 feedback inverter I2 to switch the state of cross-coupled inverter.
-0.5 (I2: small W/L → larger Ron, weaker device).
0 0.5 1 1.5 2 2.5
z to avoid reverse conduction
conduction, I4 must be weaker than I1 (I4: small W/L,
W/L
Time (ns) larger Ron, weaker device).
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Sequential Circuits Sequential Circuits
 Master--slave Register based on NMOS-
Master NMOS-only Pass Transistors
Non--Ideal Clocks
Non
‰ Negative
N ti master-slave
t l ttwo-stage
t register
i t based
b d on NMOS
NMOS-only
l ‰ Clock skews come from
pass transistors and cascade-inverter latches: 9 delay for clk’ generated from clk,
9 When clk=1, P1 on, P2 off, P3 off, P4 on, X=D’, master stage on, 9 Variations in wires used to route clk and clk’,
slave stage off, Q remains its previous value, 9 load capacitance vary based on data in connecting latches.
9 When clk=1→0, P1 off, P2 on, P3 on, P4 off, master stage off, slave ‰ Non-ideal clocks:
g on, Q=X’=(D’)’=D|
stage ( ) |clk 1 0: falling-edge
g g triggered.
gg
clk=1→0 9 1-1 overlap
9 0-0 overlap

clk clk
X !clk Q
clk !clk !clk

P1 A P3 I3 I4 !Q
D I1 I2
Id l clocks
Ideal l k Non-ideal
Non ideal clocks
B clock skew
P2 P4
1-1 overlap
0-0 overlap
© Digital Integrated Circuits2nd !clk clk © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits

Example of Clock Skew Problems Pseudostatic Two-

Two-Phase ET FF
‰ Solution: use two nonoverlapping clocks (clk1 and clk2) instead of
‰ Problems
P bl caused
db by clock
l k overlap:
l
one clock and its inversion (clk and clk’).→No 1-1 overlap, no signal
9 Race condition – direct path from D to Q during the short time when
race. But during non-overlap time (0-0 overlap), FF is in high-
both clk and !clk are high (1-1 overlap). Output changes in both clock
impedance state: feedback loop is open
open, nodes A and B are floating
floating.
rising/falling edges instead of one edge. Further, value of output Q
Leakage will destroy the state if this condition holds for too long –
depends on whether input D arrives node X before or after falling edge
pseudostatic.
of clk’. clk1 X clk2 Q
9 Undefined state – both B and D are driving A when clk and !clk are
both high B I
D P1 A I1 I2 P3 3 I4 !Q
9 Dynamic storage – when clk and !clk are both low (0-0(0 0 overlap):
inputs of I1 and I3 are floating. B
P4
X P2
clk !clk Q
clk2 clk1
P1 A P3 I3 I4 !Q dynamic
D I1 I2 master transparent storage
slave hold
B
P2 P4 clk1 master hold
tnon_overlap
non overlap slave transparent
clk2
© Digital Integrated Circuits2nd !clk clk © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 Two Phase Clock Generator Overpowering Feedback Loop : Cross-
Cross-Coupled Pairs
‰ Traditional way to switch bistable element: overpower feedback loop loop.
‰ Circuit
Ci it ffor generating
ti ttwo-phase
h non-overlapping
l i clock
l k
‰ By keeping nonoverlap time tnon_overlap large enough so that no ‰ Static SR (set-reset) flip-flop: writing data by pure force. Cross-
overlap occurs even with clock-routing delays. coupled NOR gates, with the 2nd input of NOR gates connected to
trigger inputs (S and R) for forcing output Q and Q’Q to a given state
state.
A clk1 9 SR=00: cross-coupled inverter ((A+0)’=A’, NOR gate with input “0” is
Each gate has 1 like an inverter), Q and Q’ retain their values.
clk unit
it d
delay
l 9 SR=10:
SR 10 Q iis fforcedd tto 1,
1 Q’
Q’=0.
0
9 SR=01: Q is forced to 0, Q’=1.
B clk2 9 SR=11: QQ’=00, Q’ is not inversion of Q → forbidden state.

clk NOR-based set-reset

S R Q Q
A S
Q
S Q 0 0 Q Q
B 1 0 1 0
R Q
0 1 0 1
clk1 Q
R 1 1 0 0

clk2 Forbidden State

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Sequential Circuits Sequential Circuits

SR flip-
flip-flop: Cross
Cross--Coupled NAND 6 Transistor CMOS SR Latch
‰ Another SR flip-flop implementation: cross-coupled NAND structure ‰ Previous SR flip-flop: asynchronous.
‰ Static SR (set-reset) flip-flop based on cross-coupled NAND gates, ‰ Synchronous clocked 6-transistor CMOS SR latch: use clock for
with the 2nd input of NAND gates connected to trigger inputs (S and R
R, synchronous behavior
behavior.
active low) for forcing output Q and Q’ to a given state. 9 When clk=0: R and S are isolated from cross-coupled inverters, Q
9 SR=00: QQ’=11, Q’ is not inversion of Q → forbidden state. and Q’ remains their values.
9 SR=10: Q is forced to 0 0, Q’=1
Q =1. 9 When clk=0→1,
clk=0→1 S and R are connected to Q and Q’
Q.
9 SR=01: Q is forced to 1, Q’=0. - If SR=00: Q=0, Q’=0, forbidden.
9 SR=11: cross-coupled inverter ((A·0)’=A’, NAND gate with input “1” is - If SR=11: Q=1, Q’=1, forbidden.
lik an iinverter),
like t ) Q and d Q’ retain
t i th
their
i values.
l - If SR
SR=01:
01 QQ=0,
0 Q’
Q’=1,
1 clk
lk
- If SR=10: Q=1, Q’=0. clk M2 M4
Q M6
S
S R Q Q clk
lk !Q Q M5 !Q
S Forbidden State clk R
Q
S Q 0 0 1 1
R M1 M3
1 0 0 1 S
R Q
0 1 1 0
Q 1 1 Q Q
R

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Sequential Circuits Sequential Circuits
 Clocked ratioed CMOS SR Latch Ratioed CMOS Clocked SR Latch
‰ Clocked 6-transistor CMOS SR latch: S and R are applied to ‰ Clocked ratioed 8-transistor CMOS SR latch: working principle
source/drain terminals (low impedance nodes): not good. 9 Assume initial state: Q=1, Q’=0, now R=1, S=0, M1 is on, M5 is off,
‰ Clocked ratioed 8 8-transistor
transistor CMOS SR latch: R and S applied to but clk=0,, M6 and M8 are off,, R and S are disconnected to Q and Q’,,
gate terminals. It includes a cross-coupled inverter pair, plus 4 extra cross-coupled inverters M2,M1, M4, M3 retain their current state.
transistors to drive the flip-flop from one state to another, and to
provide synchronization.
synchronization (It’s
(It s not used in datapaths any more,
more but is a
basic building memory cell) VDD
‰ In steady state, one inverter off on
i hi
in high,
h while
hil th
the other
th one iis M2 M4 M2 M4
low. No static path between Vdd Q 1
Q
and Gnd, but tranistor sizing is Q 0 !Q
essential to ensure that flip-flop
off off
can transition from one state to CLK M6 M8 CLK 0 clk M6 M8 clk 0
the other when needed. M1 M3 M1 M3
on off
ff
M7 R1
S M5 M7 R 0 S M5
off on

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Sequential Circuits Sequential Circuits

Ratioed CMOS Clocked SR Latch Sizing Issues

‰ Clocked ratioed CMOS SR latch: working principle ‰ Sizing issues for SR flip
flip-flop:
flop:
9 Now if clk=0→1, M6 and M8 are off→on. Since M4, M7 and M8 are (a). DC output Q’ v.s. pull-down device size M5-6 (with W/L2=1.5µm/0.25µm).
on, they should be properly sized so that Q is brought below switching (b). Transient response showing that M5 and M6 must each have W/L larger
th h ld off iinverter
threshold t M2/M1
M2/M1, so that
th t Q’=0→1,
Q’ 0 1 which
hi h iin tturn causes th 3 tto switch
than it h SR fli
flip-flop
fl
inverter M4/M3 to switch state, Q=1→0. Finally: Q=0, Q’=1. 2.0 3
Q S

1.5
2 W = 0.5 μ m
off → on on → off

Q (Vollts)
0 6μ m
W = 0.6

Volts
ts
M2 M4 1.0
1 →0 W = 0.7 μ m
Q
1← 0 1
!Q 05
0.5 0 8μ m
W = 0.8
off->on off->on W = 0.9 μ m
0 → 1 clk M6 M8 clk 0 → 1 W = 1μ m
M1 M3 0.0 0
on → off
ff ff → on
off 20
2.0 25
2.5 3.0
3 0 35
3.5 40
4.0 0 0.2
0 2 0.4
0 4 0.6
0 6 0.8
0 8 1 1.21 2 1.4
1 4 1.6
1 6 1.8
18 2
M7 R1
0 S M5
off on
W/L 5 and 6 time (ns)
(a) (b)
Output voltage dependence T
Transient
i t response (L=0.25µm)
(L 0 25 )
on transistor width
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 Storage Mechanisms Dynamic ET Flipflop
‰ Static storage: cross-coupled
cross coupled inverter pair forming a bistable element.
element ‰ Dynamic TG positive edge
edge-triggered
triggered register (8 transistors):
A stored value remains valid as long as supply voltage is applied. 9 When clk=0, T1 is on, T2 is off, master stage transparent, input D is
‰ Dynamic storage: utilize charge stored on capacitor to represent logic sampled to storage node 1, slave stage is hold, node 2 is floating.
signal (absence:
( 0, presence: 1).
) Due to charge leakage, periodic 9 When clk=0→1, T1 on→off, ff T2 off→on,
ff master stage is hold, slave
refreshing is needed to maintain the signal. stage is transparent, the value sampled on node 1 before clock rising
edge propagates to output Q.
master slave
!clk clk
CLK
CLK
Node 1 QM Node 2
D T1 I1 T2 I2 Q
Q
D Q
CLK C1 C2
clk !clk
D
CLK master
aste ttransparent
a spa e t
slave hold clk
CLK
master hold
Static Dynamic (charge-based) !clk
slave transparent
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Sequential Circuits Sequential Circuits

Dynamic ET Flipflop Dynamic ET Flipflop

‰ Question: Why do we need two inverters? Can we remove them? ‰ setup time: tsu=tpd_tx
‰ Answer: No. If two inverters are removed, when T1 is off, both nodes ‰ hold time: thold=0
1 and 2 are floating. We only rely on charge stored in capacitors C1 and ‰ppropagation
p g delayy tc-q=2tpd_inv
pd inv+ tpd_tx
pd tx
C2 to maintain them to be “1”,
“ which is very weak. Iff V(D)=5V,
( ) C1=CC2,
when clk=0→1, we expect V(Q)=“1”=5V, but due to charge sharing,
V(Q)=2.5V. Further, due to charge leakage, V(Q) is keep dropping.
t
master slave
l
master slave
Removing both !clk clk
!clk clk
inverters: bad
QM
design! Node 1 QM Node 2 D T1 I1 T2 I2 Q
D T1 T2 Q
C1 C2
C1 C2
clk !clk
clk !clk master transparent
master
t transparent
t t slave hold
slave hold clk clk
master hold
!clk ! lk
!clk master hold
slave transparent
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd slave transparent
Sequential Circuits Sequential Circuits
 Dynamic ET FF Race Conditions Dynamic Two-
Two-Phase ET FF
‰ Clock overlap causes race problem for dynamic edge edge-triggered
triggered flip
flip- ‰ Solution #1 to race problem: use two-phase nonoverlap clocks (clk1
flop: and clk2) instead of only one clock and its inversion (clk and clk’).
9 0-0 overlap: both PMOS of T1 and PMOS of T2 are simultaneously 9 No 1-1 overlap between clk1 and clk2: T1 and T2 will never be
on, creating a direct path for
f data to flow
f from
f D input to Q output. simultaneously onon, no race problem
problem.
9 1-1 overlap: both NMOS of T1 and NMOS of T2 are simultaneously 9 0-0 overlap between clk1 and clk2: both T1 and T2 are off, nodes A
on, creating a direct path for data to flow from D input to Q output. and B are floating, but no race issue.
!clk clk clk1
lk1 clk2
lk2

A QM B
QM D T1 I1 T2 I2 Q
D T1 I1 T2 I2 Q
C1 C2
C C !clk1 !clk2
1 2 master transparent
clk !clk
slave hold
0-0 overlap race condition
clk
lk toverlap0-0 < tT1 +tI1 + tT2 clk1
lk1
tnon_overlap
!clk
1-1 overlap p race condition clk2
toverlap1-1 < thold master hold
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd slave transparent
Sequential Circuits Sequential Circuits

Making a Dynamic Latch Pseudo-

Pseudo-Static Other Latches/Registers: C2MOS
‰ Robustness considerations limit the use of dynamic FF’s ‰ Positive C2MOS (clocked CMOS) ‰ Negative C2MOS (clocked
ƒ coupling between signal nets and internal storage nodes can latch: CMOS) latch:
j
inject significant
g noise and destroy y the FF state 9 When clk=0: M7,M8 are off, Q is 9 When clk=1: M3,M4 are off, Q is
ƒ leakage currents cause state to leak away with time floating, latch in hold mode. fl ti
floating, llatch
t h iin h
hold
ld mode.
d
ƒ internal dynamic nodes don’t track fluctuations in VDD that 9 When clk=1: M7, M8 are on, 9 When clk=0: M3, M4 are on,
reduces noise margins Q=D’, latch is in transparent Q=D’, latch is in transparent
‰ A simple fix is to make the circuit pseudostatic by adding a weak mode. VDD mode. VDD

feedback inverter. → Node X is driven by the output of an inverter, it

M6 M2
will never be floating again
again. slightly increase the delay
delay, but
improves the noise immunity significantly.
!clk CLK M8 CLK M4
Q Q
D D
X
D CLK M7 CLK M3

M5 M1
clk
‰ Add above logic (weak feedback inverter) to all dynamic
Positive C2MOS latch Negative C2MOS latch
latches
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 C2MOS (Clocked CMOS) ET Flipflop C2MOS (Clocked CMOS) ET Flipflop
‰ C2MOS (clocked CMOS) positive edge-triggered flipflop:
clock-skew insensitive, an ingenious master-slave
VDD VDD register insensitive to clock overlap (8-transistors).
Master Slave
M2 M6
M2 M6
CLK M4 CLK M8
X clk M4 !clk M8
D Q QM
CL1 CL2 D Q
CLK M3 CLK M7
!clk M3 CL1 clk M7 CL2

M1 M5
M1 M5

Master Stage Slave Stage

clk

“Keepers”
Keepers can be added to make circuit pseudo
pseudo-static
static !clk

© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd

Sequential Circuits Sequential Circuits

‰
C2MOS (Clocked CMOS) ET Flipflop
Working g principle: operates in two phases ((positive edge-triggered
g gg register).
g )
C2MOS FF 0-
0-0 Overlap Case
‰ C2MOS register with clk-clk
clk-clk’ clocking is insensitive to clock overlap
9 clk=0: M3, M4 on; M7, M8 off, master stage acts as inverter, QM=D’ (evaluation); as long as rise and fall times of clock edges are sufficiently small.
slave stage in high-impedance (hold), Q remains previous value stored on CL2.
‰ Ex: For (0-0) clock overlap, M3 M7 are off, M4 M8 are on. If D=1, M2
9 clk=1: master stage in hold mode, slave stage evaluates, Q=QM’, value stored
in CL1 propagates to Q. is off
off, D cannot pass to QM. If D=0
D=0, QM=1,
=1 but M6 is off
off, Q is floating,
floating
Master Slave QM cannot pass to Q. Thus D cannot pass to Q during (0-0) overlap.
M2 M6
M2 M6
clk Mon !clk Moff
4
QM on 8 0 M4 0 M8
off Q QM
D Q
D
!clk Mon CL1 clk Moff CL2
3
on 7 C1 C2
off
M1 M5
M1 M5
master transparent
0-0 overlap: clk=clk’=0
slave hold
clk
clk clk
!clk master hold
!clk
!clk
slave transparent
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 CEx:2MOS FFoverlap,
1-1MOverlap
1- Case C2MOS Transient Response
‰ For (1-1) clock overlap M are off
off, M M are on
on. If D=0
D=0, M is off
off, D ‰ In sum,, C2MOS register
g is insensitive to clock overlaps
p because overlaps p
4 8 3 7 1
cannot pass to QM. If D=1, QM=0, but M5 is off, Q is floating, QM cannot pass activate either pull-up or pull-down networks of latches, but never both of
to Q. Thus D cannot pass to Q during (1-1) overlap. them simultaneously.
‰ However right after overlap
However, overlap, clk’=0
clk 0 and M8 is onon, QM=0 0 propagates to QQ. → ‰ However, if tr and tf of clock is large
g ((slow clocks),) there exists a time slot
Not good. Solution: 1-1 overlap constraint: toverlap1-1 < thold (data D should be where both NMOS and PMOS are on. → Both master and slave stages are
stable during overlap period). on, Input can directly go to output → signal race condition.
3
M2 M6
2.5 For a
QM(3) 0.1 ns clock: no
QM 2 Q(3) race
D Q
1 M3 C1 1 M7 C2 1.5
Q(0.1)
( )
1
M1 M5 clk(0.1)
1-1 overlap: clk=clk’=1 0.5
For a
clk(3) 3 ns clock
clk clk 0 (race condition
exists)
!clk !clk -0 5
-0.5
0 2 4 6 8
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd Time (nsec)
Sequential Circuits Sequential Circuits

Other Latches/Registers: TSPC True Single Phase Clocked (TSPC) Latches

‰ Two-phase clocked latches: clock overlap may cause race and floating
node
d problem.
bl
‰ True single-phase clocked (TSPC) latches: use only a single clock, never
have clock overlap, no need to worry about clock overlap problem.
‰ Negative true single-phase latch: when clk=0, two cascaded inverters, VDD VDD VDD VDD
Q=In (non-inverting), transparent mode; when clk=1, both inverters are
disabled: hold mode.
‰ Positive true single-phase latch: when clk=1, two cascaded inverters, Out
Q=In (non-inverting), transparent mode; when clk=0, both inverters are
disabled: hold mode
mode. In CLK CLK In CLK CLK
Negative true single-phase latch Positive true single-phase latch Out

clk clk Q
In In clk clk
Q
Positive latch (6 transistors) Negative latch (6 transistors)
(transparent when CLK= 1) (transparent when CLK= 0)
hold when clk = 1 transparent when clk = 1
transparent when clk = 0 hold when clk = 0
© Digital Integrated Circuits
2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 Embedding Logic in TSPC Latch TSPC - True Single Phase Clock Logic
‰ TSPC latch offers possibility of embedding logic functionality into ‰ TSPC – True Single Phase Clock Logic
latches.→ reduce delay overhead due to latches. 9 Virtually no design constrains: no even-inversion
‰ Ex: AND latch. Instead of implement it as “CMOS NAND + CMOS constrains between 2 latches or between a latch and a
inverter + positive TSPC latch”, we can implement it as “AND latch”. dynamic block. Dynamic and static circuits can mix freely.
9 When clk=0, hold mode, Q remains its current value,
9 Logic functions can be included in negative TSPC or
9 When clk
clk=1,
1, transparent mode, Q=X’=((AB)’)’=AB
Q X ((AB) ) AB
positive TSPC
S C latches, or placed between them.
9Disadvantage: more transistors per latch (6 instead of 4)
VD D VDD VDD VDD
PUN A B
PUN
Q X Q
In In
clk clk clk clk Static
φ φ φ φ
Logic Out
A
PDN PDN
B
Including logic into latch AND latch (positive) Including logic into Inserting logic between
© Digital Integrated Circuits2nd © Digital Integrated Circuits2ndthe latch latches
Sequential Circuits Sequential Circuits

True Single Phase Clocked Registers (TSPCR) TSPC ETtriggered

FF TSPCR: negative latch + positive latch
‰ True single-phase
single phase clocked registers (TSPCR) can be constructed by ‰ Positive edge
edge-triggered
cascading positive and negative TSPC latches (12 transistors). 9 When clk=0, master stage is transparent, QM=In; slave stage is hold,
‰ Positive edge-triggered TSPCR: negative latch + positive latch 9 When clk=0→1, master stage hold, slave stage transparent, Q=QM,
9 Wh clk=0,
When lk 0 master
t stage
t is
i ttransparent,
t QM=In;
I slave
l stage
t is
i hold,
h ld QM value
l iis passed
d tto Q
Q: positive
iti edge-triggered.
d ti d
9 When clk=0→1, master stage hold, slave stage transparent, Q=QM, ‰ TSPC latch is dynamic: when latch in hold mode, output may be
QM value is passed to Q: positive edge-triggered. floating. → vulnerable to signal coupling and charge sharing.
‰ TSPC latch is dynamic: when latch in hold mode, output may be Master Slave
floating. → vulnerable to signal coupling and charge sharing.
Master stage Slave stage
clk on clk on on on Q
D off off QM off
cclk off cclk
clk clk Q
In QM
clk clk
master transparent
slave hold
hold when clk = 1 transparent when clk = 1 master hold
clk
lk slave transparent
transparent when clk = 0 hold when clk = 0
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 Simplified TSPC ET FF Simplified
p TSPC ET FF
‰ Simplified
Si lifi d positive
iti edge-triggered
d ti d TSPCR (9 ttransistors):
i t ) replace
l ‰ Working principle of simplified positive edge-triggered TSPCR:
the 2 intermediate clocked inverters with a dynamic Φn inverter.
9 When clk=0, X=D’, Φn inverter in precharge phase, QM=1, M8 M9
off, Q’ floating, Q remain its current value → hold mode.
9 When clk=0→1, 1st clocked inverter is off, Φn inverter evaluates,
QM=X’,, 2nd clocked inverter is on,, Q’=Q
Q QM’=D’(rising-edge),
( g g ), off
M3
on clk M9 M6
Q=D(rising-edge). → Positive edge-triggered register.
QM→ 1→ D
Q→ D
D clk M2on X→ !D clk off
off M5 on M8
M3 clk M6 M9
Q’ M1 clk Moff M7
QM on 4
Q
D clk
lk M2 X clk
M5 M8
master transparent
M1 clk M4 M7 slave hold
master hold
clk slave transparent
clk
lk
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits

Sizing Issues in Simplified TSPC ET FF Split--Output TSPC Latches

Split
‰ Transistor sizing is critical for achieving correct functionality in TSPC ‰ TSPC
S C latches can be ffurther simplifiedf to 5-transistor design,
register.
also called split-output TSPC latches.
‰ With improper sizing, glitches may occur at output due to race
condition
diti when
h clk lk transitions
t iti from
f 0 to
t 1.
1 9 only the first inverter is controlled by clock.
3 9 clock load is reduced by half.
‰ Ex: positive split-output TSPC latch.
clk 9 Wh clk=0,
When lk 0 Q is i floating,
fl ti hold
h ld mode;
d
!Qmod Transistor sizing
9 when clk=1, two cascaded inverters, Q=In, transparent mode.
2 !Qorig
Original width Positive Latch (5 transistors) Negative Latch (5 transistors)

Q=0 M4, M5 = 0.5μm

M7, M8 = 2μm Q A
1
In clk In clk
Qorig A
Modified width Q
M4, M5 = 1μm
0
Qmod M7, M8 = 1μm
0 0.2 0.4 0.6 0.8 1 transparent when clk = 1 hold when clk = 1
Time (nsec) hold when clk = 0 transparent when clk = 0
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 Split--Output TSPC Latches
Split Split
Split-
p -Output
p TSPC ET FF
‰ Problem off split-output TSPC
S C latches: not all node voltages in ‰ Split-output TSPC register: cascading positive and negative split-out
latch experience full logic swing. TSPC latches, but further share one inverter in between.
9 For ppositive split-output
p p TSPC latch: When In=0,, clk=1,, VA=1,, but ‰ Ex: p
positive split-output
p p TSPCR.
VA_max=VDD-VTn, Otherwise, NMOS for clk is off. 9 When clk=0, 1st inverter is on (transparent), A=D’, 2nd inverter is off
9 For negative slpit-output TSPC latch: When In=1, clk=0, VB=0, but (hold), QM floating, Q’ and Q remains previous state,
VB_min
B i =|V|VTp
T |,
| otherwise,
otherwise PMOS for clk is off
off. 9 When clk
clk=0→1
0→1, 1st inverter is off(hold)
off(hold), 2nd and 3rd inverters are on
(transparent), QM=A’, Q’=QM’=A=D’(rising-edge), Q=D(rising-
Negative Latch edge)→positive edge-triggered register.
Positive Latch

A
Q B clk
In clk In clk D clk QM Q’
A Q Q

transparent
p when clk = 1 hold when clk = 1
hold when clk = 0 transparent when clk = 0 clk
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits

Master--Slave Flip-
Master Flip-flops Optional: Pulse-
Pulse-Triggered Latches
‰ Master-slave
Master slave flip
flip-flops
VDD
flops implemented with TSPC
VDD VDD VDD VDD VD D
An
A Alternative
Alt ti Approach
A h
φ φ
Y
D X
D D Ways to design an edge-triggered sequential cell:
φ φ φ φ
D
φ φ
Master-Slave Pulse-Triggered
(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop
Latches Latch
L1 L2 L
VDD VDD VDD Data Data
D Q D Q D Q
D D
Clk Clk Clk Clk
φ φ

Clk

( ) Positive
(c) P iti edge-triggered
d ti d D flip-flop
fli fl
using split-output latches
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 Optional: Pulsed Latches Optional: Pulsed Latches
Hybrid Latch – Flip
Flip-flop
flop (HLFF), AMD K
K-6
6 and K
K-7
7:
VDD VDD

M3 M6 VDD
CLK CLK P1 P3
Q x Q
D CLKG CLKG MP CLKG
M2 M5
X M6
M3
MN
M1 M4
D P2 M5
M2
(a) register (b) glitch generation
M4
M1 CLKD
CLK

CLKG

(c) glitch clock

© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd

Sequential Circuits Sequential Circuits

Optional: Pulsed FF (AMD-

(AMD-K6)
Optional: Hybrid Latch-
Latch-FF Timing ‰ Pulse
P l registers
i t - a short
h t pulse
l ((glitch
lit h clock)
l k) iis generated
t d
locally from the rising (or falling) edge of the system clock
and is used as the clock inputp to the flipflop
p p
z race conditions are avoided by keeping the transparent mode time
3.0
very short (during the pulse only)
2
2.5 z advantage
d t is
i reduced
d d clock
l k lload;
d di
disadvantage
d t iis substantial
b t ti l
increase in verification complexity
2.0 D Q
0/Vdd ON/OFF
OFF
1.5
Volts

clk 0 1
P1 ON Vdd
P3 Q 1/0
1.0 X

M3 OFF M6 OFF
0.5 CLK CLKD ON ON
1/0
0.0 D M2 ON/ P2 M5
1 OFF
1 0 1
20.5 ON
M1 M4
00
0.0 02
0.2 00.44 06
0.6 08
0.8 10
1.0 ON !clkd
0 OFF
time (ns)
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 Optional: Sense Amp FF ((StrongArm
StrongArm SA100) Flipflop Comparison Chart
‰ Sense amplifier (circuits that accept small swing input
signals and amplify them to full rail-to-rail signals) flipflops Name Type #clk ld #tr tset-up thold tpFF
z advantages
g are reduced clock load and that it can be used as a
receiver for reduced swing differential buses Mux Static 8 (clk-!clk) 20 3tpinv+tptx 0 tpinv+tptx
PowerPC Static 8 (clk-!clk) 16
0 1
2-phase Ps-Static 8 (clk1-clk2) 16
D 1
M9
1 0
M2 T-gate Dynamic 4 (clk-!clk) 8 tptx to1-1 2tpinv+tptx
M5 M7
C2MOS Dynamic 4 (clk-!clk) 8
Q
TSPC Dynamic 4 (clk) 11 tpinv tpinv 3tpinv
M1 M4
1
S-O TSPC Dynamic 2 (clk) 10
!Q
AMD K6 Dynamic
y 5 ((clk)) 19
M6 M8
M3 1 1 SA 100 SenseAmp 3 (clk) 20
0 M10
clk 0 1

© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd

Sequential Circuits Sequential Circuits

Pipelining
Choosing a Clocking Strategy ‰ Pipelining:
p g ap popular
p design
g technique
q to accelerate operation
p of
‰ Choosing the right clocking scheme affects the functionality, speed, datapaths in digital processors.
and power of a circuit ‰ Ex: Datapath to compute log(|a+b|). (a,b: streams of numbers).
‰ T
Two-phase
h d
designs
i Without pipeline,
pipeline minimum clock period Tmin for correct evaluation is:
ƒ + robust and conceptually simple Tmin,non-pipe=tc-q+tpd,logic+tsu
ƒ - need to generate and route two clock signals
tc-q,
q, tsu: propagation delay and setup time of register,
tpd,logic: worst case delay path through combinational network,
ƒ - have to design to accommodate possible skew between the
two clock signals
tpd,logic=tpd,add+tpd,abs+tpd,log
‰ Single phase designs
ƒ + only need to generate and route one clock signal
ƒ + supported by most automated design methodologies
ƒ + don’t have to worry about skew between the two clocks
ƒ - have to have g guaranteed slopes
p on the clock edgesg

Example
E l off pipelined
i li d
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd computations
Sequential Circuits Sequential Circuits
 Pipelining Pipelining
‰ Pipeline
p improves
p resource utilization and increases functional ‰ Assume latch delay and setup time are ignorable with respect
throughput, with the cost of additional pipeline registers and to logic delays, and all logic blocks have approximately the same
increased latency. propagation delay
‰ Ex: Datapath to compute log(|a+b|)
log(|a+b|). (a,b:
(a b: streams of numbers)
numbers). tp,add=tp,abs=tp,log=tp
With pipeline, minimum clock period Tmin for correct evaluation is:
9 Minimum clock period for non-pipelined design: Tmin_non_pipe=3tp
Tmin,pipe=tc-q+max(tpd,add, tpd,abs, tpd,log)+tsu
9 Minimum clock period for pipelined design: Tmin_pipe
i i =ttp
9 The pipelined network outperformed the non-pipelined version
by 3 times: Tmin_pipe=Tmin_non_pipe/3

REG

REG
a a

REG

REG

REG
. .

REG
φ log Out φ log Out

φ φ φ φ

REG

REG
b b

Example
E l off pipelined
i li d computations
t ti Non pipelinedversion
Non-pipelined version Pipelined version
φ φ
(assembly-line fashion)
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits

Latch-
Latch
‰ Pipeline
p
-Based Pipeline
circuits can be constructed with level-sensitive latches or
Pipelined Logic using C2MOS Latches
‰ Pipelining datapath using C2MOS latches
edge-triggered registers.
‰ Design constraint: A C2MOS-based pipelined circuit is
‰ Ex: Pipeline based on pass-transistor-based positive and negative
latches (using clk-clk’
clk clk two
two-phase
phase non-overlapping
non overlapping clocks) race-free as long as all the logic functions F, G
9 when clk=0→1, input data is sampled on C1, computation of F starts, (implemented using static logic) between the latches are
9 when clk=1→0, result of F is stored on C2 and computation of G starts. noninverting.
‰ Latch-based pipeline has race condition if overlap between clk and clk’
clk
exists. CLK CLK CLK
M2 M6 M2
In Out
F G
clk M4 !clk M8 clk M4
C1 C2 C3 F G
In Out
!clk M3 C1 clk M7 C2 !clk M3 C3
CLK M1 M5 M1

CLK
NORA Logicg
Compute F compute G
What are the constraints on F and G?
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 Pipelined Logic using C2MOS Latches Pipelined Logic using C2MOS Latches
‰ In a C2MOS based pipelined circuit circuit, the only way a signal can ‰ Ex.
E If F is an inverter,
in erter in (0-0)
(0 0) clock overlapping,
o erlapping all
race from stage to stage is when logic function F is inverting. C2MOS latches simplify to pure pull-up networks: input races
‰ Ex. If F is an inverter, in ((1-1)) clock overlapping,
pp g all C2MOS to output
output. (clk
(clk=clk’=0
clk 0, when In=0
In 0, it directly passes to Out
Out,
latches simplify to pure pull-down networks: input races to output. Out=1→not allowed!)
(clk=clk’=1, when In=1, it directly passes to Out, Out=0→not
allowed! Signal should pass one stage at a time) time).
VDD VDD VDD

φ φ
1
φ φ

N b off a static
Number t ti inversions
i i should
h ld be
b even
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits

NORA CMOS Modules NORA CMOS Modules

‰ NORA-CMOS: NO-Race logic, used for fast pipelined ‰ Examples of NORA-CMOS modules
datapaths using dynamic logic.
9 It combines
bi C2MOS pipeline
i li registers
i t and d np-CMOS
CMOS VD D VDD VDD
dynamic logic function blocks. φ φ
9 Each module consists of a block of combinational logic φ Out
In1 PUN
that can be a mixture of static and dynamic logic, followed In2
In3
PDN
φ
byy a C2MOS latch. φ φ ((a)) φ-module
9 Logic and latch are clocked such that both are simul-
taneously in either evaluation, or hold (precharge) mode. Combinational logic Latch

9 A bl
block
k th
thatt iis iin evaluation
l ti d during
i Φ=1Φ 1 iis called
ll d a Φ-
Φ VDD VDD VDD VD D
module, while the inverse is called a Φ-module. φ In 4

In 1 φ Out
In 2 PDN
In 3 φ
φ In4 (b) φ-module
module

nor2 inverter
© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd
Sequential Circuits Sequential Circuits
 NORA CMOS Modules NORA CMOS Modules
‰ NORA datapath consists of a chain of alternating Φ and Φ
modules ‰ Design Rules
‰ While one class of module is precharging with its output 9 The dynamic-logic rule: inputs to a dynamic Φn (Φp) block
latch in hold mode, preserving the previous output value, the are only allowed to make a single 0→1 (1→0) transition
other class is evaluating. during the evaluation period.
‰ Data
D t isi passedd iin a pipelined
i li d ffashion
hi ffrom module
d l tto 9 The C2MOS rule: In order to avoid races
races, the number of
module. Due to its design flexibility, extra inverter stages, as static inversions between C2MOS latches should be even.
required in Domino-CMOS
Domino CMOS, are most often avoidedavoided. ‰ Revised C2MOS rule:
9 The number of static inversions between C2MOS latches
should be even (in the absence of dynamic nodes); if
dynamic nodes are present, the number of static inversions
between a latch and a dynamic gate in the logic block
should be even
even. The number of static inversions between
the last dynamic gate in a logic block and the latch should
be even as well.

© Digital Integrated Circuits2nd © Digital Integrated Circuits2nd

Sequential Circuits Sequential Circuits

Multivibrator Cricuits
Cricuits Non--Bistable Sequential Circuits─Schmitt Trigger
Non
‰ Bistable circuits: two stable states. ((e.g.
g register,
g , latch)) ‰ Schmitt trigger:
‰ Astable circuits: oscillators (e.g. on-chip clock generation) 9 Slowly changing input leads to fast transition time at output
‰ Monostable (one-shot) circuits: used for pulse generators 9 VTC displays different switching thresholds for positive-
‰ Schmitt
S h itt ttrigger:
i h
hysteresis
t i iin DC characteristics,
h t i ti switching
it hi and negative-going input signals - hysteresis.
threshold depends on transition direction (low-to-high or 9 Switching thresholds for low-to-high and high-to-low
high-to-low) good in noisy environments
high-to-low), environments. transitions are called VM+ and VM-.
Vout VOH
9 Hysteresis voltage = VM+-VM-

I
In O t
Out

VOL

Schematic symbol
VM– VM+ Vin
VTC of non-inverting Schmitt trigger
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 Noise Suppression using Schmitt Trigger CMOS Schmitt Trigger
‰ Schmitt trigger can turn a noisy or slowly varying input to ‰ CMOS Schmitt trigger design
a clean digital output. 9 Switching threshold VM of CMOS inverter depends on (kn/kp)
‰ Reason for hysteresis: positive feedback
feedback. 9 Increasing (kn/kp) ratio reduces VM, and vice versa
9 Adapting the ratio depending on the direction of the
Vin
i Voutt transition results in a shift in switching thresholds → hysterisis
VDD

VM+
M2 M4

Vin X Vout

VM–
M1 M3

t0 t t 0 + tp t

Moves switching threshold

of
first inverter
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Schmitt Trigger
gg Simulated VTC Alternative CMOS Schmitt Trigger Design
‰ Alternative CMOS Schmitt trigger design

VDD

5.0 6.0
M4

4.0 M6

4.0 M3
3.0
Vout (V)

V M+ In Out
VX (V)

2.0 M2
20
2.0 X
V M- M5 VD D
1.0
M1
0.0
0 0 0.0
0 0
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0
Vin (V) V in (V)

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 Transition--Triggered Monostable
Transition Monostable Trigger (RC
(RC--based)
‰ Monostable circuit:
circ it generates a pulse
p lse of a predetermined ‰ Monostable circ
circuit
it using
sing feedback combined with
ith RC timing
width every time the quiescent circuit is triggered by a pulse or network to produce output pulse of fixed width
transition event
event.
VDD
‰ Only 1 stable state (the quiescent one)
‰ Used to generate pulses of known length In
A
R
B O t
Out
‰ Monostable circuit using a delay element to control the
duration of the pulse C
(a) Trigger circuit.

9 In quiescent state
state, both inputs to XOR are identical → Out=0
9 An input transition causes XOR inputs to differ temporarily
→ Out
Out=11 for td then goes low again. In

In B VM
DELAY (b) Waveforms.
Out
td td
Out
t
t1 t2

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Astable Multivibrators (Oscillators) Voltage Controller Oscillator (VCO)

‰ Astable circuits: no stable states
states. Output oscillates back and ‰ Voltage-controlled oscillator (VCO): oscillation frequency is
forth between two quasi-stable states with a certain period. programmable (proportional to control voltage)
‰ Application: on-chip generation of clock signals. ‰ Just replace
p inverters in ring
g oscillator with current-starved
‰ Example: ring oscillator inverters
9 odd number of inverters connected in a circular chain ‰ Delay of current starved inverter can be adjusted by
9 oscillates with period T
T=2×t
2×tp×N controlling
t lli ththe currentt available
il bl tto (di
(dis)charge
) h CL off the
th gate
t
Schmitt Trigger
VD D VDD
restores signal slopes
M6 M4

M2
In
M1
Iref Iref

Vcontr M3
M5 Current starved inverter

tppH L (nsec)
4

propagation delay as a function

0.0
0.5 1.5
V co ntr (V)
2.5 of control voltage
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 Differential Delay Element and VCO Relaxation Oscillator
‰ Relaxation oscillator: astable circuit composed of an RC
network combined with feedback
Vo2 Vo1
v
v3 ‰ It has no stable state and oscillates with period T=2(log3)RC
1
in1 in2 v
2
v Out1
4
Out2
Vctrl
I1 I2

delay cell two stage VCO

3.0
V1 V2 V3 V4 R C
2.5

2.0

15
1.5 Int
1.0

0.5

0.0

2 0.5
0.5 1.5 2.5 3.5
time (ns)
T = 2 (log3) RC
simulated waveforms of 2-stage
2 stage VCO

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