EC65102 VLSI Design

L-T-P: 3-0-2; Cr: 04

Pre-requisite: Basic device electronics, MOSFET properties, and logic circuits.
Objectives: This course is intended to impart in-depth knowledge about analog and digital
CMOS circuits. The focus is on CMOS circuits. Issues to be covered include deep submicron
design, clocking, power dissipation, CAD tools and algorithms, simulation, verification,
testing, and design methodology. This course also dealt with design analysis techniques for the
static and dynamic evaluation of CMOS circuits and memory elements including flip-flops,
SRAM, and DRAM.
COURSE CONTENTS:
Unit III: Analysis of CMOS logic Circuits: MOSFET as Switch; Recapitulation of MOS;
CMOS Inverter, Noise Margin, CMOS logic circuits; NAND gate and NOR Gate; Complex
logic circuits; Pass transistor logic; CMOS Transmission gate; CMOS full adder.
Course Outcomes: After completion of course, students should be able to:
1. Demonstrate a clear understanding of CMOS fabrication flow and technology scaling.
2. Design MOSFET based logic circuit
3. Draw stick diagram and layout of a given logic circuit
4. Realize logic circuits with different design styles
5. Demonstrate an understanding of working principle of operation of different types of
memories
6. Demonstrate an understanding of working principles of clocking, power reduction and
distribution
Text/Reference Books:
1. Neil H. E. Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design", 2nd edition,
Pearson Education Asia.
2. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, "Digital Integrated Circuits: A
Design Perspective," Prentics Hall
3. Sung-Mo Kang, Yusuf Liblebici, "CMOS Digital Integrated Circuits," Tata Mc Graw HillR.
Jacob Baker, "CMOS Mixed-Signal Circuit Design," Wiley India Pvt. Ltd.
4. Ivan Sutherland, R. Sproull and D. Harris, "Logical Effort: Designing Fast CMOS Circuits",
Morgan Kaufmann

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
Introduction:
Almost 90% of the integrated circuits fabricated today use the CMOS technology. CMOS has
outperformed the BJT due to their following superior performances:
• Low power dissipation
• Low area due to less device requirement
• Easy scaling down of MOS device dimensions
• Low fabrication cost
The semiconductor world market is counted in billions of dollars per year. Almost 80% of the
market is dominated by CMOS; interestingly, silicon (Si) devices account for 97% of all
microelectronics.
The industry is projected to be 15 times the present size after 2025. Silicon is used for mostly
all IC fabrication, because of the following reasons:
• Abundance of Si in nature
• High quality native oxide of silicon (SiO2)
• Appropriate mechanical strength—up to 12-inch wafer
The desirable properties of materials used for CMOS integrated circuits are as follows:
• Si is used as a substrate
• Any other material should be compatible with Si
• Incorporation of new material should not increase production cost unexpectedly
The materials for gate and the insulator must have the following properties:
• Be compatible with Si technology
• Provide very good interface with Si
• Be reliable and reproducible.

Recapitulation of MOS
• Semiconductor devices, if properly designed, can be used for digital logic design as
well as for analog designs such as amplifiers.
• Scientists have come up with a large number of transistor structures (e.g., BJT, JFET,
MOSFET, UJT), but the metal oxide semiconductor (MOS) field effect transistor (FET)
or simply MOSFET is a semiconductor device which is most suitable for digital and
analog ICs. Almost 90% of the ICs are fabricated worldwide using MOSFET.
• The MOSFET, which is commonly known as MOS transistor has four terminals. The
source terminal serves as the source of carriers of either electron or hole.
• The drain terminal collects the carriers flown from the source terminal.
• The carriers flow from the source to the drain terminal through a conducting path called
channel.
• The flow of carriers in the channel is controlled by applying voltage at a third terminal
called gate of the MOSFET. The channel can be created either physically or electrically.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
• Depending on how the channel is created, MOSFETs are classified into two types: (a)
enhancement type and (b) depletion type.
• Enhancement-type MOSFET If the MOSFET is normally OFF, and is turned ON by
applying voltage at the gate terminal, then the MOSFET is known as enhancement-type
MOSFET.
• Depletion-type MOSFET If the MOSFET is normally ON, and is turned OFF by
applying voltage at the gate terminal, then the MOSFET is known as depletion type
MOSFET.

Fig. Cross-sectional view of MOSFET: (a) enhancement type; (b) depletion type
There are different symbols used to represent the MOSFETs, and these are illustrated
in Fig.

Fig. Enhancement-type MOSFET: (a) n-channel; (b) p-channel

• In a MOS capacitor, the lower plate is replaced by a semiconductor material which is
often called substrate. The structure of a MOS capacitor is shown in Fig.

Fig. Structure of the MOS capacitor

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 The expression for MOS capacitance can be written as

where area of the MOS capacitor is A = (W × L) and tox is the oxide thickness, and εox
is the dielectric constant of the oxide material.
• The energy band diagram of the p-type substrate is shown in Fig. 8.

Fig. Energy band diagram of a p-type silicon substrate.

• The electron affinity of silicon, which is the potential difference between the conduction
band level and the vacuum (free-space) level, is denoted by qχ.
• The energy required for an electron to move from the Fermi level into free space is
called the work function qφs, and is given by

Fig. Energy band diagrams of the components that make up the MOS system.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
• Because of the work-function difference between the metal and the semiconductor, a
voltage drop occurs across the MOS system.
• Part of this built-in voltage drop occurs across the insulating oxide layer. The rest of
the voltage drop (potential difference) occurs at the silicon surface next to the silicon-
oxide interface, forcing the energy bands of silicon to bend in this region.
• The resulting combined energy band diagram of the MOS system is shown in Fig.

Fig. Energy band diagram of the combined MOS system.

Note: If a voltage corresponding to this potential difference is applied externally
between the gate and the substrate, the bending of the energy bands near the surface
can be compensated, i.e., the energy bands become "flat." Thus, the voltage defined

by
is called the flat-band voltage.
The MOS System under External Bias:
• Depending on the polarity and the magnitude of VG, three different operating regions
can be observed for the MOS system: Accumulation, depletion and inversion.
• Note: In accumulation, accumulation of hole underneath the oxide surface. For small
gate bias, there will be a depletion region created underneath the oxide layer. Therefore,
the distance of the induced charge from the upper plate increases. As a result, the
capacitance is lower as compared to the parallel plate capacitor.
• For larger gate bias, the induced electrons accumulate underneath the oxide layer, which
is known as inversion layer. Therefore, the MOS capacitance again increases to the
parallel plate capacitance value.

Fig. MOS capacitance–voltage characteristics

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
• To derive the expression for the threshold voltage, we identify the components of the
gate voltage required to create the inversion layer under strong inversion as shown
below:
(i) The difference between the work function of the gate and channel
(ii) The voltage required to create strong inversion
(iii) The voltage required to offset the depletion layer charge
(iv) The voltage required to offset the fixed oxide charge

Combining the above four components, the threshold voltage of the MOSFET can be
written as

For zero substrate bias, the threshold voltage VT0 is expressed as follows:

For nonzero substrate bias, generalized threshold voltage expression:

The generalized form of the threshold voltage can also be written as

The depletion region charge density at surface inversion (φS=-φF)

If the substrate (body) is biased at a different voltage level than the source, which is at
ground potential (reference), then the depletion region charge density can be expressed
as a function of the source-to-substrate voltage VSB.

Thus, the most general expression of the threshold voltage VT can be found as
follows:

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Substrate bias effect or body effect: The substrate bias effect, also known as the body
effect, is a phenomenon in MOSFETs where an increase in the source-to-body voltage
VSB leads to an increase in the threshold voltage Vth. This occurs because the higher
VSB widens the depletion region in the channel, requiring a greater gate voltage to
achieve inversion.
MOSFET Current Equation

Note : The ratio of W/L is one of the most important design parameters in MOS digital
circuit design.

Incorporating channel length modulation:

Process of varying channel length with increasing VDS.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Fig.: Channel length modulation in an n-channel MOSFET operation in saturation mode.

The effective channel length is reduced to

And drain current in saturation region when adding channel length modulation:

To simplify the analysis even further, we will use the following empirical relation
between ΔL and the drain-to-source voltage instead:

Here, λ is an empirical model parameter, and is called the channel length modulation
coefficient.

Fig.: Current-voltage characteristics of an n-channel MOS transistor, including the

channel length modulation effect.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
MOSFET as Switch:

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
Pass Transistor (Application of MOSFET as Switch):

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
CMOS Transmission gate (Application of MOSFET as Switch):

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
Inverter:
An inverter is a basic logic circuit with single input and output. It is also known as the NOT
gate. The output of the inverter is the complement of its input.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
The voltage transfer characteristics (VTC) of an inverter represent its output volt age as a
function of the input voltage.

In an ideal inverter, the output voltage (Vout) is maintained at the maximum value (VDD) when
the input voltage (Vin) varies from 0 to VDD/2, and becomes 0 for input voltages from VDD/2 to
VDD.
Critical Voltages:
We have seen that in an ideal inverter circuit, the input voltage for logic ‘0’ ranges from 0 to
VDD/2; and the input voltage for logic ‘1’ ranges from VDD/2 to VDD. The same is true for the
output voltage as well. However, in practical inverter circuits the input voltage for logic ‘0’
ranges from 0 to VIL, and the input voltage for logic ‘1’ ranges from VIH to VDD. Similarly, the
output voltage for logic ‘0’ ranges from 0 to VOL, and that for logic ‘1’ ranges from VOH to
VDD; where the variables are defined as follows:
• VIL = maximum input voltage that can be treated as logic ‘0’
• VIH = minimum input voltage that can be treated as logic ‘1’
• VOL = maximum output voltage that can be treated as logic ‘0’
• VOH = minimum output voltage that can be treated as logic ‘1’.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Noise Margins
Practical inverter circuits experience external disturbances leading to extra volt age on
the signal lines. Such unwanted additional voltage is termed as noise. If the noise in a
digital circuit exceeds certain margins, known as noise margins, the desired logic levels
are changed.
In practical inverter circuits, the maximum input low level is VIL and the maxi mum
output low level is VOL. Therefore, if VIL > VOL, then there is a margin in the input
voltage for logic ‘0’, which can be allowed without causing any change in the output
voltage. Hence, the noise margin for logic ‘0’ (NML) is defined as follows:

Similarly, the noise margin for logic ‘1’ (NMH) is defined as follows:

CMOS Inverter:
• The CMOS, or complementary MOS, inverter uses a pMOS transistor in the pull-up
network, and nMOS transistor in the pull-down network, as illustrated in Fig.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
• When the input is at logic low, the pMOS transistor is ON, and the nMOS transistor is
OFF. Therefore, the output is at logic high. On the other hand, when the input is at logic
high, the pMOS transistor is OFF, and the nMOS transistor is ON, and hence the output
is at logic low.
• The advantage of a CMOS inverter is that as the nMOS and pMOS transistors
functionally complement each other, they are never ON together; and hence, there is no
direct path from VDD to the ground for static current to flow. Therefore, the static power
dissipation is zero, if we neglect the leakage current.
• Another advantage of the CMOS inverter is that the logic swing is from 0 to VDD, which
is not possible in both resistive and nMOS load inverter circuits.
Voltage Transfer Characteristics:

Fig. Voltage transfer characteristics of a CMOS inverter

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
While Calculation of VIL, we have:

So we can write:

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 While Calculation of VIH, we have:

Transient Analysis of CMOS Inverter

• In order to obtain the transient characteristics, we apply a pulse at the input of the
inverter and connect a capacitive load at its output.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
• Since a capacitor cannot get charged or discharged instantaneously—it takes some time
to charge or discharge, the charging and discharging time is determined by the time
constant of the circuit.
• In case of digital logic circuits, time delay is defined as the time difference between the
50% point of the input waveform and the 50% point of the output waveform.
• There are two-time delays between the input and output waveforms: one is due to the
delay between the input and output waveforms during the high-to-low transition of the
output waveform, termed as TPHL, and the other is due to the delay between input and
output waveforms during the low-to-high transition of output waveform, termed as
TPLH.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
Estimation of rise time, fall time & propagation delay for practical CMOS inverter:

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
Estimation of Power, Energy, and Energy-Delay for practical CMOS inverter:
Static Consumption:
• The static (or steady-state) power dissipation of a circuit is expressed as:

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 where Istat is the current that flows between the supply rails in the absence of
switching activity.
• Ideally, the static current of the CMOS inverter is equal to zero, as the PMOS and
NMOS devices are never on simultaneously in steady-state operation. There is,
unfortunately, a leakage current flowing through the reverse-biased diode junctions
of the transistors, located between the source or drain and the substrate.

Dynamic Dissipation due to Charging and Discharging Capacitances

• Each time the capacitor CL gets charged through the PMOS transistor, its voltage
rises from 0 to VDD, and a certain amount of energy is drawn from the power supply.
• Part of this energy is dissipated in the PMOS device, while the remainder is stored
on the load capacitor. During the high-to-low transition, this capacitor is discharged,
and the stored energy is dissipated in the NMOS transistor.
• Let us first consider the low-to high transition. We assume, initially, that the input
waveform has zero rise and fall times, or, in other words, that the NMOS and PMOS
devices are never on simultaneously. Therefore, the equivalent circuit of Figure is
valid. The values of the energy EVDD, taken from the supply during the transition,
as well as the energy EC, stored on the capacitor at the end of the transition, can be
derived by integrating the instantaneous power over the period of interest. The
corresponding waveforms of vout(t) and iVDD(t) are pictured in Figure.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
Pdyn is also represented as Pavg.

Analysis of CMOS logic Circuits:

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
CMOS logic circuits:
• A circuit that uses complementary pairs of p-channel and n-channel MOSFETs
is called CMOS (Complementary MOS). CMOS logic ICs combine MOSFETs
in various ways to implement logic functions.
• CMOS logic uses both NMOS and PMOS transistors. The PMOS transistors
are used as pull-up network and NMOS transistors are used as pull-down
network.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • And because of that, the static power consumption of the CMOS based logic
gates and logic circuit is very low compared to the logic gates which is designed
using only either NMOS or PMOS transistors.
• Moreover, CMOS based logic gates has higher noise margin compared to
NMOS and PMOS based logic gates.
NAND gate and NOR Gate
• NAND and NOR gates can be easily realized using CMOS logic as shown below.

Other logic gates:

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
Designing Complex logic circuits:

Assignment 2:
1. Design n bit comparator using NMOS & CMOS design techniques. Draw stick
diagram representation also.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
CMOS full adder:

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna