EC65102 VLSI Design

L-T-P: 3-0-2; Cr: 04

Pre-requisite: Basic device electronics, MOSFET properties, and logic circuits.
Objectives: This course is intended to impart in-depth knowledge about analog and digital
CMOS circuits. The focus is on CMOS circuits. Issues to be covered include deep submicron
design, clocking, power dissipation, CAD tools and algorithms, simulation, verification,
testing, and design methodology. This course also dealt with design analysis techniques for the
static and dynamic evaluation of CMOS circuits and memory elements including flip-flops,
SRAM, and DRAM.
COURSE CONTENTS:
Unit II: VLSI Circuit Design Processes: Basic CMOS Technology, n-well CMOS process, p-
well CMOS process, Twin tub process, Silicon on insulator; CMOS process enhancement-
Interconnect; circuit elements, Stick Diagrams, Design Rules and Layouts, Lambda based
design rules, Contact cuts, CMOS Lambda and Micron based design rules, Layout Diagrams
for logic gates, Transistor structures, wires and vias, Scaling of MOS circuits- Scaling
models, scaling factors, scaling factors for device parameters, Limitations of Scaling.
[8L]
Course Outcomes: After completion of course, students should be able to:
1. Demonstrate a clear understanding of CMOS fabrication flow and technology scaling.
2. Design MOSFET based logic circuit
3. Draw stick diagram and layout of a given logic circuit
4. Realize logic circuits with different design styles
5. Demonstrate an understanding of working principle of operation of different types of
memories
6. Demonstrate an understanding of working principles of clocking, power reduction and
distribution
Text/Reference Books:
1. Neil H. E. Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design", 2nd edition,
Pearson Education Asia.
2. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, "Digital Integrated Circuits: A
Design Perspective," Prentics Hall
3. Sung-Mo Kang, Yusuf Liblebici, "CMOS Digital Integrated Circuits," Tata Mc Graw HillR.
Jacob Baker, "CMOS Mixed-Signal Circuit Design," Wiley India Pvt. Ltd.
4. Ivan Sutherland, R. Sproull and D. Harris, "Logical Effort: Designing Fast CMOS Circuits",
Morgan Kaufmann
VLSI Circuit Design Processes
There are a number of approaches to CMOS fabrication, including the p-well, the n-well, the
twin-tub, and the silicon-on-insulator processes. In order to introduce CMOS design, well-
based circuits are considered. The p-well process is widely used-in practice and the n-well
process is also popular particularly as it was an easy retrofit to existing nMOS lines.
CMOS process flow:
There are a number of approaches to CMOS fabrication, including the p-well, the n-well, the
twin-tub, and the silicon-on-insulator processes.
The p-well process:
• In primitive terms, the structure consists of an n-type substrate in which p devices may
be formed by suitable masking and diffusion and, in order to accommodate n-type
devices, a deep p-well is diffused into the n-type substrate as shown.
• The p-wells act as substrates for the n-devices within the parent n-substrate, and,
provided that voltage polarity restrictions are observed, the two areas are electrically
isolated.

Fig.: MOS p-well process steps

 Fig.: CMOS p-well inverter showing VDD and VSS substrate connections

In summary, typical processing steps are:

• Mask I - defines the areas in which the deep p-well diffusions are to take place.
• Mask 2 - defines the thinox regions, namely those areas where the thick oxide is to be stripped
and thin oxide grown to accommodate p- and n-transistors and diffusion wires.
• Mask. 3 - used to pattern the polysilicon layer which is deposited after the thin oxide.
• Mask 4—A p-plus mask is now used to define all areas where p-diffusion is to take place.
• Mask 5 - This is usually performed using the negative form of the p-plus mask and, with
Mask2, defines those areas where n-type diffusion is to take place.
• Mask 6 - Contact cuts are now defined.
• Mask 7 - The metal layer pattern is defined by this mask.
• Mask 8 - An overall passivation (over glass) layer is now applied and Mask 8 is needed to
define the openings for access to bonding pads.

The n-well process

• N-well CMOS circuits are also superior to p-well because of the lower substrate bias
effects on transistor threshold voltage and inherently lower parasitic capacitances
associated with source and drain regions.
 Fig.: Main steps in a typical n-well process

Fig.: Cross-sectional view of n-well CMOS inverter

The twin-tub process

• A logical extension of the p-well and n-well approaches is the twin-tub fabrication
process.
• Here we start with a substrate of high resistivity n-type material and then create both n-
well and p-well regions. Through this process it is possible to preserve the performance
of n-transistors without compromising the p-transistors.
• In general, the twin-tub process allows separate optimization of the n- and p- transistors.
 Fig.: Twin-tub structure

Quiz:
Q. 1 What is the role of a well region in CMOS fabrication?
a) To form the source of the transistor
b) To create an isolation barrier
c) To allow for the integration of NMOS and PMOS transistors on the same chip
d) To connect the metal layers
Q. 2 In CMOS fabrication, what is the purpose of the silicon dioxide layer?
a) To act as a gate material
b) To isolate the gate from the substrate
c) To enhance electrical conductivity
d) To reduce heat dissipation

Silicon on insulator
• Silicon on insulator (SOI) refers to the use of a three-layered substrate in place of
conventional bulk silicon substrates.
• A thin layer of silicon is placed on top of an insulator such as silicon dioxide (SiO2)
also known as a buried oxide layer. This layer lies upon the substrate and isolates the
body from the substrate. The transistors are then built upon the thin silicon layer.
• The full dielectric isolation of the devices reduces parasitic capacitance, thereby
improving performance.
• The choice of the insulating layer depends largely on the intended application. Sapphire
is used for high performance radio frequency (RF) and Radiation sensitive applications
& SiO2 is used for diminished short channel effects in microelectronic devices.
What is the need of SOI ?
• For the continuation of Moore’s Law beyond 28 nm with an upgrade to traditional
planar bulk CMOS technology. Thus, As transistor shrinks, the length of the gate is
reduced. The control of the gate over a channel region is also reduced, thus lowering
the transistor performance. SOI provides more control over channel using body biasing.
• Increased complexities in scaling of conventional bulk CMOS technology.
 • To avoid interactions between the devices and the substrate which gives rise to
unwanted parasitic effects, mainly the parasitic capacitance developed between
diffused source and drain and the substrate.

Fig: SOI structure

Fully depleted silicon on insulator" (FD-SOI) refers to a transistor where the entire silicon
channel is depleted of charge carriers, while "partially depleted silicon on insulator" (PD-SOI)
means only a portion of the silicon channel is depleted, with the key difference being the
thickness of the silicon layer, where a much thinner layer is used in FD-SOI, allowing for full
depletion and better performance characteristics like lower power consumption and improved
speed compared to PD-SOI;

CMOS fabrication by SOI technology: -

The subsequent steps for fabrication of CMOS SOI are similar to Bulk Technology.
CMOS process enhancement
In the Analog, Digital or RF CMOS integrated circuits along with transistors other elements
such as interconnects, resistors, capacitors are to be integrated on chip. In order to achieve this,
enhancements in CMOS process technology is required. The main goals of adding CMOS
enhancements are :

(1) To provide on chip capacitors for analog circuits.

(2) To provide on chip resistors.

(3) To provide routing of interconnects.

The enhancements in CMOS technology are :

(1) Multilevel metal layers.

(2) Multilevel poly layers.

Transistors :

To enhance the CMOS technology the bipolar transistors can be integrated on chip in CMOS
technology and this forms the BiCMOS technology. Figure below shows the cross-section of
BiCMOS process in which NMOS and npn transistor are fabricated on the same substrate.
 Fig. Bi-CMOS Structure

The starting material is p substrate on which n type epitaxial layer is grown. To form the NMOS
transistor a p well is diffused in selected area. And n+ diffusions form the source and drain
contacts. The n epi layer is diffused with the p+ diffusion which forms the base for the npn
transistor both the devices i.e. NMOS and npn transistors are isolated by field oxide.

Interconnect :

The most important enhancement in CMOS processes is the additions of signal and power
supply routing layers. The advantage of this type of routing is it improves power and clock
distribution to the different modules inside the chip. The interconnect layers involved in
process are:

(1) Metal interconnect

(2) Polysilicon interconnect

(3) Local interconnect.

The second layer of metal interconnect (Metal 2) is required for digital Integrated circuits. The
connection between first metal layer (Metal 1) and second metal layer (Metal 2) is established
with the help of via. For high speed chips third metal layer (Metal 3) is also required.

Polysilicon Interconnect layers are used in ICs because of its high melting points as compare
to Al. But the major problem with polysilicon interconnect is it has high sheet resistance
because of this for long distance interconnects this provides significant delay.

If silicide is used as a interconnect layer for connecting different cells then it is called as local
interconnect. The important advantage of local interconnect is it allows direct connection
between polysilicon and diffusion regions due to this metal contacts are eliminated which
reduces the chip area.

Interconnect
 • Interconnects are metal wires that are used to transmit signal from one node of the circuit to
other nodes. In VLSI circuits, the interconnect exhibits parasitic resistance, capacitance, and
inductance.
• As the technology advances, the dimension of the transistors and interconnects are scaled down.
But with the scaling, the effects of parasitic resistance, capacitance, and inductances become
more and more important.
• According to the recent technology trends, the parasitic resistance and capacitance have become
dominant in comparison to the inductance effects.
• Metal is used for interconnects because of high conductivity. Aluminium (Al) and copper (Cu)
are mostly used materials for interconnects.
• Poly-Si is used for short interconnects.
• If the length of the interconnect is such that the transit time through the interconnect is
comparable to the rise/fall time of the pulse waveform, then the interconnect should be
modelled as a transmission line.
• A transmission line is modelled as a distributed RLCG network, as shown in Fig. below. RLCG
indicates resistance, inductance, capacitance, and conductance, all of which are specified per
unit length of the interconnect line.

Fig. Transmission line model of the interconnect

Circuit elements
A circuit is an interconnection of elements. Electric circuits are made up of three circuit
components. These are resistance, inductance, and capacitance. But in VLSI, we considered
only resistance, and capacitance.
Sheet Resistance Rs
Consider a uniform slab of conducting material of resistivity p, of width W, thickness t, and
length between faces L. The arrangement is shown in Figure shown below.

Fig. Sheet resistance model .

With reference to Figure, consider the resistance RAB between two opposite faces.

For the MOS processes considered here, typical values of sheet resistance are given in Table.
STANDARD UNIT OF CAPACITANCE □Cg
Stick Diagrams

• MOS design is aimed at turning a specification into masks for processing silicon to
meet the specifications.
• MOS circuits are formed on four basic layers which are isolated from one another by
thick or thin silicon dioxide insulating layers.
• MOS Layers are- n- diffusion, p-diffusion, polysilicon and metal.
• VLSI design aims to translate circuit concepts onto silicon.
• Stick diagrams are a means of capturing topography and layer information using
simple diagrams.
• Stick diagrams convey layer information through colour codes (or monochrome
• encoding).
• Acts as an interface between symbolic circuit and the actual layout.
• It does show all components/vias.
• It shows relative placement of components.
• A stick diagram is a cartoon of a layout.
• It does not show exact placement of components, Transistor sizes, Wire lengths, wire
widths, tub boundaries.
Design Rules and Layouts, Lambda based design rules, Contact cuts, CMOS Lambda
and Micron based design rules, Layout Diagrams for logic gates, Transistor structures,
wires and vias,

• Design rules specify geometric constraints on the layout artwork.

• Provide a communication channel between the IC designer and the fabrication process
engineer.
• Two approaches to describing design rules
 Scalable Design Rule (λ based design rule): all rules are defined in terms of a single
parameter λ. Scaling can be easily done by simply changing the value of λ.

Absolute design Rule (μ based design rule): the design rules are expressed in absolute
dimensions (e.g. 0.75 μm)

Why we use design rules?

• Interface between designer and process engineer
• Historically, the process technology referred to the length of the silicon channel
between the source and drain terminals in field effect transistors.
• The sizes of other features are generally derived as a ratio of the channel length, where
some may be larger than the channel size and some smaller.
• For example, in a 90 nm process, the length of the channel may be 90 nm, but the width
of the gate terminal may be only 50 nm.

"Micron" rules
• All minimum sizes and spacing specified in microns.
• Rules don't have to be multiples of λ.
• Can result in 50% reduction in area over λ based rules
• Standard in industry.

Lambda-based Design Rules

•
Lambda-based (scalable CMOS) design rules define scalable rules based on 2 λ (which
is half of the minimum channel length)
• Circuit designer in general want tighter, smaller layouts for improved performance and
decreased silicon area.
• On the other hand, the process engineer wants design rules that result in a controllable
and reproducible process.
• Generally we find there has to be a compromise for a competitive circuit to be produced
at a reasonable cost.
• All widths, spacing, and distances are written in the form
2 = 0.5 X minimum drawn transistor length
 Assignment 1:
Please complete the assignment: Layout of CMOS inverter, NAND gate & NOR gate using
Microwind tool.
Please find the videos regarding this:
1. https://youtu.be/S1VOEqApQvA
2.https://youtu.be/ARiN-aeOwY?list=PLpPqMXJWWjSpsJA4MD25DUL_M15vu49qq
3. https://youtu.be/kCUraaYtZkY?list=PLpPqMXJWWjSpsJA4MD25DUL_M15vu49qq

Scaling of MOS circuits- Scaling models, scaling factors, scaling factors for device
parameters, Limitations of Scaling.
Scaling of MOS circuits:
Microelectronic technology may be characterized in terms of several indicators, or figures of
merit. Commonly, the following are used:
• Minimum feature size
• Number of gates on one chip
• Power dissipation
• Maximum operational· frequency
• Die size
• Production cost.
Many of these figures of merit can be improved by shrinking the dimensions of transistors,
interconnections and the separation between features, and by adjusting the doping levels and
supply voltages.
SCALING MODELS AND SCALING FACTORS
The most commonly used models are
(i) The constant electric field scaling model
(ii) The constant voltage scaling model.
(iii) Combined voltage and dimension scaling model
Figure indicates the device dimensions and substrate doping level which are associated with the
scaling of a transistor.

Fig. Scaled nMOS transistor (pMOS similar).

• In order to accommodate the three models, two scaling factors-1/α and 1/ꞵ are used.
• For Combined voltage and dimension scaling model, 1/ꞵ is chosen as the scaling factor for
supply voltage VDD and gate oxide thickness D, and 1/α is used for all other linear.
dimensions, both vertical and horizontal to the chip surface.
• For the constant field model, ꞵ = α is applied
• For the constant voltage model, ꞵ = 1 respectively are applied.

SCALING FACTORS FOR DEVICE PARAMETERS

LIMITATIONS OF SCALING

(i) Substrate Doping:

As the channel length of a MOS transistor is reduced, the depletion region widths must
also be scaled down to prevent the source and drain depletion regions from meeting.
Depletion region width d for the junctions is given by:
 • NB is increased to reduce the depletion width, but this also increases the threshold voltage
Vt which is against the required trends for scaling down. Thus, NB must be maintained at a
satisfactory level.

(ii) Limits of Miniaturization

• The minimum size of a transistor is determined by both process technology and the
physics of the device itself.
• The size of a transistor is usually defined in terms of its channel length L.
• As the channel length is scaled down, the edge of the depletion region around the
source comes closer to that around the drain.
• In order to prevent punch-through and maintain transistor action, it can be shown
th-at the channel length L must be at least 2d.
(iii) Limits of Interconnect and Contact Resistance
• With decreasing device dimensions, there is further increment in the levels of integration
and consequent increases in die size. This lengthens the interconnections from one side of
the chip to the other and, therefore, both resistance and capacitance of the interconnects are
increased, producing much larger time constant values. Thus, the effects of increased
propagation delays, signal decay, and clock skew will decrease maximum achievable
operating frequency.
• One solution to this problem has been to make use of multilayer interconnections with
thicker, wider conductors and thicker separating layers. This will reduce both R and C and
also reduce die size
(iv) Limits Due to Subthreshold Currents

• So, scaling affects Subthreshold Currents.

(v) Limits on Logic Levels and Supply Voltage Due to Noise

 • Major advantages in the scaling of devices are smaller gate delay time, that is, higher
operating frequencies and lower power dissipation. However, the decreased inter-
feature spacing and greater switching speeds inevitably result in noise problems. Noise
may also be amplified and is thus a major concern.
• Due to fluctuation of carriers in channel, flicker noise is experienced; which depends
on operating frequency. In addition to it, other noise inputs (mutual inductive and
capacitive coupling) also limits logic level and supply voltage.

(vi) Limits Due to Current Density

• The scaling down of dimensions also increases the current density in interconnects by the same
factor 'if constant field scaling is applied.
• High purity aluminium seems the most attractive, and is thus the most widely used, material for
forming interconnections in VLSI chips.

Major Advantage of scaling:

• Smaller gate delay implies high operating frequency & lower power dissipation
• Deceased inter-feature spacing thereby less production cost, thus more gate can be
fabricated in a chip.