Reg.

No:

V.R.S. College of Engineering and Technology, Arasur – 607 107

(Reaccredited by NAAC and an ISO 9001:2008 Recertified Institution)
Department of Electrical and Electronics Engineering
B.E. Degree CA Test-I
EE3022 – VLSI DESIGN (Regulation 2021)
Year : III Maximum Marks : 50 Marks
Semester : VI Time : 2 hours
Date : 23.04.2025
Answer ALL Questions.
PART–A(42=08Marks)
1. Define PAL.
2. Compare PLA and PAL.
3. Define and classify PLD.
4. Write the applications of CPLD.

PART–B(314=42Marks)

1. Explain the architecture of CPLD with proper diagram.

2. Draw and explain the architecture of PLA and PAL.
3. Implement the following Boolean functions using PAL,PLA.
w (A, B, C,D) = ∑ m (0, 2, 6, 7, 8, 9, 12, 13),
x ( A,B,C,D) = ∑ m (0, 2, 6, 7, 8, 9, 12, 13, 14)
y ( A,B,C,D) = ∑ m (2, 3, 8, 9, 10, 12,13),
z ( A,B,C,D) = ∑ m (1, 3, 4, 6, 9, 12, 14)
 Reg. No:

V.R.S. College of Engineering and Technology, Arasur – 607 107

(Reaccredited by NAAC and an ISO 9001:2008 Recertified Institution)
Department of Electrical and Electronics Engineering
B.E. Degree CA Test-I
EE3022 – VLSI DESIGN (Regulation 2021)
Year : III Maximum Marks : 100 Marks
Semester : VI Time : 180Minutes
Date : 26.03.2025
SET II
Answer ALL Questions.
PART–A (102=20Marks)

1. Define CMOS Transmission gate. 2 K1 CO1

2. Justify why nMOS is called as a pull down device? 2 K5 CO1
3. Tabulate nMOS and pMOS devices. 2 K1 CO1
4. Define scaling. List different types of scaling. 2 K1 CO1
5. List the different operating regions of MOS system. 2 K2 CO1
6. Give the advantages of CMOS IC. 2 K2 CO1
7. Define SSI, MSI, LSI and VLSI. 2 K1 CO2
8. Sketch a complementary CMOS gate computing Y = (AB+BC)’. 2 K4 CO2
9. Draw the stick diagram of static CMOS 2-input NAND gate 2 K2 CO2
10. List the limitations of stick diagrams. 2 K1 CO2

PART–B(513=65Marks)

Explain dynamic CMOS logic with suitable diagrams. (13) K2 CO1

11. A

OR
B Illustrate CMOS Logic Design with proper examples. Realise
CMOS Logic of [(A.B.C)+D]’ (13) K3 CO1

12. A Explain the types of scaling, scaling principles and fundamental

units of CMOS inverter (13) K2 CO1
OR
B List out the device parameters for scaling with relevant expressions.
(13) K1 CO1
 A Discuss the cutoff, linear and saturation region operation of MOS
13. transistor. (13) K3 CO1

OR
B Discuss short notes on transmission gates. Draw transmission gates
for NAND, NOR, XOR. (13) K2 CO1

Describe with neat diagram the p-well and channel formation in

14. A CMOS process. (13) K2 CO2

OR
Describe with neat diagram the n-well and channel formation in
B CMOS process. (13) K2 CO2

List the stick diagram rules. Draw stick diagram for NAND, NOR
15. A and inverter circuits.
(13) K2 CO2

OR
Explain the different steps involved in twin tub fabrication /
manufacturing process with neat diagrams. (13) K2 CO2
B

PART–C (115=15Marks)

Discuss the steps in IC fabrication of BiCMOS technology.

16. A
(15) K4 CO1
OR
Discuss the steps in IC fabrication process of SOI technology.
B (15) K4 CO1

Bloom’s Taxonomy Levels (K1-Remembering,K2- Understanding, K3 – Applying, K4–

Analyzing,K 5 – Evaluating, K6 - Creating)
At end of the Course, Students can

COURSE
DETAILS
OUTCOME
Develop CMOS design techniques
CO1
CO2 Learn and build IC fabrication
 V.R.S. College of Engineering and Technology, Arasur – 607 107
(Reaccredited by NAAC and an ISO 9001:2008 Recertified Institution)
Department of Electrical and Electronics Engineering
B.E. Degree CA Test-I
EE3022 – VLSI DESIGN (Regulation 2021)
Year/Sem : III /VI SET 1 –ANSWER KEY
PART–A(102=20Marks)
1. Define SSI, MSI, LSI and VLSI.
Small scale Integration:
 Small-Scale Integration (SSI) circuits have less than 10 gates. Example: 7404 inverters.
Medium scale Integration:
 Medium-Scale Integration (MSI) circuits have up to 1000 gates. Example: 74161
counters.
Large scale Integration:
 Large-Scale Integration (LSI) circuits have up to 10,000 gates. Example: 8-bit
microprocessor (8085).
Very large scale Integration:
 Very large scale Integration (VLSI) with gates counting upto lakhs. Example: 16-bit
microprocessor (8086).
2. Give the advantages of CMOS IC.
Advantages of Integrated Circuit:
 Size is less
 High Speed
 Less Power Dissipation
3. Define scalingList different types of scaling.
Scaling is reducing the feature size of transistor. The transistor size has reduced by 30%
every two to three years. As transistors become smaller, they switch faster, dissipate less power,
and are cheaper to manufacture. Types of scaling are transistor scaling and interconnect
scaling.Types of transistor scaling are lateral scaling, constant field scaling and constant voltage
scaling.
4. List the different operating regions of MOS system.
• Cutoff Region
• Non-Saturated
• (Linear) Region
• Saturated Region
5. Tabulate nMOS and pMOS devices.
 In nMOS, electrons are the majority carriers.
When the gate of an nMOS transistor is high, the transistor is ON. When the gate is
low, the nMOS transistor is OFF.
 In pMOS, holes are the majority carriers.When the gate of a pMOS transistor is
low, the transistor is ON. When the gate is high, the
pMOS transistor is OFF.
nMOS Symbol pMOS Symbol

6. Justify why nMOS is called as a pull down device?

 A device is connected to pull the output voltage to the lower supply voltage (0V) is called pull
down device.
8. Sketch a complementary CMOS gate computing Y = (AB+BC)’.

9. Draw the stick diagram of static CMOS 2-input NAND gate.

10. List the limitations of stick diagrams.

Oversimplification
Lack of Detail
Not to Scale
Simplified Representation of Layers
PART–B
Explain the types of scaling, scaling principles and fundamental units of CMOS (13)
11. A inverter
Scaling Definition: (4 Marks)
Types of scaling:( 2*4=8 Marks)
B List out the device parameters for scaling with relevant expressions.
(13)
Scaling Device parameters-13*1 (13 marks)
A Explain dynamic CMOS logic with suitable diagrams.
12 Logic Diagram &Truth table (6 Marks) (13)
Explanation(7 Marks)
B Illustrate CMOS Logic Design with proper examples. Realize CMOS Logic of
[(A.B.C)+D]’ (13)
Step by Step Realization: (6 Marks)
CMOS logic Diagram: (7 Marks)
A Discuss the cutoff, linear and saturation region operation of MOS transistor.
13. Cutoff region(3 Marks) (13)
Linear (Active) Region(5 Marks)
Saturation region(4 Marks)
B Discuss short notes on transmission gates. Draw transmission gates for NAND,
(13)
NOR, XOR.
Transmission gates definition &Explanation(4 Marks)
Draw transmission gates for NAND, NOR, XOR.(3+3+3=9 Marks)
Describe with neat diagram the p-well and channel formation in CMOS process.
14. A (13)
Fabrication steps:(8 Marks)
 Diagram(5 Marks)

Describe with neat diagram the n-well and channel formation in CMOS process.
B
Fabrication steps:(8 Marks)
Diagram(5 Marks)
List the stick diagram rules. Draw stick diagram for NAND, NOR and inverter
15. A circuits.
Stick diagram rules(4 Marks) (13)
Stick diagram for NAND, NOR and inverter circuits.
Explain the different steps involved in twin tub fabrication / manufacturing process
with neat diagrams. (13)
B
Fabrication steps:(8 Marks)
Diagram(5 Marks)
PART–C (115=15Marks)

List out the steps in IC fabrication with proper diagrams.

16 A (15)
. Fabrication steps:(8 Marks)
Diagram(7 Marks)
Discuss the steps in IC fabrication of BiCMOS technology.
B Fabrication steps:(8 Marks) (15)
Diagram(7 Marks)

SET II –ANSWER KEY

Answer ALL Questions.
PART–A (102=20Marks)

1. Define CMOS Transmission gate. 2

 By connecting an nMOS and a pMOS transistor in parallel, we obtain a switch
that turns on when a 1 is applied to the gate terminal in which 0’s and 1’s are
both passed in an acceptable fashion.
 We term this a transmission gate or pass gate.
2. Justify why nMOS is called as a pull down device? 2
A device is connected to pull the output voltage to the lower supply voltage (0V) is called pull
down device.
3. Tabulate nMOS and pMOS devices. 2
 In nMOS, electrons are the majority carriers.
When the gate of an nMOS transistor is high, the transistor is ON. When the
gate is low, the nMOS transistor is OFF.
 In pMOS, holes are the majority carriers.When the gate of a pMOS transistor
is low, the transistor is ON. When the gate is high, the
pMOS transistor is OFF.
nMOS Symbol pMOS Symbol

4. Define scaling. List different types of scaling. 2

Scaling is reducing the feature size of transistor. The transistor size has reduced by 30% every
two to three years. As transistors become smaller, they switch faster, dissipate less power, and
are cheaper to manufacture. Types of scaling are transistor scaling and interconnect
scaling.Types of transistor scaling are lateral scaling, constant field scaling and constant
voltage scaling.
5. List the different operating regions of MOS system. 2
 • Cutoff Region
• Non-Saturated
• (Linear) Region
• Saturated Region
6. Give the advantages of CMOS IC. 2
Advantages of Integrated Circuit:
 Size is less
 High Speed
Less Power Dissipation
7. Define SSI, MSI, LSI and VLSI. 2
 Small-Scale Integration (SSI) circuits have less than 10 gates. Example: 7404
inverters.
Medium scale Integration:
 Medium-Scale Integration (MSI) circuits have up to 1000 gates. Example: 74161
counters.
Large scale Integration:
 Large-Scale Integration (LSI) circuits have up to 10,000 gates. Example: 8-bit
microprocessor (8085).
Very large scale Integration:
Very large scale Integration (VLSI) with gates counting upto lakhs. Example: 16-bit
microprocessor (8086).
8. Sketch a complementary CMOS gate computing Y = (AB+BC)’. 2

9. Draw the stick diagram of static CMOS 2-input NAND gate 2

10. List the limitations of stick diagrams. 2

Oversimplification
Lack of Detail
Not to Scale
Simplified Representation of Layers
PART–B
Explain dynamic CMOS logic with suitable diagrams. (13)
11. A Logic Diagram &Truth table (6 Marks)
Explanation(7 Marks)
B Illustrate CMOS Logic Design with proper examples. Realize CMOS Logic of
[(A.B.C)+D]’ (13)
 Step by Step Realization: (6 Marks)
CMOS logic Diagram: (7 Marks)
A Explain the types of scaling, scaling principles and fundamental units of CMOS
12 inverter
Scaling Definition: (4 Marks)
Types of scaling:( 2*4=8 Marks)
B List out the device parameters for scaling with relevant expressions.
(13)
Scaling Device parameters-13*1 (13 marks)
A Discuss the cutoff, linear and saturation region operation of MOS transistor.
13. Cutoff region(3 Marks) (13)
Linear (Active) Region(5 Marks)
Saturation region(4 Marks)
B Discuss short notes on transmission gates. Draw transmission gates for NAND,
(13)
NOR, XOR.
Transmission gates definition &Explanation(4 Marks)
Draw transmission gates for NAND, NOR, XOR.(3+3+3=9 Marks)
Describe with neat diagram the p-well and channel formation in CMOS process.
14. A (13)
Fabrication steps:(8 Marks)
Diagram(5 Marks)
List the stick diagram rules. Draw stick diagram for NAND, NOR and inverter
15. A circuits.
Stick diagram rules(4 Marks) (13)
Stick diagram for NAND, NOR and inverter circuits.
Explain the different steps involved in twin tub fabrication / manufacturing process
with neat diagrams. (13)
B
Fabrication steps:(8 Marks)
Diagram(5 Marks)
PART–C (115=15Marks)

List out the steps in IC fabrication with proper diagrams.

16 A (15)
. Fabrication steps:(8 Marks)
Diagram(7 Marks)
Discuss the steps in IC fabrication of BiCMOS technology.
B Fabrication steps:(8 Marks) (15)
Diagram(7 Marks)