R.V.

COLLEGE OF ENGINEERING®,
BENGALURU
(AUTONOMOUS INSTITUTION AFFILIATED TO VTU, BELAGAVI)
DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

Design of Testing and Testability

(18EC7F3)
Experimental Learning report on

Complete BIST design for Full Adder

Team Members USN

Nihar KM 1RV18EC097
Sandesh Padiyar 1RV18EC141

Under the Guidance of:

Mrs. Namita Palecha
Assistant Professor
Department of Electronics and Communication Engineering
R.V College of Engineering, Bengaluru - 560059

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 Index
Sl.No Title Page No.
1 Introduc on 3
2 Problem Statement and specifica ons 4
3 Circuit Under Test (Code+TB+Result) 4
4 Test Pa ern Generator (Code+TB+Result) 6
5 Output Response Analyzer (Code+TB+Result) 9
6 BIST Controller Design (Code+TB+Analysis) 12
7 Conclusion 18

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Introduc on
The basic idea of BIST, in its most simple form, is to design a circuit so that
the circuit can test itself and determine whether it is “good” or “bad”
(fault-free or faulty, respec vely). This typically requires that addi onal circuitry
and func onality be incorporated into the design of the circuit to facilitate the
self-tes ng feature. This addi onal func onality must be capable of genera ng
test pa erns as well as providing a mechanism to determine if the output
responses of the circuit under test (CUT - in our case a 1-bit full adder) to the
test pa erns correspond to that of a fault-free circuit.

Figure 1.1 BIST Architecture

A representa ve architecture of the BIST circuitry as it might be incorporated

into the CUT is illustrated in the block diagram of Figure 1.1. The two essen al
func ons include the test pa ern generator (TPG) and output response
analyzer (ORA). While the TPG produces a sequence of pa erns for tes ng the
CUT, the ORA compacts the output responses of the CUT into some type of
Pass/Fail indica on. The BIST controller is the top module genera ng control
signals. When test mode is 1 the golden Signature is compared with the output
of the MISR and determine whether it matches with the golden signature
stored. Based on this a pass/fail output would be generated.

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PROBLEM STATEMENT
Design and simula on of 1 bit Full Adder with complete BIST func onality.
Specifica ons :
4bit MISR for Output Response Analyzer (ORA).
3bit LFSR for Test Pa ern Genera on.
1 bit Full Adder CUT
Design of BIST controller

CIRCUIT UNDER TEST (CUT)

The CUT is a 1- bit full adder. Faults have been injected at 3 points in the design
i.e a@0, sum@1, r@0. The response from the MISR is compared with the
golden signature to check whether the fault is detected or goes undetected.

CODE:
module full_adder(
input a,
input b,
input cin,
output[1:0] dataIn );
parameter f_1 = 1'b0; // a stuck at 0
parameter f_2 = 1'b0; // r stuck at 0

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parameter f_3 = 1'b0; // sum stuck at 1
wire p,q,r,a11,r1,sum1,sum,cout;
and f1(a11,~f_1,a);
xor x1(p,a11,b);
and a1(r,a11,b);
xor x2(sum1,p,cin);
or f3(sum,sum1,f_3);
and a2(q,p,cin);
and f2(r1,r,~f_2);
or o1(cout,q,r1);
assign dataIn = {sum,cout};
endmodule

TEST BENCH:
module CUT_tb;
reg a,b,cin;
wire sum,cout;

full_adder dut(a,b,cin,sum,cout);

ini al begin
a=1'b0;b=1'b0;cin=1'b0;
#10 a=1'b0;b=1'b0;cin=1'b1;
#10 a=1'b0;b=1'b1;cin=1'b0;
#10 a=1'b0;b=1'b1;cin=1'b1;
#10 a=1'b1;b=1'b0;cin=1'b0;
#10 a=1'b1;b=1'b0;cin=1'b1;
#10 a=1'b1;b=1'b1;cin=1'b0;
#10 a=1'b1;b=1'b1;cin=1'b1;
end
ini al begin #80 $finish; end
endmodule

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SIMULATION RESULTS:

TEST PATTERN GENERATOR (TPG) - 3 BIT LFSR USING PRIMITIVE POLYNOMIAL

Polynomial Equa on : 1 + x + x3

The LFSR has been seeded to 001. The LFSR has period of 7 (= 23 -1)
Next State Equa ons:
Q0* = Q2
Q1* = Q0 + Q2
Q2* = Q1

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Test Pa erns generated

Q0 Q1 Q2
0 0 1
1 1 0
0 1 1
1 1 1
1 0 1
1 0 0
0 1 0

VERILOG CODE:
module ML_lfsr(data_out, complete, reset, clock);

input reset;

input clock;

output [0:2] data_out;

output reg complete;

reg [0:2] lfsr_reg;

reg [2:0] counter;

always@(posedge clock or posedge reset)

begin

if(reset == 1)

begin

lfsr_reg <= 9'b001;

counter <= 3'b000;

end

else

begin

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 lfsr_reg[0] <= lfsr_reg[2];

lfsr_reg[1] <= lfsr_reg[0] ^ lfsr_reg[2];

lfsr_reg[2] <= lfsr_reg[1];

counter = counter + 1;

if(counter <= 3'b110)

complete = 0;

else

complete = 1;

end

end

assign data_out = lfsr_reg;

endmodule

TEST BENCH:
module tb_ML_lfsr;

reg clock,reset;

wire [0:2] dt_out;

wire [0:2] counter;

ML_lfsr lfsr1(dt_out, complete, reset, clock);

ini al

begin

clock = 1'b0;

end

always

#5 clock = ~clock;

ini al

begin

reset = 1'b1;

#10 reset = 1'b0;

end

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always #100 $finish;

endmodule

SIMULATION RESULTS:

OUTPUT RESPONSE ANALYZER (ORA) - 4BIT MISR

Polynomial Equa on : 1 + x + x4

NEXT STATE EQUATIONS

Q0* = Sum + Q3
Q1* = Cout + Q1 + Q3
Q2* = Q1
Q3* = Q2

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VERILOG CODE:
module MISR_4bit(dataIn,reset,clock,dataOut);

input [0:1] dataIn;

input reset,clock;

output reg [0:3] dataOut;

always@(posedge clock or posedge reset)

begin

if(reset == 1)

dataOut <= 4'b0000;

else

begin

dataOut[0] <= dataOut[3] ^ dataIn[0];

dataOut[1] <= dataOut[3] ^ dataOut[1] ^ dataIn[1];

dataOut[2] <= dataOut[1] ;

dataOut[3] <= dataOut[2] ;

end

end

endmodule

TEST BENCH:
module MISR_4bit_tb;

reg clock,reset;

wire [3:0] dataOut;

reg [1:0] dataIn;

MISR_4bit dut(.dataIn(dataIn),.reset(reset),.clock(clock),.dataOut(dataOut));

ini al

begin

clock = 1'b0;

end

always

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#5 clock = ~clock;

ini al

begin

reset = 1'b1;

#10 reset = 1'b0;

dataIn = 2'b10;

#10 dataIn = 2'b01;

#10 dataIn = 2'b01;

#10 dataIn = 2'b11;

#10 dataIn = 2'b01;

#10 dataIn = 2'b10;

#10 dataIn = 2'b10;

#20 $finish;

end

endmodule

SIMULATION RESULTS:

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BIST CONTROLLER DESIGN
VERILOG CODE:
module controller_new(clock,reset,w,x,y,data_out,dataIn ,dataOut,testmode, fault_detected);

input clock,reset,testmode;

input w,x,y; // a,b and cin

output [2:0] data_out; // lfsr output

output [1:0] dataIn; // Misr input

output [3:0] dataOut; // Misr output

output reg fault_detected;

wire a,b,cin;

wire finish;

parameter golden_signature = 4'b0011;

assign {a,b,cin} = (testmode == 1)? (data_out[2:0]) : ({w,x,y});

ML_lfsr I1(data_out, finish, reset, clock);

full_adder I2(a,b,cin,dataIn); //dataIn is {sum,cout} of full adder

MISR_4bit I3(dataIn, reset, clock,dataOut);

always @(posedge clock)

begin

if(testmode == 0) //when bist mode is not on, faults can't be detected

fault_detected = 0;

else

begin

if(finish == 1)

begin

if(golden_signature == dataOut)

fault_detected = 0;

else

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 fault_detected = 1;

end

end

end

endmodule

TEST BENCH:
module tb_controller_new;

// Inputs

reg clock;

reg reset;

reg w,x,y;

reg testmode;

// Outputs

wire [2:0] data_out;

wire [1:0] dataIn;

wire [3:0] dataOut;

controller_new uut (

clock,reset,w,x,y,data_out,dataIn ,dataOut,testmode, fault_detected);

ini al begin

clock = 0;

reset = 1;

w = 1; x=1; y=1;

testmode = 0;

end

always #5 clock = !clock;

ini al begin

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 #10 reset =1'b0;

testmode =1'b1;

end

always #120 $finish;

endmodule

OUTPUT WAVEFORM FOR FAULT FREE OPERATION:

Sum Cout Q0 Q1 Q2 Q3

1 0 0 0 0 0
0 1 1 0 0 0
0 1 0 1 0 0
1 1 0 0 1 0
0 1 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1

Golden Signature 0 0 1 1

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OUTPUT WAVEFORM FOR FAULT a@0:

Sum Cout Q0 Q1 Q2 Q3

1 0 0 0 0 0
0 1 1 0 0 0
0 1 1 0 0 0
1 1 0 1 0 0
0 1 0 0 1 0
1 0 1 0 0 1
1 0 1 1 0 0

Faulty Signature (a@0) 1 1 1 0

The faulty signature 1110 is different from the golden signature 0011 and
hence the fault a@0 is ge ng detected.

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OUTPUT WAVEFORM FOR FAULT r@0:

Sum Cout Q0 Q1 Q2 Q3

1 0 0 0 0 0
0 1 1 0 0 0
0 1 0 0 0 0
1 1 0 1 0 0
0 1 1 1 1 0
1 0 0 0 1 1
1 0 0 1 0 1

Faulty Signature (r@0) 0 0 1 0

The faulty signature 0010 is different from the golden signature 0011 and
hence the fault r@0 is ge ng detected.

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 OUTPUT WAVEFORM FOR FAULT sum@1:

Sum Cout Q0 Q1 Q2 Q3

1 0 0 0 0 0
1 1 1 0 0 0
1 1 1 1 0 0
1 1 1 0 1 0
1 1 1 1 0 1
1 0 0 1 1 0
1 0 1 1 1 1

Faulty Signature (sum@1) 0 0 1 1

The faulty signature is matching with the golden signature 0011 and hence
the fault sum@1 is undetected.

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CONCLUSION
BIST verifies all or a por on of the internal func onality of the IC. It is
becoming an integral part of many me cri cal circuits recently. In this
experien al learning assignment, a complete BIST design was implemented for
full adder which included Output Response Analyzer (ORA) , Test Pa ern
Generator.
The faults were injected in the Circuit Under Test and analysis was done
whether the BIST is able to detect the faults.
The simula on results obtained were verified with hand calcula ons.

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