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Assignment 4

The document outlines a series of questions related to logic synthesis, physical synthesis, and chip design, covering topics such as assumptions at the logic synthesis stage, commands used in Design Compiler (DC), and the differences between link_library and target_library. It also addresses the usage of IO pads, challenges in IO placement, and common packaging techniques. Additionally, the document includes a practical assignment to draw an initial floorplan and calculate the required area for a given IP design.

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Serajeldeen Ghalyoub 201-801-104
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11 views4 pages

Assignment 4

The document outlines a series of questions related to logic synthesis, physical synthesis, and chip design, covering topics such as assumptions at the logic synthesis stage, commands used in Design Compiler (DC), and the differences between link_library and target_library. It also addresses the usage of IO pads, challenges in IO placement, and common packaging techniques. Additionally, the document includes a practical assignment to draw an initial floorplan and calculate the required area for a given IP design.

Uploaded by

Serajeldeen Ghalyoub 201-801-104
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment 4

Islam Ahmed
1- What are the assumptions we make at logic synthesis stage? What design aspects do we address as well?
2- What commands used in DC for:
• Translation
• Optimization
• Choosing a specific metric to be prioritized.
• Reporting violating endpoints
• Reporting total area
3- What is the difference between link_library and target_library? What commands will be reffering to target_library
.dbs?
4- What are .tluplus files? How they are used in physical synthesis?
5- What is technology file? What corresponds to it to non-Synopsys physical synthesis tools?
6- What views do we need to model a macro in ICC?
7- What is the usage of: core area, site rows, wire tracks?
8- What is the usage of IO pads in chip design?
9- What are the types of IO pads usually provided in any IO library?
10- What is the challenge associated with IO placement? What are the common strategies used for IO placement?
11- What is the difference between core-limited and pad-limited designs? What IO placement strategies can be used
for pad-limited designs to avoid increased die are and increased cost accordingly?
12- What are the common packaging techniques what are the benefits of flop-chip packaging over wirebond
packaging?
13- What are the assumptions we make at logic synthesis stage? What design aspects do
we address as well?
14- What are .tluplus files? How they are used in physical synthesis?
15- What is technology file? What corresponds to it to non-Synopsys physical synthesis
tools?
16- What views do we need to model a macro in ICC?
17- What is the usage of: core area, site rows, wire tracks?
18- What is the usage of IO pads in chip design?
19- What are the types of IO pads usually provided in any IO library?
20- What is the challenge associated with IO placement? What are the common strategies
used for IO placement?
21- What is the difference between core-limited and pad-limited designs? What IO
placement strategies can be used for pad-limited designs to avoid increased die are and
increased cost accordingly?
22- What are the common packaging techniques what are the benefits of flop-chip
packaging over wirebond packaging?
Please draw an initial floorplan and calculate the required area
accordingly for your IP; knowing that:
You usually have a total area of 125,000 um2 after synthesis.
You have 1 analog Macro with area of: 400um*400um, required to have a
blockage surrounding it by 20um from all sides.
Required initial floorplan utilization is 35%.

[Hint review floorplanning slides and macro placement guidelines]

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