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Assignment 2

The document outlines various questions and exercises related to Static Timing Analysis (STA) and its comparison with logic simulation, including the identification of timing paths, setup and hold requirements, and the modeling of external delays. It also discusses concepts such as clock skew, propagation time, and maximum clock frequency, along with practical exercises for calculating delays and checking for setup or hold violations. Additionally, it emphasizes the importance of specifying false paths and understanding multi-cycle paths for optimization and analysis.

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Serajeldeen Ghalyoub 201-801-104
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6 views9 pages

Assignment 2

The document outlines various questions and exercises related to Static Timing Analysis (STA) and its comparison with logic simulation, including the identification of timing paths, setup and hold requirements, and the modeling of external delays. It also discusses concepts such as clock skew, propagation time, and maximum clock frequency, along with practical exercises for calculating delays and checking for setup or hold violations. Additionally, it emphasizes the importance of specifying false paths and understanding multi-cycle paths for optimization and analysis.

Uploaded by

Serajeldeen Ghalyoub 201-801-104
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment 2

Islam Ahmed
1- What are the main inputs and outputs of STA?
2- Please compare STA to logic simulation, listing the pros and cons of each of them.
3- Do you think we should run ONLY STA, or ONLY simulation? Or we have to run both?
4- Write down the inequalitys that has to be satisfied to satisfy setup and hold
requirements.
5- If you have 2 values for each of: Tcomb, Tskew, Tclk2q. Please rewrite the setup and
hold inequalities with annotating each parameter with min or max, to specify most
pessimistic analysis that is followed by STA tools.
6- How do we model external top-level design delays, while developing the block in-hand,
so that when merging our design into top-level no setup-hold violations are reported?
7- Why do we have to specify false paths for optimization and analysis tools?
8- What is a multi-cycle path?
9- How do we estimate interconnect parasitics at logic synthesis? [Please Google it]
• What is clock skew, propagation time, clk-to-q time, setup time?
• What is the max. clock frequency that can be used?
• What is clock skew, propagation time, clk-to-q time, setup time?
• What is the max. clock frequency that can be used?
Exercise
1. Identify all timing paths [assume i/p delay constraint = 0.3ns]
2. Calculate max. clock frequency

Setup requirement = 0.4 ns


for both FF’s
Exercise: Is there any setup or hold violation in this
circuit?

Assume i/p delay constraint = 0.3ns


Exercise 0.3n 0.3ns
Setup Time
s Requirement
TO_BE_SYNTHESIZED

D Q M N D Q X D Q S T D Q
FF1 FF2 FF3 FF4
QB QB

Clk
Tclk= 2ns
■ set_output_delay –max:
● Describes the maximum time requirement of the external logic on the output ports
Note: we should make sure that our design helps the assumed FF outside the block to
meet its setup requirements! By choosing the appropriate value for
max_output_delay
If FF has TSETUP = 0.3ns and TT = 0.3ns:
What is the max output_delay?

24
Constraining Input Paths: Example 1
Spec:
Latest Data Arrival Time at Port A, after Jane’s launching clock edge = 0.6ns
mydesign.con
create_clock -period 2 [get_ports Clk] set_input_delay -max 0.6
-clock Clk [get_ports A]

MY_DESIGN
JANE’s_DESIGN TSetup, FF2
0.2ns
Tmax
A
D Q M N D Q X D Q S
FF1 FF2 FF3
0.6ns
QB QB QB

Clk

What is the maximum delay Tmax for the input path N in

MY_DESIGN? __________________________
Constraining Output Paths : Example 1
Spec:
Latest Data Arrival Time at Port B, before Joe’s capturing clock = 0.8ns mydesign.con

create_clock -period 2 [get_ports Clk] set_input_delay -max 0.6


-clock Clk [get_ports A]
set_output_delay -max 0.8 -clock Clk [get_ports B]

JOE’s_DESIGN
MY_DESIGN TT + Tsetup
Tmax 0.7ns 0.1ns
B
N D Q X D Q S T D Q
FF2 FF3 FF4
QB QB QB
Clk

What is the maximum delay Tmax for the output path through

S in MY_DESIGN? __________________________

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