Why Microcontroller?

Purpose ?
 Microcontroller
• Microcontrollers are important part of
Embedded systems
• To understand Structure & working of
Microcontrollers
• For Designing good Embedded system
complete understanding of
microcontrollers required
Microcontroller
Integrated chip that typically contains integrated CPU,
memory (RAM ROM), I/O ports on a single Chip.

System on a single Chip

Designed to execute a specific task to control a single

system

Smaller & Specified (design cost)

Differs from Microprocessor
general-purpose chip
Used to design multi purpose computers or devices
Require Multiple chips to to handle various tasks
 General Purpose Microprocessors vs. Microcontrollers
● General Purpose Microprocessors

● Microcontrollers
CPU RAM ROM
Serial
Timer I/O
Port
 Microprocessor vs. Microcontroller
Microprocessor Microcontroller
● CPU is stand-alone, RAM, ROM, I/O, ● CPU, RAM, ROM, I/O and timer are all
timer are separate on a single chip

● Designer can decide on the amount of ● Fix amount of on-chip ROM, RAM, I/O
ports
ROM, RAM and I/O ports.

● Not Expansive
● Expansive
● For applications in which cost, power
● Versatility and space are critical

● General-purpose ● Single-purpose
 Microcontrollers

A microcontroller
interfaces to
external devices
with a minimum of
external
components
 Most common microcontrollers
● 8-bit microcontrollers

○ AVR

○ PIC

○ HCS12

○ 8051

● 32-bit microcontrollers

○ ARM

○ PIC32
 Intel 51 family (8-bit MC)
● 8051

○ 40 pin DIP

○ 4K ROM

○ 128 byte Data Memory

○ 32 I/O lines

○ Two 16-bit Timer

○ 5 Interrupt

○ UART

○ Support external 60K program memory

○ Support external 64K data memory

 Pin Description of the 8051
● 8051 family members (e.g., 8751, 89C51, 89C52, DS89C4x0)

○ Have 40 pins dedicated for various functions such as I/O, RD, WR, address, data, and interrupts.

○ Come in different packages, such as

■ DIP(dual in-line package),

■ QFP(quad flat package), and

■ LLC(leadless chip carrier)

● Some companies provide a 20-pin version of the 8051 with a reduced number of I/O
ports for less demanding applications
Pin Diagram of the 8051
 XTAL1 and XTAL2
● The 8051 has an on-chip oscillator but requires an external clock to run it

○ A quartz crystal oscillator is connected to inputs XTAL1 (pin19) and XTAL2 (pin18)

○ The quartz crystal oscillator also needs two capacitors of 30 pF value

 XTAL1 and XTAL2 …..
● If you use a frequency source other than a crystal oscillator, such as a TTL oscillator:

○ It will be connected to XTAL1

○ XTAL2 is left unconnected

 XTAL1 and XTAL2 …..
● The speed of 8051 refers to the maximum oscillator frequency connected to
XTAL.

● We can observe the frequency on the XTAL2 pin using the oscilloscope.
 RST
● RESET pin is an input and is active high (normally low)
● Upon applying a high pulse to this pin, the microcontroller will reset and
terminate all activities
● This is often referred to as a power-on reset
● Activating a power-on reset will cause all values in the registers to be lost
 RST
● In order for the RESET input to be effective, it must have a minimum duration
of 2 machine cycles.

● In other words, the high pulse must be high for a minimum of 2 machine
cycles before it is allowed to go low.
 EA’
● EA’, “external access’’, is an input pin and must be connected to
Vcc or GND

● The 8051 family members all come with on-chip ROM to store
programs and also have an external code and data memory.

● Normally EA pin is connected to Vcc

● EA pin must be connected to GND to indicate that the code or

data is stored externally.
 8051 Memory Structure

External

External
60
K
64 64
K K
SFR
EXT INT 4K
128
EA = 0 EA = 1
Program Memory Data Memory
 PSEN’ and ALE
● PSEN, “program store enable’’, is an output pin

● This pin is connected to the OE pin of the external memory.

● For External Code Memory, PSEN’ = 0

● For External Data Memory, PSEN’ = 1

● ALE pin is used for demultiplexing the address and data.

 I/O Port Pins
● The four 8-bit I/O ports P0, P1, P2 and
P3 each uses 8 pins.

● All the ports upon RESET are

configured as output, ready to be used
as input ports by the external device.
 Port 0
● Port 0 is also designated as AD0-AD7.

● When connecting an 8051 to an external memory, port 0 provides

both address and data.

● The 8051 multiplexes address and data through port 0 to save pins.

● ALE indicates if P0 has address or data.

○ When ALE=0, it provides data D0-D7

○ When ALE=1, it has address A0-A7

 Port 1 and Port 2
● In 8051-based systems with no external memory
connection:

○ Both P1 and P2 are used as simple I/O.

● In 8051-based systems with external memory connections:

○ Port 2 must be used along with P0 to provide the 16-bit address for the
external memory.

○ P0 provides the lower 8 bits via A0 – A7.

○ P2 is used for the upper 8 bits of the 16-bit address, designated as A8 – A15,
and it cannot be used for I/O.
 Port 3
● Port 3 can be used as input or output.

● Port 3 has the additional function of

providing some extremely important
signals
 Pin Description Summary
PIN TYPE NAME AND FUNCTION
Vss I Ground: 0 V reference.
Vcc I Power Supply: This is the power supply voltage for normal, idle, and
power-down operation.
P0.0 - P0.7 I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 is also the
multiplexed low-order address and data bus during accesses to external
program and data memory.
P1.0 - P1.7 I/O Port 1: Port I is an 8-bit bi-directional I/O port.

P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the high order address
byte during fetches from external program memory and during accesses to
external data memory that use 16 bit addresses.
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also serves special
features as explained.
 Pin Description Summary
PIN TYPE NAME AND FUNCTION
RST I Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device.
ALE O Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory.
PSEN* O Program Store Enable: The read strobe to external program memory. When
executing code from the external program memory, PSEN* is activated twice
each machine cycle, except that two PSEN* activations are skipped during each
access to external data memory.
EA*/VPP I External Access Enable/Programming Supply Voltage: EA* must be externally
held low to enable the device to fetch code from external program memory
locations. If EA* Is held high, the device executes from internal program
memory. This pin also receives the programming supply voltage Vpp during
Flash programming. (applies for 89c5x MCU's)
General Block Diagram of 8051
Interrupt 4K 128 B Timer 0
Control ROM Timer 1
RAM

CPU

Bus Serial
OSC Control
4 I/O Ports
Port

TXD RXD
P0 P1 P2 P3
 SECTION 2.1: INSIDE THE 8051
• Registers

Figure 2–1a
Some 8-bit Registers of the 8051
 SECTION 2.1: INSIDE THE 8051
• Registers

Figure 2–1b Some 8051 16-bit Registers

 SECTION 2.1: INSIDE THE 8051
• most widely used registers are A, B, R0, R1,
R2, R3, R4, R5, R6, R7, DPTR and PC
• all registers are 8-bits, except DPTR and the
program counter which are 16 bit
• register A is used for all arithmetic and logic
instructions
• simple instructions MOV and ADD
 SECTION 2.4: THE PROGRAM COUNTER AND ROM
SPACE IN THE 8051
• Program counter in the 8051
– 16 bits wide
– can access program addresses 0000 to FFFFH
– total of 64K bytes of code
 SECTION 2.4: THE PROGRAM COUNTER AND ROM
SPACE IN THE 8051
• Where the 8051 wakes up when it is powered
up:
– wakes up at memory address 0000 when it is
powered up
– first opcode must be stored at ROM address
0000H
 SECTION 2.4: THE PROGRAM COUNTER AND ROM
SPACE IN THE 8051
• Placing code in program ROM
– the opcode and operand are placed in ROM
locations starting at memory 0000
 SECTION 2.4: THE PROGRAM COUNTER AND ROM
SPACE IN THE 8051

• ROM memory map in the 8051 family

Figure 2–3 8051 On-Chip ROM Address Range

 Program Status Word [PSW]

C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1
User Flag 0 Register Bank Select Overflow
 128 Byte RAM
• There are 128 bytes of RAM in the 8051.
– Assigned addresses 00 to 7FH General Purpose
Area
• The 128 bytes are divided into 3 different
groups as follows: BIT Addressable
1. A total of 32 bytes from locations 00 to 1F hex are 128Area
BYTE
set aside for register banks and the stack. INTERNAL
Reg Bank 3
RAM
2. A total of 16 bytes from locations 20H to 2FH are
set aside for bit-addressable read/write memory. Register
Reg Bank 2
3. A total of 80 bytes from locations 30H to 7FH are Banks
Reg Bank 1
used for read and write storage, called scratch Reg Bank 0
pad.
8051 RAM with addresses
 8051 Register Bank Structure

Bank 3 R0 R1 R2 R3 R4 R5 R6 R7

Bank 2 R0 R1 R2 R3 R4 R5 R6 R7

Bank 1 R0 R1 R2 R3 R4 R5 R6 R7

Bank 0 R0 R1 R2 R3 R4 R5 R6 R7
8051 Register Banks with address
SECTION 2.7: 8051 REGISTER BANKS AND STACK
• How to switch register banks

Table 2–2 PSW Bits Bank Selection

 8051 Stack
• The stack is a section of RAM used by the CPU to store
information temporarily.
– This information could be data or an address

• The register used to access the stack is called the SP (stack

pointer) register
– The stack pointer in the 8051 is only 8 bit wide, which means that it
can take value of 00 to FFH
– When the 8051 is powered up, the SP register contains value 07
– RAM location 08 is the first location begin used for the stack by the
8051
 8051 Stack
• The storing of a CPU register in the stack is called a PUSH
– SP is pointing to the last used location of the stack
– As we push data onto the stack, the SP is incremented by one and
store the value
– This is different from many microprocessors

• Loading the contents of the stack back into a CPU register is

called a POP
– With every pop, the top byte of the stack is copied to the register
specified by the instruction and the stack pointer is decremented
once