Assignment - ESP-VI
Assignment - ESP-VI
QB
Sr. Question Question Marks
No.
Define a binary search tree (BST)
2
1 and explain its key properties.
Explain the difference between a
binary tree and a binary search tree 2
2 (BST). Provide an example of each.
Discuss the advantages and
disadvantages of a singly linked list
2
compared to an array. Provide
3 specific examples for each.
Explain the concept of enqueue
2
4 and dequeue operations in a queue.
#define f(a,b) a+b
#define g(a,b)a*b
main()
{
int m; 2
m=2*f(3,g(4,5));
printf("\n m is %d", m);
}
5 What is the value of m?
How many different types of trees
that can be realized are with six 2
6 nodes?
Consider the following C
declaration
struct {
short s [5]
union{
float y; 2
long z;
}u;
}t;
What is the memory requirement
7 for variable t?
Find the maximum number of
binary trees that can be formed 2
8 with three unlabeled nodes.
Suppose the numbers 7, 5, 1, 8, 3,
6, 0, 9, 4, 2 are inserted in that
order into an initially empty binary
search tree. The binary search tree
uses 2
the usual ordering on natural
numbers. What is the inorder
traversal sequence of the resultant
9 tree?
Find the number of pointers
affected for an insertion operation 2
10 in a doubly linked list.
The function of the given Linked
List with the first node as the head
is:-
void funx1(struct node* head)
{
if (head == NULL)
2
return;
funx1 (head -> next) ;
printf (" %d ", head -> data ) ;
}
2
20 Define hit ratio.
A computer has 1GB of memory. Each
word in the computer is 32 bits. How
2
many bits are needed to address any
21 single word in the memory?
2
29 What is database normalization?
2
33 What is Identity?
35 2
What is a Trigger?
36 2
What is a stored procedure?
37 2
What are ACID properties?
39 2
What is Denormalization?
What is the difference between a
40 database schema and a database 2
state?
(i) >
(ii) > -2
(iii) =
(iv) =
(i)
where
(ii) { | m = n and p = q,
where
(iii) { | m = n = p, p q,
52 2
where
(iv) { | mn = p + q,
where
2
81 What is an instruction cycle?
2
82 What is the function of ALU?
2
86 Define pipelining in a processor.
2
87 What is cache memory?
2
93 Convert (47.625)₁₀ into binary.
Part B
QB
Question
Sr. Question
Marks
No.
Let T(n) be the number of different binary
search trees on n distinct elements. Then
5
Analyze the value of x ?
1
Find the postfix expression for the infix expression
5
2 A + B * (C + D)/E + F * G.
Postorder traversal of a given binary search tree T
produces the following sequence of keys
5
10, 9, 23, 22, 27, 25, 15, 50, 95, 60, 40, 2. Find the
3 inorder traversal of the tree T?
The following postfix expression with single-digit
operands is evaluated using a stack: 5
4 823∧ /23*+51*−
Note that ∧ is the exponentiation operator. Find
the top two elements of the stack after the first *
is evaluated.
Analyze the value printed by the following C
program?
#include <stdio.h>
int f(int * a, int n)
{
if (n<= 0)return 0;
else if(*a% 2= = 0)
return * a + f(a
+1,n - 1);
else return * a - 5
f(a + 1, n - 1);
}
int main( )
{
int a[ ] = {12, 7,
13, 4, 11, 6};
printf("%d",f(a,6));
return 0;
5 }
Analyze the value printed by the following C
program?
# include <stdio.h>
int fun(int n, int * f_p) {
int t, f;
if (n <= 1) {
* f_p =1;
return 1;
}
t = fun (n - 1, f_p);
f = t+ * f_p;
* f_p = t;
return f;
}
int main() {
int x = 15;
printf (" % d\ n", fun(5, & x));
6 return 0;
}
Consider the following C program that attempts
to locate an element x in an array Y[ ] using binary
search. The program is erroneous.
1. f(int Y[10], int x) {
2. int u, j, k;
3. i = 0; j = 9;
4. do {
5. k = (i + j) / 2;
6. if (Y[k] < x) i = k;
else j = k; 5
7. } while ((Y[k]! = x) &&
(i < j));
8. if (Y [k] == x) print f ("x is in
the array");
9. else print f ("x is not in the
array");
10. }
Analyze where the correction needed in the
7 program to make it work properly.
The preorder traversal of a binary search tree is
15, 10, 12, 11, 20, 18, 16, 19. Evaluate post-order 5
8 traversal.
9 Write an algorithm to reverse a singly linked list 5
Write an algorithm to delete an element from a
5
10 singly linked list if the item available in the list.
Write an algorithm to sort a singly linked list in
descending order. Assume numbers in the list are 5
11 random.
Suppose a circular queue of capacity (n – 1)
elements is implemented with an array of n
elements. Assume that the insertion and deletion
operation are carried out using REAR and FRONT
5
as array index variables, respectively. Initially,
REAR = FRONT = 0. Write down the algorithm
to detect whether the queue is full and queue
12 empty.
Consider a hash table with 100 slots. Collisions
5
13 are resolved using chaining. Assuming simple
uniform hashing. Calculate the probability, so that,
the first 3 slots are unfilled after the first 3
insertions.
A computer uses RAM chips of 1024 x 1 capacity.
How many chips are needed to provide a memory 5
14 capacity of 16K bytes?
A 4-way set-associative cache memory uses
blocks of four words. The cache can accommodate
a total of 1024 words from the main memory. The
5
main memory size is 128K×32. Formulate all
pertinent information required to construct the
15 cache memory.
Consider a memory hierarchy system containing a
cache, a main memory and a virtual memory.
Assuming, cache access time of 4 ns, and 70% hit
ratio. The access time of the main memory is 100 ns, 5
and it has a 99.5% hit rate. The access time of the
virtual memory is 10 ms. Calculate the average access
16 time of the memory hierarchy.
Suppose physical memory is of 2GB and each
word is of 16 bits. There is a cache containing 2K
words of data, and each cache block contains 16
5
words. For each of the direct mapped and 2-way
set associative cache configurations, specify how
17 the address would be partitioned.
Consider a direct mapped cache of size 32 KB
with block size 32 bytes. The CPU generates 32-
5
bit addresses. What are number of bits needed for
18 addressing block in cache and number of tag bits?
A main memory unit with a capacity of 4
megabytes is built using 1M × 1-bit DRAM chips.
Each DRAM chip has 1 K rows of cells with 1K
cells in each row. The time taken for a single 5
refresh operation is 100 ns. Calculate how much
time is uired to perform one refresh operation on
19 all the cells in the memory unit?
Consider a direct mapped cache of size 32KB with a
block size of 32 bytes. The CPU generates bit 5
20 addresses. What are the number of bits needed for
cache indexing and the number of tag bits,
respectively?
Create a DFA that recognizes strings over {a, b}
where the number of 'a's is one less than the 5
21 number of 'b's.
Devise a DFA that accepts strings over the
alphabet {0, 1} containing an even number of both 5
22 '0's and '1's.
Consider the context-free grammar G below:
S --> aSb | X
X --> aX | Xb | a | b
23
Consider the language L over the alphabet {0, 1},
given below:
24
3. Comment on whether the following are
decidable or undecidable. Explain your
answer with the definition of undecidable
problem.
Part C
QB
Question
Sr. Question
Marks
No.
A priority queue is implemented as a max-heap.
Initially, it has five elements. The level-order
traversal of the heap is given below: 10
10, 8, 5, 3, 2. Two new elements `1’ and `7’ are
1 inserted in the heap in that order. Evaluate the
level-order traversal of the heap after the
insertion of the elements.
10
6
Create an AVL tree by the following elements
in Lexicographic order: Jan, Feb, Mar, Apr,
10
May, Jun, Jul, Aug, Sep, Oct, Nov & Dec. Show
7 balance factors after insertion of each element.
Consider a sequence a of elements a0 = 1, a1 = 5,
a2 = 7, a3 = 8, a4 = 9, and a5 = 2.
The following operations are performed on a
stack S and a queue Q, both of which are initially
empty.
I: push the elements of a from a0 to a5 in that
order into S.
II: enqueue the elements of a from a0 to a5 in that
order into Q. III: pop an element from S.
IV: dequeue an element from Q. V: pop an
element from S. 10
VI: dequeue an element from Q.
VII: dequeue an element from Q and push the
same element into S. VIII: Repeat operation VII
three times.
IX: pop an element from S. X: pop an element
from S.
Show the stack and the queue at each intermediate
step.
8
The access time of a cache memory is 100 ns and
that of main memory is 1000 ns. It is estimated
that 70% of the memory requests are for read
and remaining 30% for write. The hit ratio for
read accesses only is 0.9. A write-through
procedure is used.
10
(a) What is the average access time of the system
considering only memory read cycles?
(b) What is the average access time of the system
for both read and write requests?
(C) What is the hit ratio taking into consideration
9 the write cycles also?
Consider a 2-way set associative cache
consisting of 256 blocks of 8 words each, and 10
10 assume that the main memory is addressable by
16-bit address and it consists of 4K blocks.
Calculate the number of bits in each of the TAG,
BLOCK/SET and word fields for different
mapping techniques?
A computer employs RAM chips of 256 × 8 and
ROM chips of 1024 × 16. The computer system
needs 2K bytes of RAM and 4K bytes of ROM
and four interface units each with four registers. 10
Draw a memory address map for the system and
give the address range in hexadecimal for RAM
11 and ROM chips.
A 4-way set-associative cache memory uses
blocks of four words. The cache can
accommodate a total of 1024 words from the
main memory. The main memory size is 128K ×
10
32.
(a) Formulate all pertinent information required
to construct the cache memory.
12 (b) What is the size of the cache memory?
Design a Turing machine to determine if a given
10
13 string is a palindrome.
Create a Turing machine to recognize the
language of all strings over {a, b} where the
10
number of occurrences of 'a' is twice the number
14 of occurrences of 'b'.
Create a Turing machine that computes the
10
15 Fibonacci sequence given an input number n.
Design a PDA to recognize the language of
balanced parentheses, where strings consist of '(' 10
16 and ')' symbols and are properly nested.
Implement a Turing machine that computes the
addition of two unary numbers represented as 10
17 strings of consecutive '1's.
A system has a writethrough cache with access
time of 100 ns and hit ratio of 90%. The main
memory access time is 500ns. 70% of memory
18 references are for read operations. Find out 10
average memory access time for read operations
only, Average memory access time for write
operations only, Average memory access time
for read-write operations both and Effective hit
ratio.
CPU referred to access the cache memory 200 times,
among them Cache hit is occurred for 160 times and
Cache miss is occurred for 40 times. For each hit
19 CPU requires 10 ns and for each miss CPU requires 10
100 ns. What will be the average memory access time
for CPU to access Cache memory? Explain the
working principle of Cache memory.
34 name-> rollNo 10
rollNo-> name
What is the highest normal form of this relation
scheme (Student_Performance). Justify your
answer with proper explanation?