MODULE II MEMORY AND PROGRAMMABLE LOGIC 8

Introduction - Basic memory structure – ROM -PROM – EPROM – EEPROM, RAM –

Static and dynamic RAM – Programmable Logic Devices – Programmable Logic
Array (PLA) – Programmable Array Logic (PAL) – Field Programmable Gate Arrays
(FPGA) – Implementation of combinational logic circuits using PLA, PAL. Types of
Memories, Memory Decoding, error detection and correction, RAM and ROMs.
Programmable Logic Array, Programmable Array Logic, Sequential Programmable
Devices.
Topics yet to be covered

I. Sequential Programmable Devices - Field Programmable Gate Arrays (FPGA)

II. RAM – Static and dynamic RAM
III. Memory Decoding
IV. Error detection and correction
I. Sequential Programmable Devices
● include both gates and flip flops
● 3 types
a. SPLD (Simple / Sequential Programmable Devices)
b. CPLD (Complex Sequential Programmable Devices)
c. FPGA (Field Programmable Gate Array)
● is a combinational PAL together with D flip flops. a. SPLD
Ex. 2 input 5 wide PAL
● Each section of an SPLD is called a macrocell,
which is a circuit that contains a sum-of-products
combinational logic function and an optional
flip-flop.
● A typical SPLD has 8 to 10 macrocells within one
IC package. All the flip-flops are connected to the
common CLK input, and all three-state buffers are
controlled by the OE input.
● In addition to programming the AND array, a
macrocell may have other programming features.
○ the ability to either use or bypass the flip-flop,
○ the selection of clock edge polarity (+ or -)
○ the selection of preset and clear for the
register
○ the selection of the true value or complement macrocell
of an output.
● Consists of multiple SPLDs interconnected
b. CPLD
through a programmable switch matrix.
● The input–output (I/O) blocks provide the S S S S
connections to the IC pins.
● Each I/O pin can be programmed to act as
input or output.
● The switch matrix receives inputs from the I/O
block and directs them to the individual
macrocells.
● Similarly, selected outputs from macrocells are
sent to the outputs as needed.
● Each SPLD typically contains from 8 to 16
macrocells, usually fully connected.
● In some cases the macrocell flip-flop is S S S S
programmed to act as a D, JK, or T flip-flop.
 c. FPGA
● A field-programmable gate array (FPGA) is a VLSI circuit that can be programmed at the
user’s location.

● A typical FPGA consists of an array of millions of configurable logic blocks (CLB), surrounded
by programmable input and output blocks and connected together via programmable
interconnections. There is a wide variety of internal configurations within this group of devices.

● A typical FPGA logic block consists of lookup tables, multiplexers, gates, and flip-flops. A
lookup table is a truth table stored in an SRAM and provides the combinational circuit
functions for the logic block.
○ The advantage of using RAM instead of ROM to store the truth table is that the table can
be programmed by writing into memory.
○ The disadvantage is that the memory is volatile and presents the need for the lookup
table’s content to be reloaded in the event that power is disrupted.

● Xilinx launched the world’s first commercial FPGA in 1985

 Basic architecture of Xilinx Spartan
consists of
(i) an array of configurable logic blocks (CLBs)
Each CLB consists of
(a) a programmable lookup table
(b) multiplexers
(c) registers
(d) paths for control signals
(ii) a variety of local and global routing resources
The interconnect has three types of general
purpose interconnects:
(a) single-length lines
(b) double-length lines
(c) long lines
A grid of horizontal and vertical single-length
lines connects an array of switch boxes that
provide a reduced number of connections between
signal paths within each box
(iii) input–output (I/O) blocks (IOBs)
(iv) programmable I/O buffers
(v) an SRAM-based configuration memory
II. Basic memory structure
● Memory unit is a collection of storage cells, together with associated circuits needed to transfer
information into and out of the device.
● The process of storing new information into memory is called write operation. The process of
transferring the stored information out of memory is called read operation.
● The architecture of the memory is such that the information can be selectively retrieved from any of
its internal locations.
● ROM (Read Only Memory) can perform only read operation. i.e The binary information is already
stored inside the memory and it can be retrieved at any time.
● RAM (Random Access Memory) or R/W memory (Read-Write Memory) can perform both read and
write operations. The time it takes to read the binary information from any desired random location is
always same. Similarly the time it takes to write the binary information to any desired random
location is always same. Hence the name Random access memory. Whereas the time required to
retrieve the information that is stored in magnetic tape depends on the location of the data. therefore
magnetic tape comes under the classification of sequential access memory.
RAM
● Communication between memory and its environment
is achieved through
○ data input lines - n data input lines provide the
information to be stored in memory
○ data output lines -n data output lines supply the
information coming out of memory
○ address selection lines -k address lines specify the
particular word chosen among the many available
○ control lines that specify the direction of transfer
■ The Write input causes binary data to be
transferred into the memory
■ The Read input causes binary data to be
transferred out of memory.
● The 1K×16 memory has 10
bits in the address and 16
bits in each word.

● The number of bits in the

address is determined from
the relationship 2k≥m, where
m is the total number of
words and k is the number of
address bits needed to
satisfy the relationship.
Write and Read Operations
● The write signal specifies a transfer-in operation and the read signal specifies a transfer-out operation.
● steps for write operation
1. Apply the binary address of the desired word to the address lines.
2. Apply the data bits that must be stored in memory to the data input lines.
3. Activate the write input.
The memory unit will then take the bits from the input data lines and store them in the word
specified by the address lines.
● steps for read operation
1. Apply the binary address of the desired word to the address lines.
2. Activate the read input.
The memory unit will then take the bits from the word that has been selected by the address and apply
them to the output data lines. The contents of the selected word do not change after the read
operation, that is, the read operation is nondestructive.
 Types of Memories

Static RAM (SRAM) consists essentially of internal latches that store the binary information. The
stored information remains valid as long as power is applied to the unit.

Dynamic RAM (DRAM) stores the binary information in the form of electric charges on
capacitors provided inside the chip by MOS transistors. The stored charge on the capacitors tends to
discharge with time, and the capacitors must be periodically recharged by refreshing the dynamic
memory. DRAM offers reduced power consumption and larger storage capacity in a single memory
chip.

Memory units that lose stored information when power is turned off are said to be volatile. CMOS
integrated circuit RAMs, both static and dynamic, are of this category, since the binary cells need
external power to maintain the stored information. In contrast, a nonvolatile memory, such as
magnetic disk, ROM retain its stored information after the removal of power.
III. MEMORY DECODING
1. Internal Construction
2. Coincident Decoding
3. Address Multiplexing
 1. Internal Construction
● The binary storage cell is the basic building block of a
memory unit.
● The binary cell stores one bit in its internal latch.
● 3 inputs and 1 output
● The select input enables the cell for reading or writing,
and the read/write input determines the operation of
the cell when it is selected.
○ A 1 in the read/write input provides the read
operation by forming a path from the latch to the
output terminal. (S=0; R=0; previous output- read)
○ A 0 in the read/write input provides the write Binary Storage Cell or Binary Cell (BC)

operation by forming a path from the input terminal

to the latch. (Output =0; write)
Logical construction of RAM
● The internal construction of a RAM of m
words and n bits per word consists of
(i) m×n binary storage cells and
(ii) associated decoding circuits for selecting
individual words.
● This RAM consists of four words of four bits
each and has a total of 16 binary cells.
● The small blocks labeled BC represent the
binary cell with its three inputs (input data,
select, read/write) and one data output.
Logical construction of RAM ● A memory with four words needs two address
lines. The two address inputs go through a 2×4
decoder to select one of the four words.
● The decoder is enabled with the memory enable
input.
● When the memory enable is 0, all outputs of the
decoder are 0 and none of the memory words are
selected. The contents of all cells remain
unchanged regardless of the value of the
read/write input.
● When the memory enable is 1, one of the four
words is selected, dictated by the value in the two
address lines.
● Once a word has been selected, the read/write
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input determines the operation.
Logical construction of RAM

● During the read operation, the four bits of

the selected word go through OR gates to
the output terminals.
● During the write operation, the data
available in the input lines are transferred
into the four binary cells of the selected
word.
● The binary cells that are not selected are
disabled, and their previous binary values
remain unchanged.
 2. Coincident Decoding
● A decoder with k inputs and 2k outputs requires
2k AND gates with k inputs per gate.
● The 1K×16 memory has 10 (210=1024=1K) bits in
the address and 16 bits in each word.
● It requires 1024 AND gates with 10 inputs per gate.
● The total number of gates and the number of inputs
per gate can be reduced by employing two
decoders in a two-dimensional selection scheme.
● In this configuration, two k/2-input (5 input)
decoders are used instead of one k-input (10 input)
decoder.
● One decoder performs the row selection and the
other the column selection in a two-dimensional Two-dimensional decoding structure for
a 1K-word memory
matrix configuration.
 2. Coincident Decoding
● Instead of using a single 10×1024 decoder, two 5×32
decoders are used.
● With the single decoder, we would need 1,024 AND gates
with 10 inputs in each.
● In the two-decoder case, we need 64 AND gates with 5
inputs in each. The five most significant bits of the address
go to input X and the five least significant bits go to input Y.
● Each word within the memory array is selected by the
coincidence of one X line and one Y line. Thus, each word in
memory is selected by the coincidence between 1 of 32
rows and 1 of 32 columns, for a total of 1,024 words.
● Each intersection represents a word that may have any
number of bits.
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 2. Coincident Decoding
● As an example, consider the word whose address is
404.
● The 10-bit binary equivalent of 404 is 01100 10100.
This makes X=01100 (binary 12) and Y=10100
(binary 20). The n-bit word that is selected lies in the
X decoder output number 12 and the Y decoder
output number 20. All the bits of the word are
selected for reading or writing.

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 3. Address Multiplexing
Advantages of DRAM
● The DRAM cell contains a single MOS transistor and a capacitor. The charge
stored on the capacitor discharges with time, and the memory cells must be
periodically recharged by refreshing the memory.
● Because of their simple cell structure, DRAMs typically have four times the
density of SRAMs. This allows four times as much memory capacity to be
placed on a given size of chip.
● The cost per bit of DRAM storage is three to four times less than that of
SRAM storage.
● A operational cost of DRAM is less because of the lower power requirement
of DRAM cells.

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 3. Address Multiplexing
● DRAM chips are available in capacities from 64K to 512M bits.
● Most DRAMs have a 1- bit word size, so several chips have to be combined
to produce a larger word size.
● Because of their large capacity, the address decoding of DRAMs is arranged
in a two-dimensional array, and larger memories often have multiple arrays.
● To reduce the number of pins in the IC package, designers utilize address
multiplexing whereby one set of address input pins accommodates the
address components.
● In a two-dimensional array, the address is applied in two parts at different
times, with the row address first and the column address second.
● Since the same set of pins is used for both parts of the address, the size of
the package is decreased significantly.
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3. Address Multiplexing for a 64K DRAM
● 64K= 64 X 1024 = 65536 words are to be stored
● Requires
○ 16 bit address lines (216=65536) and
○ a 16X 65536 decoder or
○ two 8X(28) i.e 8X256 decoders
● The memory consists of a two-dimensional array of cells
arranged into 256 rows by 256 columns, for a total of
28×28=216=65536= 65536/1024 = 64K words.
● There is a single data input line, a single data output line, and a
read/write control, as well as an eight-bit address input and two
address strobes for enabling the row and column address into
their respective registers. The row address strobe (RAS)
enables the eight-bit row register, and the column address
strobe (CAS) enables the eight-bit column register.
● The bar on top of the name of the strobe symbol indicates that
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the registers are enabled on the zero level of the signal.
3. Address Multiplexing for a 64K DRAM
● The 16-bit address is applied to the DRAM in two
steps using RAS and CAS.
● Initially, both strobes are in the 1 state.
● The 8-bit row address is applied to the address
inputs and RAS is changed to 0. This loads the row
address into the row address register.
● RAS also enables the row decoder so that it can
decode the row address and select one row of the
array.
3. Address Multiplexing for a 64K DRAM
● After a time equivalent to the settling time of the row
selection, RAS goes back to the 1 level.
● The 8-bit column address is then applied to the address
inputs, and CAS is driven to the 0 state.
● This transfers the column address into the column
register and enables the column decoder. Now the two
parts of the address are in their respective registers, the
decoders have decoded them to select the one cell
corresponding to the row and column address, and a
read or write operation can be performed on that cell.
CAS must go back to the 1 level before initiating
another memory operation.
 IV. ERROR DETECTION AND CORRECTION

● The reliability of a memory unit may be improved by employing

error-detecting and error-correcting codes.
● The most common error detection scheme is the parity bit.
● A parity bit is generated and stored along with the data word in
memory.
● The parity of the word is checked after reading it from memory. The
data word is accepted if the parity of the bits read out is correct.
● If the parity check results in an inversion, an error is detected, but it
cannot be corrected.
 IV. ERROR DETECTION AND CORRECTION
● An error-correcting code generates multiple parity check bits that are stored with the
data word in memory.
● Each check bit is a parity over a group of bits in the data word.
● When the word is read back from memory, the associated parity bits are also read
from memory and compared with a new set of check bits generated from the data
that have been read.
○ If the check bits are correct, no error has occurred.
○ If the check bits do not match the stored parity, they generate a unique pattern,
called a syndrome, that can be used to identify the bit that is in error.
■ A single error occurs when a bit changes in value from 1 to 0 or from 0 to 1
during the write or read operation. If error is identified in the specific bit, then
the error can be corrected by complementing the erroneous bit.
 Hamming Code
● One of the most common error-correcting codes used in RAMs was devised
by R. W. Hamming.
● In the Hamming code, k parity bits are added to an n-bit data word, forming a
new word of n+k bits.
● The bit positions are numbered in sequence from 1 to n+k.
● Those positions numbered as a power of 2 {1(20), 2 (21), 4(22), 8(23), 16(25)......}
are reserved for the parity bits.
● The remaining bits are the data bits.
● The code can be used with words of any length.
 Step 1: Determination of k (no of parity bits or check bits)
● The syndrome value C consists of k bits and has a range of 2k values between 0 and 2k−1.
● One of these values, usually zero, is used to indicate that no error was detected, leaving 2k−1
values to indicate which of the n+k bits was in error.
● Each of these 2k−1 values can be used to uniquely describe a bit in error.
● Therefore, the range of k must be equal to or greater than n+k, giving the relationship
2k−1≥n+k ===> 2k−1−k≥n
● This relationship gives a formula for establishing the number of data bits that can be used in
conjunction with k check bits.
Number of Check Bits, k Range of Data Bits, n
● when k=1, n≤(21−1−1)=0.
3 2-4
● when k=2, n≤(22−1−2)=1.
4 5-11
● when k=3, n≤(23−1−3)=4.
5 12-26
● when k=4, n≤(24−1−4)=11.
6 27-57
7 58-120
 Step 2: Determination of Parity Bits Decimal Binary bit Position
P1, P2, P4, P8, P16, P32, ... 0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
P1 3 0 0 1 1
4 0 1 0 0
● P1 is the parity bit for all data bits in positions whose binary
5 0 1 0 1
representation includes a 1 in the least significant position 6 0 1 1 0
excluding 1 (3, 5, 7, 9, 11 and so on) 7 0 1 1 1
8 1 0 0 0
P1= XOR of bits (3, 5, 7, 9, 11…) 9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
 Determination of Parity Bits
P2 Decimal Binary bit Position
0 0 0 0 0
● P2 is the parity bit for all data bits in positions whose 1 0 0 0 1
binary representation includes a 1 in the position 2 2 0 0 1 0
3 0 0 1 1
from right except 2 (3, 6, 7, 10, 11 and so on)
4 0 1 0 0
P2= XOR of bits (3, 6, 7, 10, 11….) 5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
 Determination of Parity Bits
P4 Decimal Binary bit Position
0 0 0 0 0
● P4 is the parity bit for all data bits in positions whose 1 0 0 0 1
binary representation includes a 1 in the position 3 2 0 0 1 0
3 0 0 1 1
from right except 4 (5-7, 12-15, 20-23 and so on)
4 0 1 0 0
P4= XOR of bits (5,6,7,12,13,14,15,20,….) 5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
 Determination of Parity Bits
P8 Decimal Binary bit Position
0 0 0 0 0
● P8 is the parity bit for all data bits in positions whose 1 0 0 0 1
binary representation includes a 1 in the position 4 2 0 0 1 0
3 0 0 1 1
from right except 8 (9, 10, 11, 12, 14, 15 and so on)
4 0 1 0 0
P8= XOR of bits (9, 10, 11, 12,13,14,15,….) 5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
 Step 3 : Evaluation of Check Bits
When the n+k bits are read from memory, they are checked again for errors. The parity is
checked over the same combination of bits, including the parity bit. The 4 check bits are
evaluated as follows:
C1 = XOR of bits (1, 3, 5, 7, 9, 11)
C2 = XOR of bits (2, 3, 6, 7, 10, 11)
C4 = XOR of bits (4, 5, 6, 7, 12)
C8 = XOR of bits (8, 9, 10, 11, 12)
A 0 check bit designates even parity over the checked bits and a 1 designates odd parity.
Since the bits were stored with even parity, the result, C=C8C4C2C1=0000, indicates that no
error has occurred. However, if C≠0, then the binary number formed by the check bits gives the
position of the erroneous bit.
 EX: Consider the 8-bit data word 11000100.
1. Calculate no of parity bits(k) required; for n = 5 to 11, k= 4;
2. Identify positions of k parity bits. Here k=4 hence positions are P1, P2, P4, and P8.
(The 8 bits of the data word are in the remaining positions)
3. Form the new word of n+k length. (8+4=12)
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0
4. Determine the parity bits.
P1 = XOR of bits (3, 5, 7, 9, 11) =1⊕1⊕0⊕0⊕0=0; P2 = XOR of bits (3, 6, 7, 10, 11)=1⊕0⊕0⊕1⊕0=0;
P4 = XOR of bits (5, 6, 7, 12)=1⊕0⊕0⊕0=1; P8 = XOR of bits (9, 10, 11, 12)=0⊕1⊕0⊕0=1
5. Substitute the 4 Parity bits in their proper positions,
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0 Remember that the exclusive-OR operation
performs the odd function: It is equal to 1
0 0 1 1 1 0 0 1 0 1 0 0 for an odd number of 1’s in the variables
and to 0 for an even number of 1’s.
6. Evaluate Check bits
C1 = XOR of bits (1, 3, 5, 7, 9, 11)
C2 = XOR of bits (2, 3, 6, 7, 10, 11)
C4 = XOR of bits (4, 5, 6, 7, 12)
C8 = XOR of bits (8, 9, 10, 11, 12)
 Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
Consider three cases (i) No error 0 0 1 1 1 0 0 1 0 1 0 0
(ii) Error in bit 1 1 0 1 1 1 0 0 1 0 1 0 0
(iii) Error in bit 5 0 0 1 1 0 0 0 1 0 1 0 0
In the first case, there is no error in the 12-bit word. In the second case, there is an error in bit position
number 1 because it changed from 0 to 1. The third case shows an error in bit position 5, with a change
from 1 to 0.

case C8=XOR of bits C4= XOR of C2 = XOR of bits C1= XOR of bits C=C8C4C2 Error
(8,9,10,11,12) bits (4,5,6,7,12) (2, 3, 6, 7,10, 11) (1, 3, 5, 7, 9, 11) C1 in bit
(i) No Error XOR(1,0,1,0,0) XOR(1,1,0,0,0) XOR(0,1,0,0,1,0) XOR(0,1,1,0,0,0 0000 No
=0 =0 =0 ) error
=0
Error in bit XOR(1,0,1,0,0) XOR(1,1,0,0,0) XOR(0,1,0,0,1,0) XOR(1,1,1,0,0,0 0001 1
1 =0 =0 =0 )
=1
Error in bit XOR(1,0,1,0,0) XOR(1,0,0,0,0) XOR(0,1,0,0,1,0) XOR(0,1,0,0,0,0 0101 5
 Single-Error Correction, Double Error Detection
● The Hamming code can detect and correct only a single error.
● By adding another parity bit to the coded word, the Hamming code can be used to correct a
single error and detect double errors.
● If we include this additional parity bit, then the previous 12-bit coded word becomes
001110010100P13, where P13 is evaluated from the exclusive-OR of the other 12 bits. This
produces the 13-bit word 0011100101001 (even parity). When the 13-bit word is read from
memory, the check bits are evaluated, as is the parity P over the entire 13 bits. If P=0, the parity is
correct (even parity), but if P=1, then the parity over the 13 bits is incorrect (odd parity).
● The following four cases can arise:
○ If C=0 and P=0, no error occurred.
○ If C≠0 and P=1, a single error occurred that can be corrected.
○ If C≠0 and P=0, a double error occurred that is detected, but that cannot be corrected.
○ If C=0 and P=1, an error occurred in the P13 bit. This scheme may detect more than two
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errors, but is not guaranteed to detect all such errors.
● Integrated circuits use a modified Hamming code to generate and check parity
bits for single-error correction and double-error detection. The modified Hamming
code uses a more efficient parity configuration that balances the number of bits
used to calculate the XOR operation.
● A typical integrated circuit that uses an 8-bit data word and a 5-bit check word is
IC type 74637. Other integrated circuits are available for data words of 16 and 32
bits.
● These circuits can be used in conjunction with a memory unit to correct a single
error or detect double errors during write and read operations.

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