Module V BEHAVIORAL MODELING

● Procedural blocks
1. Initial
2. always
● Statements
1. If else
2. Case
3. Forever
4. For
● HDL for combinational circuits by behaviour level modelling
● HDL for
1. flip flops
2. counters
3. shift registers
4. universal shift registers
5. sequence detector
1
Procedural blocks

2
● Verilog is a concurrent programming language, which means that different
blocks of the Verilog program run in parallel.
● The main reason for the concurrent nature is the fact that in hardware each
block of the module will operate individually in parallel once it is powered on.
● Also, the hardware once turned on, it will go on operating until it is powered
off.
● Thus, to model the hardware in Verilog, the Verilog program also runs
indefinitely until the simulation is terminated.
● To achieve all these behaviours, Verilog provides with procedural blocks.
● Verilog provides two structured procedural blocks or two kinds of abstract
behaviors

1. initial block - single pass behaviour

2. always block - cyclic behaviour
3
 Initial always
single pass behaviour -This declares a cyclic behavior
procedural block is executed only -The always block starts its execution
once when the Verilog simulation at the beginning of the simulation and
begins, i.e., at time step 0.
continues to execute in a loop.
expires after the associated executes and re-executes indefinitely,
statement executes. until the simulation is stopped.
designers use single-pass behavior designers use cyclic behavior primarily
primarily to prescribe stimulus to design sequential circuit
signals in a testbench

4
• Initial and always statements describe independent processes, meaning that the
statements in one process execute autonomously.
• Both types of processes consist of procedural statements
• And both start immediately as the simulator is started.
• The difference between the two is that initial processes execute once, whereas
always process execute repeatedly forever.

5
1. Initial Block
• This procedural block is executed only once when the Verilog simulation begins,
i.e., at time step 0.
• As said earlier, hardware will go on operating unless the power is switched off,
thus this procedural block cannot be realised into actual hardware, i.e., it is not
synthesizable. This block is mainly used in test bench.
• initial keyword is used to declare an initial procedural block. If the block consists of
more than one statement, the statements are enclosed within begin end
statement.
• If more than one initial block is declared in a module, all the blocks will run
concurrently, i.e., will run parallelly and all will start at the same time at 0-time
step.
• The statements within the block are executed sequentially.
• Multiple initial blocks are valid in a module and each block executes at zero
simulation time. An individual block may finish their execution independently.
• Nested initial blocks are not valid. 6
Syntax:
(i) initial •If there are multiple statements within an
<single statement> initial block, they must be grouped using
begin and end keywords.
(ii)initial begin •Initial blocks are typically used for
<statement 1> initialization, monitoring, providing test inputs
<statement 2> and other operations, which must be
<statement 3> executed only once during the entire
... simulation.
... •Timing control is used to provide delay
end •‘#’ followed by time value provides a delay.
•Initial block is not synthesizable, hence used
for Testbench or simulation, not for Designs.

7
module initial_block; three initial blocks all of which are
reg [3:0] a; started at the same time and run in parallel.
initial begin:block_1 However, depending on the statements and
the delays within each initial block, the time
a = 4'd5;
taken to finish the block may vary.
#9;
a = 4'd2;
end
initial begin:block_2
#5;
a = 4'd9;
end
initial begin:block_3 Output
$monitor("At [%0t], a = %0d", $time, a); # At [0], a = 5
end # At [5], a = 9
8
endmodule # At [9], a = 2
2. Always Block
• Verilog behavioral descriptions of hardware are declared with the keyword
always, followed by an optional event control expression (sensitivity list)
and a begin . . . end block of procedural assignment statements.
• The always block starts its execution at the beginning of the simulation and
continues to execute in a loop.
• Similar to the initial block, the always block is executed sequentially.
• Based on changes in single or multiple signals in the sensitivity list, always
block is executed.
• If no sensitivity list is specified, always block executes repeatedly
throughout the simulation.
• Multiple always blocks are valid in a module and each block executes
independently.
• Nested always blocks are not valid.
9
 @, is called the event control operator
Syntax:
always
<single statement>

always @(<sensitivity_list or event control expression >)

<single statement>

always @(<sensitivity_list or event control expression >)

begin
<statement 1>
<statement 2>
...
...
end 10
● Statements
1. If else
2. Case
3. Forever
4. For
5. Repeat

11
1. If else statement
Verilog supports ‘if’, ‘else if’, ‘else’ same as other programming languages.
The ‘If’ statement is a conditional statement based on which decision is made
whether to execute lines inside if block or not.

The begin and end are required in case of multiple lines present in ‘if’ block. For
single-line inside if statement may not require ‘begin..end’

The ‘if’ statement returns true if the expression calculates its value as 1 otherwise,
for 0, x, z values ‘if’ block will not be executed.

12
Syntax: if condition
Syntax: if and else condition
if(<condition>) begin
if(<condition>) begin
...
...
end
end
Syntax: ‘else if’ and ‘else’ condition
else begin
if(<condition>) begin
...
...
end
end
else if(<condition>) begin
...
end
else if(<condition>) begin
...
end
else begin
...
end 13
 ● The procedural assignment
Ex: Mux statements inside the
always block are executed
module mux_2x1_beh (m_out, A, B, select); every time there is a
input A, B, select; change in any of the
output m_out; variables listed in the
reg m_out; // or output reg m_out; sensitivity list after the @
// must be of the reg data type, because it is assigned value symbol.
// by a Verilog procedural assignment ● (Note that there is no
always @ (A or B or select) semicolon (;) at the end of
// Alternative: always @ (A, B, select) the always statement.)
● Note that the keyword or,
if (select == 1) instead of the logical OR
m_out = A; operator “ | ” , is used
else between variables.
m_out = B; ● The conditional statement
endmodule if-else provides a decision
based upon the value of the
select input. 14
module comparator (input [3:0] A, B, output reg g,l,e);
always@(A,B)
begin
g = 0; l = 0; e= 0;
if(A>B)
g = 1'b1;
else if(A<B)
l = 1'b1;
else
e = 1'b1;
end
endmodule

15
module comparator_tst;
reg [3:0] A,B;
wire e,l,g;
comparator DUT (A,B,g,l,e);
initial
begin
A= 4'b1100;
B = 4'b1100;
#10;
A = 4'b0100;
B = 4'b1100;
#10;
A = 4'b1111;
B = 4'b1100;
#10;
$finish;
end
endmodule 16
2. case statement
The case statement has a given expression and it is checked with the
expression (case item) mentioned in the list in the written order and if it
matches then the statement or group of statements are executed. If it does
not match with any of the written expressions of the list then, the default
statement will be executed.

If the ‘default’ statement is not given and the given expression is not
matched with any expression in the list, then the case statement evaluation
will exit.

Verilog case statement uses case, endcase, and default keywords.

17
Syntax:

case(<expression>) 1. The default statement is not

<case_item1>:statement 1 mandatory. There must be
only one default statement for
<case_item2>:statement 2
the single case statement.
<case_item3>:statement 3 2. The nested case statement is
<case_item4>: begin allowed.
... 3. Verilog case statements work
... similarly as switch statements
end in C language.
default:
endcase

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// Behavioral description of four-to-one line multiplexer //
module mux_4x1_beh (
output reg m_out,
input in_0, in_1, in_2, in_3,
input [1: 0] select );
always @ (in_0, in_1, in_2, in_3, select)
case (select)
2'b00: m_out <= in_0;
2'b01: m_out <= in_1;
2'b10: m_out <= in_2;
2'b11: m_out <= in_3;
endcase
endmodule 19
The case statement also has a total of three variations: case, casex
and casez. Note the following differences.
1. casex: considers all x and z values as don’t care.
2. casez: considers all z values as don’t cares. The z can also be
specified as ?

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 3. forever
As the name suggests, a
forever loop runs
indefinitely. To terminate
the loop, a break
statement can be used.
initial
Syntax: begin
clk = 1’b0;
forever begin
forever #10 clk = ~clk;
... end
end end
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 4. for
The for loop iterates till the mentioned condition is
satisfied. The execution of for loop depends on –

1. Initialization
2. Condition
3. Update

Syntax:

for (<initialization>; <condition>; <update>)

begin
…
end

22
4. for
module my_design;
integer i;
initial
begin // Note that ++, --operator does not exist in Verilog !
for (i = 0; i < 10; i = i + 1)
begin
$display ("Current loop#%0d ", i);
end
end
endmodule

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 initial
5. repeat begin
clk = 1'b0;
repeat (30)
#10 clk = ~clk;
A repeat loop is used to execute statements a given end
number of times.

Syntax:
repeat(<number>)
initial
begin // <number> can be variable or fixed value
begin
... clk = 1'b0;
end a=30;
repeat (a)
#10 clk = ~clk;
end
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HDL for combinational circuits by behaviour level modelling

1. half adder
2. full adder
3. Four bit comparator
4. Decoder
5. Encoder
6. Multiplexer
7. Demultiplexer

25
 1. half adder

module half_adder_behavioral (a, b, s,c);

input a,b;
output reg s,c;
always @(a,b)
begin
s = a ^ b;
c = a & b;
end
endmodule

26
2. full adder

module fulladder_behavioral (a, b, cin,s,c);

input a,b,cin;
output reg s,c;
always @(a,b,cin)
begin
s = a ^ b^cin;
c = (a & b)|(b&cin)|(cin&a);
end
endmodule

27
 3. Four bit comparator

module comparator(
input [3:0] A, B,
output reg g,l,e);

always@(A,B)
begin
g = 0; l = 0; e= 0;
if(A>B)
g = 1'b1;
else if(A<B)
l = 1'b1;
else
e = 1'b1;
end
endmodule 28
 4. 3 to 8 Decoder
module binary_decoder(input [2:0] D,output reg [7:0] y);
always@(D) begin
y = 0;
case(D)
3'b000: y[0] = 1'b1;
3'b001: y[1] = 1'b1;
3'b010: y[2] = 1'b1;
3'b011: y[3] = 1'b1;
3'b100: y[4] = 1'b1;
3'b101: y[5] = 1'b1;
3'b110: y[6] = 1'b1;
3'b111: y[7] = 1'b1;
default: y = 0;
endcase
end
29
endmodule
5. Encoder
module encoder_8to3(i,y);
input [7:0]i;
output reg [2:0]y;
always @(i)
begin
if(i[7]==1) y=3'b111;
else if(i[6]==1) y=3'b110;
else if(i[5]==1) y=3'b101;
else if(i[4]==1) y=3'b100;
else if(i[3]==1) y=3'b011;
else if(i[2]==1) y=3'b010;
else if(i[1]==1) y=3'b001;
else
y=3'b000;
end
else y=3'bzzz;
end
endmodule 30
6. Multiplexer
module mux_4x1_beh (
output reg m_out,
input in_0, in_1, in_2, in_3,
input [1: 0] select );
always @ (in_0, in_1, in_2, in_3, select)
case (select)
2'b00: m_out <= in_0;
2'b01: m_out <= in_1;
2'b10: m_out <= in_2;
2'b11: m_out <= in_3;
endcase
endmodule 31
7. Demultiplexer
module demux_1x8_bh(output reg y0, y1, y2, y3, y4, y5,
y6, y7,input i,input [2:0] s);
always @(i,s) begin
y0 = (s == 3'b000) ? i : 1'b0;
y1 = (s == 3'b001) ? i : 1'b0;
y2 = (s == 3'b010) ? i : 1'b0;
y3 = (s == 3'b011) ? i : 1'b0;
y4 = (s == 3'b100) ? i : 1'b0;
y5 = (s == 3'b101) ? i : 1'b0;
y6 = (s == 3'b110) ? i : 1'b0;
y7 = (s == 3'b111) ? i : 1'b0;
end
endmodule 32
● HDL for
1. flip flops(D,JK,T)
2. shift registers
3. universal shift registers
4. counters
5. sequence detector

33
1. a. D Flip Flop

module dff(input d, clk, rstn, output reg q);

always @(posedge clk or negedge rstn)
begin
if (rstn==0)
q <= 0;
else
q <= d;
end
endmodule

34
module dfftb;
reg d, rstn, clk;
wire q;
dff uut (d,clk,rstn,q);
initial begin
clk=0; //always #5 clk = ~clk;
forever #10 clk = ~clk;
end
initial begin
d = 0;
rstn = 0;
clk = 0;
// Reset de-assertion after some time
#50 rstn = 1;
// Apply input d changes
#10 d = 1;
#20 d = 0;
#30 d = 1;
#100 $finish;
end
endmodule
35
 1. b. JK Flip Flop module tb_jk;
reg j, k,clk,rstn;
module jkff (input j, k, clk, rstn, output reg q); wire q;
always @ (negedge clk or negedge rstn) initial begin
if (rstn==0) clk=0;
q <= 0; forever #10 clk = ~clk;
else begin end
case ({j,k}) jkff uut ( j, k, clk,rstn,q);
2'b00 : q <= q; initial begin
2'b01 : q <= 0; rstn =0;
2'b10 : q <= 1;
#20 rstn=1;
2'b11 : q <= ~q;
endcase #20 j <= 0; k <= 0;
end #20 j <= 0; k <= 1;
endmodule #20 j <= 1; k <= 0;
#20 j <= 1; k <= 1;
#20 $finish;
end
36
endmodule
 module tb_tff;
reg j, k,clk,rstn;
1. c. t Flip Flop wire q;
initial begin
module tff (input t, clk, rstn, output reg q); clk=0;
always @ (negedge clk or negedge rstn) forever #10 clk = ~clk;
if (rstn==0) end
q <= 0; tff uut ( t, clk,rstn,q);
else begin initial begin
case (t) rstn =0;
1’b0 : q <= q;
#20 rstn=1;
1'b1 : q <= ~q;
endcase #20 t <= 0;
end #20 t <= 1;
endmodule #20 t<= 0;
#20 $finish;
end
endmodule
37
 2. Counters
a. Asynchronous up Counter

module jkff (input j, k, clk, rstn, output q,qbar);

reg q,qbar;
always @ (negedge clk or negedge rstn)
if (rstn==0)
q <= 0;
else begin
module asynupcounter(input [3:0] j,k,clk, rstn, output [3:0]q,qbar
case ({j,k})
jkff jk0 ( j[0], k[0], clk, rstn, q[0],qbar[0]);
2'b00 : q <= q; jkff jk1 ( j[1], k[1], q[0], rstn, q[1],qbar[1]);
2'b01 : q <= 0; jkff jk2 ( j[2], k[2], q[1], rstn, q[2],qbar[2]);
2'b10 : q <= 1; jkff jk3 ( j[3], k[3], q[2], rstn, q[3],qbar[3]);
2'b11 : q <= ~q; endmodule
endcase
assign qbar = ~q;
end
endmodule 38
module tb_asyncounter;
reg [3:0]j, k;
reg clk, rstn;
wire [3:0]q,qbar;
initial begin
clk=0;
forever #10 clk = ~clk;
end
asynupcounter uut ( j, k, clk, rstn, q,qbar);
initial begin
j <= 4'b1111;
k <= 4'b1111;
rstn <= 0;
#25 rstn <= 1;
#500 $finish;
end
endmodule
39
 2. Counters
b. Asynchronous down Counter

module jkff (input j, k, clk, rstn, output q,qbar);

reg q,qbar;
always @ (negedge clk or negedge rstn)
if (!rstn)
q <= 0;
else begin module asyndowncounter(input [3:0] j,k,clk, rstn, output [3:0]q,qbar);
case ({j,k}) jkff jk0 ( j[0], k[0], clk, rstn, q[0],qbar[0]);
2'b00 : q <= q; jkff jk1 ( j[1], k[1], qbar[0], rstn, q[1],qbar[1]);
2'b01 : q <= 0; jkff jk2 ( j[2], k[2], qbar[1], rstn, q[2],qbar[2]);
2'b10 : q <= 1; jkff jk3 ( j[3], k[3], qbar[2], rstn, q[3],qbar[3]);
2'b11 : q <= ~q; endmodule
endcase
assign qbar = ~q;
end
endmodule 40
module tb_asyncounter;
reg clk, rstn;
wire [3:0]q,qbar;
initial begin
clk=0;
forever #10 clk = ~clk;
end
asyndowncounter uut ( j, k, clk, rstn, q,qbar);
initial begin
j <= 4'b1111; k <= 4'b1111;
rstn <= 0;
#25 rstn <= 1;
#500 $finish;
end
endmodule

41
2.c. Synchronous Counter

42
 2. Counters
c. Synchronous up Counter

module jkff (input j, k, clk, rstn, output q,qbar);

reg q,qbar;
always @ (negedge clk or negedge rstn)
if (rstn==0)
q <= 0;
else begin module syncounter(input [2:0] j,k,clk, rstn, output [2:0]q,qbar);
case ({j,k}) jkff jk0 ( 1, 1, clk, rstn, q[0],qbar[0]);
2'b00 : q <= q; jkff jk1 ( q[0],q[0], clk, rstn, q[1],qbar[1]);
2'b01 : q <= 0; jkff jk2 ( (q[1]&q[0]), (q[1]&q[0]), clk, rstn, q[2],qbar[2]);
2'b10 : q <= 1; endmodule
2'b11 : q <= ~q;
endcase
assign qbar = ~q;
end
endmodule 43
module tbsyncounter;
reg [2:0]j, k;
reg clk, rstn;
wire [2:0]q,qbar;
initial begin
clk=0;
forever #10 clk = ~clk;
end
syncounter uut ( j, k, clk, rstn, q,qbar);
initial begin
rstn <= 0;
#25 rstn <= 1;
#500 $finish;
end
endmodule

44
3. Shift Register
module dff(input d, clk, rstn, output reg q);
always @(posedge clk or negedge rstn) module shiftregister(input clk, rstn, din,
begin output [3:0]q);
if (!rstn) dff d0 ( din, clk, rstn, q[0]);
q <= 0; dff d1 ( q[0], clk, rstn, q[1]);
else dff d2 ( q[1], clk, rstn, q[2]);
q <= d; dff d3 ( q[2], clk, rstn, q[3]);
end endmodule
endmodule

45
module tbshiftregister;
reg clk, rstn,din;
wire [3:0]q;
initial begin
clk=0;
forever #10 clk = ~clk;
end
shiftregister uut (clk, rstn, din,q);
initial begin
rstn <= 0;
din<=1;
#25 rstn <= 1;
#500 $finish;
end
endmodule

46
module univshiftreg (output reg [3: 0] q, input [3: 0] d, input s1, s0, MSB_in, LSB_in, clk,rstn);
always @ (posedge clk, negedge rstn)
if (rstn== 0) q <= 4'b000;
else
case ({s1, s0})
2'b00: q <= q; // No change
2'b01: q <= {MSB_in, q[3: 1]}; // Shift right
2'b10: q <= {q[2: 0], LSB_in}; // Shift left
2'b11: q <= d; // Parallel load of input
endcase
endmodule

47
module usrtb;
wire [3:0]q;
reg [3:0]d;
reg s1,s0,MSB_in, LSB_in,clk, rstn;
initial begin
clk=0;
forever #10 clk = ~clk;
end
univshiftreg uut (q,d,s1,s0,MSB_in, LSB_in,clk, rstn);
initial begin
rstn <= 0;
#25 rstn <= 1; d<=4'b1001; s1=1 ; s0= 1 ; MSB_in=1; LSB_in=1;
#25 s1=0 ; s0= 1 ;
#25 s1=1 ; s0= 0 ;
#25 s1=0 ; s0= 0 ;
#500 $finish;
end
endmodule

48
Seq Verilog parameter is
used to pass a constant
to the module when it is
module seqdetector(output y,input x, clk, rstn); instantiated. It is not
considered under net or
reg [1: 0] state; reg data types.
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @ ( posedge clk, negedge rstn)
if (rstn == 0) state <= S0; // Initialize to state S0
else case (state)
S0: if (x) state <= S1; else state <= S0;
S1: if (x) state <= S2; else state <= S0;
S2: if (x) state <= S3; else state <= S0;
S3: if (x) state <= S3; else state <= S0;
endcase
assign y = (state == S3); // Output of flip-flops
endmodule
49
module tb;
reg x, clk,rstn;
wire y;
seqdetector uut (y, x, clk, rstn);
initial begin
clk = 0;
forever #10 clk=~clk;
end
initial begin
rstn =0;
#25 rstn =1;
x=1;
#20 x=0;
#20 x=1;
#20 x=0;
#20 x=1;
#20 x=1;
#20 x=0;
#20 x=1;
#20 x=1;
#20 x=1;
#20 x=0;
#20 $finish;
end 50
endmodule