Exercise 1

Figure-1 shows a feedback triple utilizing MOSFETs. All three MOSFETs are biased
and sized to operate at gm = 4 mA/V. (Neglect ro)

a) Determine the type of Feedback Topology

b) Find the feedback network and calculate β

c) Draw amplifier without feedback but taking the feedback network loading into
account (input and out circuits)

Figure 1: Feedback triple utilizing three MOSFETs for Q 1

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Solution 1
a) Voltage-Series (Series-Shunt) or Voltage Amplifier or voltage sampling-voltage mixing
b) The feedback network is as shown in Figure 2 below:

Figure 2: Feedback network for # Q 1

The feedback gain β is calculated as, for RF = 1 kΩ:

c)

Fig.3: The amplifier without feedback but taking the feedback network loading into account for Q 1

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Exercise 2

Consider the circuit shown in Fig. 4. It is required to analyze this amplifier to obtain
its voltage gain ⁄ , input resistance , and output resistance Find numerical
values for the case = 4 mA/V, = 10 kΩ, = 1 kΩ and = 9
kΩ. For simplicity, neglect of each of a .

Fig.4: The amplifier with feedback for Q 2

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Solution 2
We identify the feedback network as the voltage divider ( , ). Its loading effect at
the input is obtained by short circuiting its port 2 (because it is connected in shunt
with the output). Then, looking into its port 1, we see . The loading effect at
the output is obtained by open-circuiting port 1 of the feedback network (because it is
connected in series with the input). Then, looking into port 2, we see in series with
. The A circuit will therefore be as shown in Fig. 5.

Fig.5: The A circuit without feedback but taking the feedback network loading into account for Q 2

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The gain A is determined as the product of the gain of and the gain of as
follows:

For the numerical values given,

The value of β is determined from the β circuit in Fig. 6

Figure 6: Feedback network for # Q 2

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The closed-loop gain ⁄ can now be found as

The input resistance is obviously infinite because of the infinite input resistance of the
MOSFET. The output resistance is obtained as follows,

Where is the output resistance of the A circuit. From Fig. 5

The amount of feedback is

Which is relatively low given that the open-loop amplifier has = 5000Ω.

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Exercise 3

A designer is considering two possible designs of a feedback amplifier. The ultimate

goal is Af = 10 V/V. One design employs an amplifier for which A = 1000 V/V and
the other uses A = 500 V/V. Find β and the desensitivity factor in both cases. If the A
= 1000 amplifier units have a gain uncertainty of ±10%, what is the gain uncertainty
for the closed-loop amplifiers utilizing this amplifier type? If the same result is to be
achieved with the A = 500 amplifier, what is the maximum allowable uncertainty in
its gain?

Solution 3

Step 1: Find the Feedback Factor β

The closed-loop gain of a feedback amplifier is given by:

Solving for β

For A = 1000 V/V

β =

For A = 500 V/V

β =

Step 2: Find the Desensitivity Factor D

The desensitivity factor is:

D = 1+Aβ

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For A = 1000 V/V
D = 1 + (1000×0.099) = 1+99 = 100

For A = 500 V/V

D = 1 + (500×0.098) = 1+49 = 50

Step 3: Calculate Gain Uncertainty for A = 1000

If A has an uncertainty of ±10%, then A varies between:

Amin = 1000×0.9 = 900

Amax = 1000×1.1 = 1100 A

The corresponding closed-loop gains are:

Thus, the gain uncertainty in the closed-loop amplifier is negligible.

Step 4: Find Maximum Allowable Uncertainty for A = 500

To achieve the same result, the closed-loop gain must remain stable with a
desensitivity factor of 50. The allowed percentage uncertainty in A is:

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Exercise 4
Consider an NMOS differential amplifier, where a common mode voltage VCM is
applied shown in figure 7.
Let VDD = VSS = 1 V, = 0.4 mA/V2, W/L = 12.5, Vt = 0.5 V, I = 0.2 mA and
RD = 10 kΩ (neglect channel length modulation). Let vG1 = vid and vG2 = 0, find the
value of vid and vD1 where:

a) iD1 = iD2 = 0.1 mA

b) iD1 = 0.15 mA and iD2 = 0.05 mA
c) iD1 = 0.2 mA and iD2 = 0

Figure 7: The MOS differential pair with a differential input signal vid applied.

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Solution 4
a) Since iD1 = iD2 = I/2 = 0.1 mA, the circuit is being supplied by common mode
input,
i.e. vG1 = vG2; and hence vG2 = 0 ⇒ vG1 = 0. Therefore,
vid = 0
vD1 = VDD − iD1RD = 1 − (0.1 × 10−3 ) × (10 × 103 ) = 0 V
b)

c)

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Exercise 5
The differential amplifier in Figure 8 below utilizes a resistor RSS to establish a 1-mA DC bias
current. Note that this amplifier uses a single 5-V supply, and thus the DC common-mode voltage
VCM cannot be zero. Transistors Q1 and Q2 have k’n (W/L) = 2.5 mA/V2, Vt =0.7 V, and λ = 0.
a) Find the required value of VCM.
b) Find the value of RD that results in a differential gain Ad of 8 V/V.
c) Determine the DC voltage at the drains.
d) Determine the single-ended-output common-mode gain VD1/VCM. (Hint: You need to take
1/gm into account.)
e) Use the common-mode gain found in (d) to determine the change in VCM that results in Q1
and Q2 entering the triode region.

Figure 8

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Solution 5

Given Data:

 Supply Voltage: VDD =5 V

 Bias Current: ISS = 1mA (divided equally between Q1 and Q2 )

 MOSFET Parameters:

 k′n(W/L) = 2.5 mA/V²

 Vt = 0.7V

 λ=0 (neglecting channel-length modulation)

a) Finding the Required VCM:

The common-mode voltage VCM is the DC voltage at the sources of Q1 and Q2,
which are connected through RSS to ground.
Since ID1 = ID2 = ISS/2 = 0.5mA, we use the MOSFET quadratic equation in
saturation:
ID = k′nW/L(VGS−Vt)2
Substituting the known values:
0.5mA = 2.5mA/V2⋅(VGS−0.7V)2
Solving for VGS

VGS = 1.147V
Since VCM = VGS, we get:
VCM = 1.147V
b) Finding RD for Differential Gain Ad = 8V/V:
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 The differential gain for a MOSFET differential amplifier is given by:
Ad = gmRD
Where gm is the transconductance:

2.24mS
Solving for RD:

c) Finding the DC Voltage at the Drains:

V V
V V
d) Finding the Common-Mode Gain

The common-mode gain is:

e) Finding the Change in VCM for Triode Region Entry:

For Q1 and Q2 to enter the triode region, the drain voltage must be less than the
source voltage by Vt:
VD < VS + Vt
Since VS = VCM,
3.215V < VCM + 0.7

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 VCM > 2.515V
The required increase in VCM:
ΔVCM = 2.515V−1.147V = 1.368V
From (d),
ΔVD1 = ACM⋅ΔVCM
ΔVD1 = 1.46×1.368V = 1.996 V 2V
Thus, the new drain voltage would be:

VD, new = 3.215V − 1.996V = 1.219V

Since this is still above VS + Vt, we need a slightly larger VCM, this gives an
approximate threshold.

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Exercise 6
An NMOS differential amplifier employing equal drain resistors, RD = 47 kΩ, has a differential gain
Ad of 20 V/V.
a) What is the value of gm for each of the two transistors?
b) If each of the two transistors is operating at an overdrive voltage VOV = 0.2 V, what must the
value of I be?
c) For vid = 0, what is the dc voltage across each RD?
d) If vid is 20-mV peak-to-peak sine wave applied in a balanced manner but superimposed on
VCM = 0.5 V, what is the peak of the sine-wave signal at each drain?
e) What is the lowest value that VDD must have to ensure saturation-mode operation for Q1 and
Q2 at all times? Assume Vt = 0.5 V.
Solution 2
Given Data:
 RD = 47kΩ
 Differential Gain: Ad=20 V/V
 Overdrive voltage: VOV = 0.2V
 Threshold voltage: Vt = 0.5V
 Common-mode voltage: VCM = 0.5V
 Input signal: vid = 20mV peak-to-peak
 Assume equal transistors operating in saturation.
a) Find gm for each transistor

The differential gain for an NMOS differential pair with equal drain resistors is given by:

Rearrange for gm:

b) Find the bias current I

The transconductance of a MOSFET operating in saturation is given by:

Since each transistor carries a current ID = I/2:

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Solving for I:

Substituting values:

I = (0.0004255)(0.2) = 85.1μA
c) Find the DC voltage across each RD

For vid = 0, the drain currents of both transistors are equal, so each transistor carries ID = I/2.

The voltage across RD:

( )
= (42.55µA) ( ) = 2.0 V
d) Find the peak of the sine-wave signal at each drain
The output differential voltage is given by:

Since vid is a 20 mV peak-to-peak sine wave:

= 400mV peak-to-peak

Each drain voltage fluctuates in opposite directions by half of this differential output:

vd1 = −vo/2 = −200mV

vd2 = +vo/2 = +200mV

Since the DC drain voltage is VD = VDD − VRD = VDD − 2V, the total voltage at each drain is:

Vd1 = VD − 200mV
Vd2 = VD + 200mV

If VDD = 5V, then:

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 VD = 5V − 2V = 3V
Vd1 = 3V − 0.2V = 2.8V
Vd2 = 3V + 0.2V = 3.2V
e) Find the minimum VDD to ensure saturation
For saturation, each NMOS must satisfy:

VDS ≥ VOV
VD − VS ≥ 0.2V

Since VS = 0V (assuming an ideal current source at the tail), the drain voltage must be at least:

VD ≥ 0.2V

Since VD = VDD – VRD, we require:

VDD – VRD ≥ 0.2V

VDD − 2V ≥ 0.2V
VDD ≥ 2.2V

Thus, the minimum required VDD is 2.2V.

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