Machine Structure II

ZAIRI HADJER

Chapter I: combinational circuits

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In this Chapter
I. Introduction
II. Definition.
III.Combinatorial circuits.
IV. Steps in designing a combinatorial circuit:
1. Establishing the truth table.
2. Simplifying logical functions.
3. Creating the logical diagram.

V. Study of some common combinatorial circuits:

1. Half-adder. 2. Full-adder.
3. Subtractor-adder (in two complement).
4. Decoders. 5. Multiplexers.
6. Priority encoders. 7. Demultiplexers.

- Other examples of combinatorial circuits.

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Chapter- 1 : introduction

Definition
• A logic circuit is defined as an electronic circuit
implementing one or more logical function(s). It is
defined by the interconnection of a set of logic gates
connecting outputs to inputs. Thus, overall, a logic circuit
can be schematized as a black box with inputs (binary)
and binary outputs (the logical functions). Of course, the
black box is composed of a set of interconnected logic
gates that can be schematized by a diagram called a logic
diagram.

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Chapter- 1 : introduction
Digital logic circuits
Digital circuits are classified as combinational or sequential.
• A combinational circuit’s outputs depend only on the current values of the inputs; in other
words, it combines the current input values to compute the output
• No Feedback between input and output.
• No memory
• A sequential circuit’s outputs depend on both current and previous values of the inputs; in
other words, it depends on the input sequence
• Feedback is present
• Memory is present
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Chapter- 1 : Combinational circuits
Example Which of the circuits in the following figure are combinational circuits
according to the rules of combinational composition?

Solution: Circuit (a) is combinational. (b) is not combinational, because there is a

cyclic path: the output of the XOR feeds back to one of its inputs. (c) is
combinational.
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Chapter- 1 : Combinational circuits
• Are specially designed using multiple interconnected logic gates such that the
output will be generated by computing the logical combinations of the
You should
present input only. know
Basic gates
• Combinational circuit consist of :
Input variables
for ' n ' input variables, there will be 2N possible combinations..
Logic gates
Generate signals from the inputs to the output Universal gates
Output variables
For each combination of input, find the output values. there is one
possible output value.
Boolean laws

De-Morgans
Theorem

Kmaps
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Chapter- 1 : Combinational circuits
Classification of Combinational circuits

Are basically divided into 3 classes:

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Chapter- 1 : Combinational circuits
Applications of Combinational Circuit
Combinational circuits are fundamental building blocks in digital electronics and are widely used in various
applications. Here are some key applications of combinational circuits:

Arithmetic & Logic Operations (ALU)

Microprocessors (Intel, AMD, ARM) –Calculators (Casio, Texas Instruments)
Data Encoding & Decoding
Barcode & QR Code Scanners –Digital TV & Set-Top Boxes – Networking (Routers & Modems) –
Memory Addressing
RAM & Cache in Computers –SSD Controllers – Graphics Cards (NVIDIA, AMD)
Display Systems
Seven-Segment Displays in Digital Clocks & Elevators –LED Billboards & Scoreboards – Automobile Dashboards

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Chapter- 1 : Combinational circuits
Example Design a combinational logic circuit with three input Truth table of circuit
variables that will produce a logic 1 output when more than one
input variable are logic 1. Input 1 Input 2(B) Input 3 (C) Output (X)
𝐵ത 𝐶ҧ ത
𝐵𝐶 𝐵𝐶 𝐵 𝐶ҧ (A)
0 0 0 0
𝐴ҧ 0 0 1 0
𝐴 0 1 1 1 0 0 1 0

0 1 0 0
𝑿 = 𝑨𝑪 + 𝑨𝑩 + 𝑩𝑪
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

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Chapter- 1 : Design of arithmetic combination circuits
Integrated Logic Circuit 7483
Design of adder circuits
- Full Adder
❑ The most basic arithmetic operation is the addition.
❑ Simple addition of two bits consists of 4 possible elementary
operations:
0+0=0
0+1=1
1+0=1
1+1=0 with a carry of 1
❑ A combinational circuit that performs the addition is called adder.
❑ Adder circuits are divided in two types;
✓ half adder circuit
✓ full adder circuit

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Chapter- 1 : Design of arithmetic combination circuits
Designing of half adder
❑ Half adder is a combinational circuit that adds two single-bit binary numbers and
produces two outputs: the sum and the carry. Truth table of circuit
❑ A half adder does not take into account any carry input from previous A B S C
calculations
❑ We can draw Block diagram
0 0 0 0
0 1 1 0
A Sum (S)
HA ≡
B Carry(C) 1 0 1 0

Half adder 1 1 0 1

ഥ B + A𝑩
S= 𝑨 ഥ =A⨁B C = A.B
𝐵ത B 𝐵ത B
𝐴ҧ 0 1 𝐴ҧ 0 0
𝐴 1 0 𝐴 0 1
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Chapter- 1 : Design of arithmetic combination circuits
Designing of full adder
➢ A full adder is a combinational circuit that adds three single-bit binary numbers: two
input bits (A and B) and a carry input (𝑪𝒊𝒏 ). A S
➢ It produces two outputs sum (S), carry out 𝑪𝒐𝒖𝒕
➢ Takes into account a carry-in from the previous addition B FA
𝐶𝑖𝑛 𝐶𝑜𝑢𝑡
Truth table of circuit
A B 𝐶𝑖𝑛 S 𝐶𝑜𝑢𝑡 S ത 𝑖𝑛
𝐵𝐶 ത 𝑖𝑛
𝐵𝐶 𝐵𝐶𝑖𝑛 ҧ
𝐵 𝐶𝑖𝑛
𝐴ҧ 0 1 0 1
0 0 0 0 0 𝐴 1 0 1 0 ത 𝑖𝑛 𝐵𝐶
𝐶𝑜𝑢𝑡 𝐵𝐶 ത 𝑖𝑛 𝐵𝐶𝑖𝑛 ҧ
𝐵 𝐶𝑖𝑛
0 0 1 1 0
S=𝐴.ҧ 𝐵.
ത 𝐶𝑖𝑛 + 𝐴.ҧ 𝐵. 𝐶𝑖𝑛 + 𝐴. 𝐵.
ത 𝐶𝑖𝑛 + 𝐴. 𝐵. 𝐶𝑖𝑛 = 𝐴ҧ 0 0 1 0
0 1 0 1 0 (𝐴 ⨁ 𝐵)⨁𝐶𝑖𝑛 𝐴 0 1 1 1
0 1 1 0 1
1 0 0 1 0 𝐶𝑜𝑢𝑡 = ഥ𝐴. 𝐵. 𝐶𝑖𝑛 + 𝐴. 𝐵.
ത 𝐶𝑖𝑛 + 𝐴. 𝐵. 𝐶𝑖𝑛 +
1 0 1 0 1 𝐴. 𝐵. 𝐶𝑖𝑛 = (𝐴 ⨁ 𝐵). 𝐶𝑖𝑛 + 𝐴. 𝐵 = 𝐴. 𝐵 +
𝐴. 𝐶𝑖𝑛 + 𝐵. 𝐶𝑖𝑛
1 1 0 0 1
1 1 1 1 1
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 Chapter- 1 : Design of arithmetic combination circuits
Design of full adder by half adder To design a full adder using half adders, we
needs:
from half adder To full adder • Uses two half adders and an OR gate.
S= (𝐴 ⨁ 𝐵)⨁𝐶𝑖𝑛 • First half adder: Adds A and B to get an
S= 𝐴 ⨁ 𝐵 A intermediate sum and carry.
A • Second half adder: Adds intermediate
HA B FA
B sum with Cin.
• OR gate: Combines both carry outputs.
𝐶𝑖𝑛
C= 𝐴. 𝐵 𝐶𝑜𝑢𝑡 = (𝐴 ⨁ 𝐵). 𝐶𝑖𝑛 + 𝐴. 𝐵

1st half adder

S= (𝐴 ⨁ 𝐵)⨁𝐶𝑖𝑛
A S
HA1 HA2
B
Cout 2nd half adder
Cin
𝐶𝑜𝑢𝑡 = (𝐴 ⨁ 𝐵). 𝐶𝑖𝑛 + 𝐴. 𝐵

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Chapter- 1 : Design of arithmetic combination circuits
Design of 4 bits adder B4B3B2B1 A4A3A2A1
❑ A parallel adder (also called a cascading adder) is used to add multi-bit binary
numbers.
❑ It is constructed by connecting multiple full adders in series, where each full adder C 4-bit full Adder
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handles one bit of the input numbers.
❑ The carry output of one full adder is connected to the carry input of the next full
adder, allowing the addition of numbers with multiple bits. S3 S2 S1 S0
Carry bit from the
A= (A4, A3, A2, A1) B= (B4, B3, B2, B1) previous stage.
A4 A3 A2 A1
B4 B3 B2 B1

c 4 c3 c2 c1 .
+ A4 A3 A2 A1 C0 =0
+ B4 B3 B2 B1 C0 =0 FA FA FA FA
────────
C4 S3 S2 S1 S0
c3 c2 c1 C4 C3 C2 C1
S3 S2 S1 S0
 Chapter- 1 : Design of arithmetic combination circuits
Design of half subtractor Design of Full subtractor
➢ A half subtractor is a combinational circuit that ➢ The full subtractor performs subtraction of three
performs subtraction of two single-bit binary single-bit binary numbers: two input bits (A and B) and
numbers. a borrow input (Bin).
➢ It has two inputs (A and B) and two outputs: ➢ It produces two outputs: the difference (D) and
the difference (D) and the borrow (Bout). the borrow output (Bout).
Truth table of circuit A D
A B 𝐵𝑖𝑛 D 𝑩𝑜𝑢𝑡 B FS
A Diff (D)
HS 0 0 0 0 0 𝐵𝑜𝑢𝑡
B Borrow(Bout)
𝐵𝑖𝑛
0 0 1 1 1
ҧ + A𝐵ത = A ⨁ B
D= 𝐴B ҧ
𝐵𝑜𝑢𝑡 = 𝐴𝐵 0 1 0 1 1
0 1 1 0 1
Truth table of circuit 1 0 0 1 0
A B D 𝐵𝑜𝑢𝑡 1 0 1 0 0
1 1 0 0 0
0 0 0 0
1 1 1 1 1
0 1 1 1
𝐵𝑜𝑢𝑡 = ഥ𝐴𝐵𝐵
ത 𝑖𝑛 + 𝐴𝐵𝐵ҧ 𝑖𝑛 + 𝐴𝐵𝐵ҧ 𝑖𝑛
1 0 1 0 D=𝐴.ҧ 𝐵.
ത 𝐵𝑖𝑛 + 𝐴.ҧ 𝐵. 𝐵𝑖𝑛 + 𝐴. 𝐵.
ത 𝐵𝑖𝑛 +
+ 𝐴𝐵𝐵𝑖𝑛 = (𝐴 ⨁ 𝐵). 𝐵𝑖𝑛 + 𝐴.ҧ 𝐵
1 1 0 0 𝐴. 𝐵. 𝐵𝑖𝑛 = (𝐴 ⨁ 𝐵)⨁𝐵𝑖𝑛 15
𝐵𝑜𝑢𝑡 = 𝐴.ҧ 𝐵 + ഥ𝐴. 𝐵𝑖𝑛 + 𝐵. 𝐵𝑖𝑛
Chapter- 1 : Design of arithmetic combination circuits
Design of 4 bits full subtractor with full adder
➢ To design a full subtractor using full adders, we can leverage the fact that subtraction can be achieved by
adding the minuend A with the two's complement of the subtrahend B.
➢ The two's complement of a binary number can be obtained by flipping all the bits and then adding 1 to
the result.
▪ A – B = A + (-B) = A +2’s complement of (B)= A +(1’s complement of (B) +1)
▪ 1’s complement of (B)= 𝑩 ഥ

A4 B4 A3 B3 A2 B2 A1 B1

C0=1

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0 16
 Chapter- 1 : Design of arithmetic combination circuits
Design of full adder /subtractor
➢ A full adder/subtractor is a versatile circuit that can perform both addition and subtraction. It uses the
same set of inputs for both operations
➢ By adding a control signal (C), we can configure the circuit to operate as either an adder or a subtractor
When C is 0, addition is performed; when C is 1, subtraction is performed.
➢ The XOR gate is used to toggle between the input A and its complement 𝑨 ഥ based on the Signal control
C (0/1)
C Operation A⨁C 𝑪𝒊𝒏 /𝑩𝒊𝒏
0 Addition 𝑨 0
1 Subtraction ഥ
𝑨 1
S= D = (𝐴 ⨁ 𝐵)⨁𝐶𝑖𝑛

ഥ. 𝐵
𝐵𝑜𝑢𝑡 = (𝑨 ⨁ 𝑩). 𝐵𝑖𝑛 + 𝑨

𝐶𝑜𝑢𝑡 = (𝑨 ⨁ 𝑩). 𝐶𝑖𝑛 + 𝑨. 𝐵 17

Chapter- 1 : Design of arithmetic combination circuits
Design of 4 bits full adder /subtractor
➢ Each bit of B is XORed with the control signal (C).
C Operation B⨁C 𝑪𝒊𝒏
• If C=0, B remains unchanged (for addition).
0 Addition 𝑩 0
• If C=1, B is complemented (for subtraction) ഥ
1 Subtraction 𝑩 1

B4 B3 B2 B1
C(0/1)

A4 A3 A2 A1

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0 18
Chapter- 1 : Design of arithmetic combination circuits
Magnitude Comparator
➢ A magnitude comparator is a combinational circuit used to compare the magnitudes of two binary numbers. It
determines whether one number is greater than, less than, or equal to the other.

The outcome of the comparison is specified by three binary variables that indicate whether A > B, A = B, or A < B.

A G (A > B) Greater
1-bit E (A = B) Equal
B comp
S (A < B) Smaller

A B E G S ≡
𝑬 = 𝐴.ҧ 𝐵ത + 𝐴. 𝐵 = (𝐴 ⨁ 𝐵)
0 0 1 0 0
G= 𝐴. 𝐵ത ;
0 1 0 0 1 𝑺 = 𝐴.ҧ 𝐵
1 0 0 1 0
1 1 1 0 0 ഥ +𝑨
𝑬 = 𝑨. 𝑩 ഥ . 𝑩 = ( 𝑮 + 𝑺)
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Chapter- 1 : Design of arithmetic combination circuits Truth table of circuit
A2 A1 B2 B1 A>B A=B A<B
2-bits Magnitude Comparator
0 0 0 0 0 1 0
➢ A 2-bit comparator compares the magnitudes of two 2-bit
0 0 0 1 0 0 1
binary numbers A=A2 A1, B= B1B2
0 0 1 0 0 0 1
A2 G (A > B) Greater 0 0 1 1 0 0 1
A
A1 2-bits E (A = B) Equal 0 1 0 0 1 0 0
B B2 comp
S (A < B) Smaller 0 1 0 1 0 1 0
B1
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
It can be said that :
1 0 0 1 1 0 0
𝐴 = 𝐵 𝑖𝑓 𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 = 𝐵1 ;
𝐴 > 𝐵 𝑖𝑓 𝐴2 > 𝐵2 𝒐𝒓 𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 > 𝐵1 ; 1 0 1 0 0 1 0
𝐴 < 𝐵 𝑖𝑓 𝐴2 < 𝐵2 𝒐𝒓𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 < 𝐵1 1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 20 0
Chapter- 1 : Design of arithmetic combination circuits
2-bits Magnitude Comparator
➢ A 2-bit comparator compares the magnitudes of two 2-bit binary numbers A=A2 A1, B= B2B1

A>B A<B
B2B1 00 01 11 10 B2B1 00 01 11 10
A2 A1 A2 A1

00 00 1 1 1
01 1 01 1 1
11 1 1 1 11
10 1 1 10 1

𝐵2 𝐴2 + 𝐵2 𝐵1 𝐴1 + 𝐵2 𝐴2 𝐴1 𝐴2 𝐵2 + 𝐴2 𝐴1 𝐵1 + 𝐴1 𝐵2 𝐵1

B2B1 00 01 11 10
A2 A1

00 1
01 1 𝐴1 ⨁ 𝐵1 (𝐴2 ⨁ 𝐵2 )
A=B
11 1
10 1 21
 Chapter- 1 : Design of arithmetic combination circuits
2-bit comparator using 1-bit comparators
G (A > B) E (A = B) S (A < B)
➢ It is possible to create a 2-bit comparator using 1-bit comparators
and logic gates.
➢ One comparator should be used to compare the least significant
bits, and another one to compare the most significant bits.
➢ The outputs of the two comparators used must be combined to
generate the outputs of the final comparator.

As a result:
𝐴 = 𝐵 𝑖𝑓 𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 = 𝐵1 ;
𝐹𝑒 = 𝐸1 𝐸2

𝐴 > 𝐵 𝑖𝑓 𝐴2 > 𝐵2 𝒐𝒓 𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 > 𝐵1 ;

𝐹𝑔 = 𝐺2 + 𝐸1𝐺1

𝐴 < 𝐵 𝑖𝑓 𝐴2 < 𝐵2 𝒐𝒓𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 < 𝐵1

𝐹𝑠 = 𝑆2 + 𝐸2𝑆1

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Chapter- 1 : Design of data transmission circuits
Multiplexers Block Diagram:
➢ A multiplexer , often abbreviated as "mux," is a multi-input and single- D0
output combinational circuit.
➢ The basic operation of a multiplexer involves selecting one information D1 Output
Mux

Input
from a set of 2n possible input and passing its data to the output line based 2n:1 Y

,
,,,,,,,,,,,,,,,,
on a selection signal. Dm
➢ Multiplexers come in different configurations, such as 2-to-1, 4-to-1, 8-to-1,
etc., depending on the number of input lines and the size of the control ,,,,,,,,,,,,,,,,
,

signal. Sn-1 S0
➢ Basic Multiplexing Switch:
Select
.

1. Two-to-one-line multiplexer

D0 S0 Y
Mux
Input

D1 Y 0 D0 𝐹 = 𝐷0. 𝑆0 + 𝑆0 𝐷1
2:1 Output
1 D1
23
S0
 Chapter- 1 : Design of data transmission circuits
Multiplexers Block Diagram:
2. Four -to-one-line multiplexer D0
➢ A 4-to-1 multiplexer (often denoted as 4:1 mux) is a type of multiplexer that D1 Output
Mux

Input
has four input lines and one output line. It selects one of the four input lines D2 4:1 Y
based on the combination of selection lines. D3
.
S1 S0 Y
0 0 D0 S1 S0
0 1 D1 𝑌 = 𝑆0 𝑆ഥ1 𝐷0 + 𝑆0 𝑆ഥ1 𝐷1+ 𝑆0 𝑆1 𝐷2 + 𝑆0 𝑆1 𝐷3
1 0 D2
1 1 D3

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 Chapter- 1 : Design of data transmission circuits
Multiplexers E
2. Four -to-one-line multiplexer D0
➢ In case we need to take into consideration the enable, the truth table is D1 Output
Mux

Input
modified as follows: D2 4:1 Y

E S1 S0 Y 𝑌 = 𝐸(𝑆0 𝑆ഥ1 𝐷0 + 𝑆0 𝑆ഥ1 𝐷1+ 𝑆0 𝑆1 𝐷2 + 𝑆0 𝑆1 𝐷3) D3

0 X X 0 Block Diagram
1 0 0 D0 S1 S0
1 0 1 D1
1 1 0 D2
1 1 1 D3
E S1 S0 Y
➢ This enable is used to activate the multiplexer, when it is high, the mux works, when it is 1 X X 0
low, the mux is disabled. The multiplexer can be either active high or active low.
0 0 0 D0
➢ In other hand, when it is active low, then the multiplexer works when the enable is set to 0 as 0 0 1 D1
in the following truth table: 𝑌 = 𝐸ത (𝑆 𝑆ഥ 𝐷0 + 𝑆 𝑆ഥ 𝐷1+ 𝑆 𝑆 𝐷2 + 𝑆 𝑆 𝐷3)
0 1 0 1 0 1 0 1 0 1 0 D2
➢ The logic expression for the following active low multiplexer is: 0 1 1 25 D3
 Chapter- 1 :Design of data transmission circuits
Multiplexers Block Diagram
3. Eight -to-one-line multiplexer D0
➢ A 8-to-1 multiplexer (often denoted as 8:1 mux) is another type of multiplexer that D1
has 8 input lines D0, D1, D2…………..D7 , single output line (Y) and three select D2

Input
(control) line (S0, S1,S2). D3 Output
S2 S1 S0 Y D4 Mux Y
D5 8:1
0 0 0 D0
D6
0 0 1 D1
D7
0 1 0 D2
0 1 1 D3 𝑌 = 𝑆2 𝑆ഥ1 𝑆0 𝐷0 + 𝑆2 𝑆ഥ1 𝑆0 𝐷1+ 𝑆2 𝑆1 𝑆0 𝐷2 +
1 0 0 D4 𝑆2 𝑆1 𝑆0 𝐷3 + 𝑆2 𝑆ഥ1 𝑆0 𝐷4 + 𝑆2 𝑆ഥ1 𝑆0 𝐷5 + S2 S1 S0
𝑆2 𝑆1 𝑆0 𝐷6 + 𝑆2 𝑆1 𝑆0 𝐷7
1 0 1 D5
1 1 0 D6
1 1 1 D7
26
 Chapter- 1 : Design of data transmission circuits
Multiplexers
4. 8-to-1 Mux using 4-to-1 Mux and 2-to-1 Mux
➢ If you observe the Boolean Expression of 8-to-1 Multiplexer shown above, we consider the multiplexer is in active high, we
can re-write it as follows:
𝑌 = 𝑆2 𝑆ഥ1 𝑆0 𝐷0 + 𝑆2 𝑆ഥ1 𝑆0 𝐷1+ 𝑆2 𝑆1 𝑆0 𝐷2 + 𝑆2 𝑆1 𝑆0 𝐷3 + 𝑆2 𝑆ഥ1 𝑆0 𝐷4 + 𝑆2 𝑆ഥ1 𝑆0 𝐷5 + 𝑆2 𝑆1 𝑆0 𝐷6 + 𝑆2 𝑆1 𝑆0 𝐷7

𝑌 = 𝑆2 (𝑆ഥ1 𝑆0 𝐷0 + 𝑆ഥ1 𝑆0 𝐷1+ 𝑆1 𝑆0 𝐷2 + 𝑆1 𝑆0 𝐷3) + 𝑆2 (𝑆ഥ1 𝑆0 𝐷4 + 𝑆ഥ1 𝑆0 𝐷5 + 𝑆1 𝑆0 𝐷6 + 𝑆1 𝑆0 𝐷7)

The expression in the first red bracket is similar to the Boolean Expression of a 4-to-1 Multiplexer with D0, D1, D2 and D3
as inputs and S1 and S0 as Select Lines. Let this expression be P1. P1 = (𝑆ഥ1 𝑆0 𝐷0 + 𝑆ഥ1 𝑆0 𝐷1+ 𝑆1 𝑆0 𝐷2 + 𝑆1 𝑆0 𝐷3)

Similarly, the expression in the second blue bracket is similar to the Boolean Expression of another 4-to-1 Multiplexer with
D4, D5, D6 and D7 as inputs and S1 and S0 as Select Lines. Let this expression be P2. P2 = (𝑆ഥ1 𝑆0 𝐷4 + 𝑆ഥ1 𝑆0 𝐷5 +
𝑆1 𝑆0 𝐷6 + 𝑆1 𝑆0 𝐷7)
Now, replacing the above expressions with P1 and P2, we get : 𝑌 = 𝑆2 𝑃1 + 𝑆2 𝑃2

This expression is similar to a 2-to-1 Multiplexer with P1 and P2 (where, P1 and P2 are outputs of respective 4-to-1
Multiplexers) as Inputs and S2 as Select Signal. So, finally, we can deduce that an 8-to-1 Multiplexer can be implemented
using two 4-to-1 Multiplexers and one 2-to-1 Multiplexer. The block diagram of the same is shown below: 27
 Chapter- 1 : Design of data transmission circuits
Multiplexers
4. 8-to-1 Mux using 4-to-1 Mux and 2-to-1 Mux
So, finally, we can deduce that an 8-to-1 Multiplexer can be implemented using two 4-to-1 Multiplexers and one 2-to-1
Multiplexer. The block diagram of the same is shown below:

Block Diagram
D0
D1 Mux P1 Mux Output
Y
D2 4:1 2:1
D3

S1 D4
S0
D5 P2 S2
Mux
D6 4:1
D7
S1 S0
28
 Chapter- 1 : Design of data transmission circuits
Implementing Boolean Functions with Multiplexers

5. EXEMPLE1

The lighting of a stairwell in a three-story building is governed by the following operating conditions:

There is one switch per floor, and the lights are on if:
• Only one switch is activated.
• All three switches are activated.
1. Establish the truth table for this system.
2. Deduce the expression of the output function E.
3. Implement the function governing the operation of the system using a 4-to-1 multiplexer

6. EXEMPLE2
1. Implement the product-of-sums Boolean function expressed by ς 1,2,5 by a suitable multiplexer.

29
 Chapter- 1 : Design of data transmission circuits
Implementing Boolean Functions with Multiplexers
5. EXEMPLE
1. Establish the truth table for this system.
A B C L 2. the expression of the output function E.
0 0 0 0 L= 𝐴ҧ𝐵𝐶 ҧ 𝐶+
ത + 𝐴𝐵 ҧ 𝐴𝐵ത 𝐶ҧ + 𝐴𝐵𝐶

0 0 1 1 3. Implement the function governing the operation of the system using a 4-to-1 multiplexer
To implement this function using a 4-to-1 multiplexer, we set up the logical function
0 1 0 1 of the system term by term with the logic function of the 4-to-1 multiplexer.
0 1 1 0 L= 𝐴ҧ𝐵𝐶 ҧ 𝐶+
ത + 𝐴𝐵 ҧ 𝐴𝐵ത 𝐶ҧ + 𝐴𝐵𝐶 Y= 𝑆ഥ1 𝑆0 𝐷0 + 𝑆ഥ1 𝑆0 𝐷1+ 𝑆1 𝑆0 𝐷2 + 𝑆1 𝑆0 𝐷3
1 0 0 1
A= S1 𝑎𝑛𝑑 𝐵 = 𝑆0 D0= C C
1 0 1 0 ≫
D1= 𝐶ҧ D0 Y=L
1 1 0 0 D2= 𝐶ҧ D1 Mux
D3= C 4:1
D2
1 1 1 1
D3
30
A B
Chapter- 1 : Design of data transmission circuits
Implementing Boolean Functions with Multiplexers
6. EXEMPLE2

1. Let the Boolean function be f(A, B, C) = ς 1,2,5 .

2. The equivalent sum-of-products expression can be written as f A, B, 𝐶 = σ 0,3,4,6,7
F= 𝐴ҧ𝐵ത 𝐶ҧ + 𝐴𝐵𝐶+
ҧ 𝐴𝐵ത 𝐶ҧ + 𝐴𝐵𝐶ҧ + 𝐴𝐵𝐶
The truth table for the given Boolean function is given in the Table below, The given function can be implemented with a 4-
to-1 multiplexer with two selection lines.

Y= 𝑆ഥ1 𝑆0 𝐷0 + 𝑆ഥ1 𝑆0 𝐷1+ 𝑆1 𝑆0 𝐷2 + 𝑆1 𝑆0 𝐷3

A Boolean function with n variables can be implemented with a MUX with ( n-1 ) selection lines
3 variable Boolean Function can be implemented with a 4 to 1 MUX (which has 2 selection lines)

During the implementation, starting from the MSB, the first ( n-1 ) variables are connected to the selection lines and the
last variable is connected to the data lines
In this example A and B is considered as selection line however C is connected to the input data

31
Chapter- 1 : Design of data transmission circuits
6. EXEMPLE2 Implementing Boolean Functions with Multiplexers
1. Let the Boolean function be f(A, B, C) = ς 1,2,5 .
2. The equivalent sum-of-products expression can be written as f A, B, 𝐶 = σ 0,3,4,6,7
F= 𝐴ҧ𝐵ത 𝐶ҧ + 𝐴𝐵𝐶+
ҧ 𝐴𝐵ത 𝐶ҧ + 𝐴𝐵 𝐶ҧ + 𝐴𝐵𝐶
The truth table for the given Boolean function is given in the Table below, The given function can be implemented with a 4-
to-1 multiplexer with two selection lines.
A= S1 𝑎𝑛𝑑 𝐵 = 𝑆0 A B C F Fmux
A B C F
• When inputs A and B are 0, we notice the output is 1 for 𝐶ҧ 0 0 0 1 D0= 𝐶ҧ
0 0 0 1 and 0 for 𝐶 . We set 𝐶ҧ in the output,
0 0 1 0 0 0 1 0
• When inputs A and B are 0 and 1. We notice the output is C.
0 1 0 0 • when inputs A and B are 1 and 0, output is 1 in 𝐶ҧ 0 1 0 0 D1= C
0 1 1 1 • 0 1
finally when inputs A and B are 1. The output is always 1 E1 1
1 0 0 1 no matter the value of C. 1 0 0 1 D2= 𝐶ҧ
1 0 1 0 B1 C 1 0 1 0
A
1 1 0 1 D0 1 1 0 1 D3= 1
Y=F
1 1 1 1 D1 Mux 1 1 1 1
4:1
D2
D3
32
Chapter- 1 : Design of data transmission circuits
De-Multiplexers Block Diagram
➢ Contrary to multiplexer , DEMUX has only one input and many outputs. Its
output depends upon the input given to the select lines. A Demultiplexer Y0
Input
( DEMUX ) acts as a signal allocator. Din De_Mux :
➢ Suppose a demultiplexer has 2n number of outputs then it has n number of 1:2^n Y1

,
,,,,,,,,,,,,,,,,
select lines.
If a DEMUX has 22 number of output pins then total outputs are 4 and Ym
number of select lines are 2. It is represented as 1:4 DEMUX ( 1 input and 4 ,,,,,,,,,,,,,,,,
,
Output
output ). Sn-1 S0
➢ Like Mux, there are various types of demultiplexers available depending on
Select
the output configuration, such as 1 to 2, 1 to 4, 1 to 8, and 1 to 16.

1. One-to-Two-line demultiplexer
E Output En S Y1 Y0
0 X 0 0
Y0
Din DeMux 1 0 0 Din
2:1 Y1 1 1 Din 0 𝑌0 = 𝐸𝑛𝐷𝑖𝑛𝑆ҧ
de-multiplexer (active high) Y1 = En𝐷𝑖𝑛𝑆 33
S
Chapter- 1 : Design of data transmission circuits
1. One-to-four-line demultiplexer De-Multiplexers de-multiplexer (active low)
➢ 1:4 DEMUX has 22 number of output pins then total S1 S0 E Y0 Y1 Y2 Y3 Active low
outputs are 4, number of select lines are 2 and 1 input, x x 1 0 0 0 0
E 0 0 0 Din 0 0 0 𝑌0 = 𝑆ഥ1 𝑆0 𝐸Din
ത
Output
Y0 0 1 0 0 Din 0 0 𝑌1 = 𝑆0 𝑆ഥ1 𝐸Din
ത
Din Y1
deMux 1 0 0 0 0 Din 0 ത
𝑌2 = 𝑆1 𝑆0 𝐸Din
1:4 Y2
1 1 0 0 0 0 Din ത
𝑌3 = 𝑆1 𝑆0 𝐸Din
Y3
de-multiplexer (active high)
S0 S1 S1 S0 E Y0 Y1 Y2 Y3 Active high
x x 0 0 0 0 0
Block Diagram 0 0 1 Din 0 0 0 𝑌0 = 𝑆ഥ1 𝑆0 EDin
0 1 1 0 Din 0 0 𝑌1 = 𝑆0 𝑆ഥ1 EDin
1 0 1 0 0 Din 0 𝑌2 = 𝑆1 𝑆0 EDin
1 1 1 0 0 0 Din 𝑌3 = 𝑆1 𝑆340 EDin
 Chapter- 1 : Design of data transmission circuits
Implementing Boolean Functions with Demultiplexers
5. EXEMPLE Let M(A, B, C) be a function that gives the value of the majority of the variables A, B, and C.
Example M(1,0,1)=1 ; M(0,1,0)=0
Implement this function using a combination of logic gates and:
- 1:8 Demultiplexer (case 1: N° of select demux=number of input of given problem)
- Minimum of 1:4 Demultiplexer (case 2: N° of select demux≠number of input of given problem)
E
E A B C M
Case 1: N° of select demux=number of input of given
0 X X X 0 problem:
1 0 0 0 0 • No of select line =3 = number of inputs of given problem
1 0 0 1 0 • No of input=1
1 0 1 0 0 1 deMux • No of outputs =8
1 0 1 1 1 1:8 Y3 M ✓ We affect Each minterms to its equivalent in demux
1 1 0 0 0 outputs
Y5
1 1 0 1 1 ✓ We connect the active demux outputs with or gate to get
1 1 1 0 1 Y6 the final output of demux
1 1 1 1 1 Y7

35
A B C
Chapter- 1 : Design of data transmission circuits
Implementing Boolean Functions with Demultiplexers
5. EXEMPLE Let M(A, B, C) be a function that gives the value of the majority of the variables A, B, and C.
Example M(1,0,1)=1 ; M(0,1,0)=0
Case 2: N° of select demux≠number of input of given problem:
• We need for that two demux 1:4 and with B and C as a line of selection and we
use A as a enable for this two demux
• We affect Each minterms to its equivalent in demux outputs M
• We connect the active demux outputs with or gate to get the final output of E
demux M Y0
E A B C M 1
deMux Y1
0 X X X 0 1:4 Y2
1 0 0 0 0 Y3
deMux
1 0 0 1 0 A
1:4 E
1 0 1 0 0 B C
1 0 1 1 1
Y4
1 1 0 0 0 1 deMux Y5
1 1 0 1 1 deMux 1:4 Y6
1 1 1 0 1 1:4
1 1 1 1 1 Y7
B C 36
Chapter- 1 : Design of data transmission circuits
Difference between multiplexers and Demultiplexers

Multiplexer De-Multiplexer
Accepts multiple inputs and give one output Accepts one input and give multiple outputs
Known as data selector Known as data distributer
Have multiple inputs of data or signals Have multiple outputs of data or signals
Has several types: 2x1, 4x1, 8x1, 16x1 …etc Has several types: 1x2, 1x4, 1x8, 1x16 …etc
37
 Chapter- 1 : Design of data transmission circuits
Application
MULTIPLEXERS DEMULTIPLEXERS
Data Transmission Data Demultiplexing
In telecommunications, multiplexers are extensively used to combine In telecommunications and data communication systems, demultiplexers
multiple signals into one channel for transmission over a single line. This are used to extract individual data streams from a single channel or line,
allows efficient use of bandwidth and reduces costs. allowing the data to be directed to specific receivers.
Digital Communication Systems Address Decoding
Multiplexers are essential components in digital communication systems Demultiplexers play a crucial role in memory systems for address decoding.
like fiber optics, where they combine several data streams into one for They receive address signals and direct them to specific memory locations,
transmission through a single fiber. enabling read or write operations to targeted memory cells
e coût élevé et l'équipement de grande taille, le long temps de e coût élevé et l'équipement de grande taille, le long temps de
Analog-to-Digital Conversion Display Systems
préparation des échantillons, l'exigence d'un personnel formé préparation des échantillons, l'exigence d'un personnel formé
In data acquisition systems, multiplexers select different analog signals In display applications, demultiplexers can be used to control multiple
from multiple sensors or sources and feed them into an analog-to-digital display elements, such as LEDs or segments in a digital display. Each
converter (ADC) for conversion into digital form. output line can be connected to a separate display unit.
Address Decoding Addressable Latches
In computer memory systems, multiplexers are used for address decoding. Demultiplexers can be used to implement addressable latches, enabling
They select specific memory locations based on the address lines received selective storage or manipulation of data based on address inputs.
from the CPU, enabling read or write operations to the selected memory
cell.
38
 Chapter- 1 : Design of Transcoding circuits
Transcoding circuits
A transcoding circuit refers to a circuitry or system that converts data from one format or encoding scheme to another;
The three types of transcoding are as follows:

2n intput

n inputs
n inputs

Decoder 2n Output Encoder n outputs Trancoder p outputs

n to p

With n data inputs and 2n outputs, only When one of the inputs within the range of Transcoder: Converting from code1 to
one output is active at any given time. 2n is activated, the outputs indicate the code2
When a number is represented in pure corresponding input number using the • With n inputs and p outputs,
binary at the input, the corresponding selected binary code. • The construction of the transcoder is
output becomes activated. based to the specific conversion
 Chapter- 1 : Design of Transcoding circuits
Decoder
➢ A decoder is a combinational circuit that decodes the information on n input lines to a

n inputs
Decoder 2n Output
maximum of 2n unique output lines,
➢ One of this outputs will be Active High based on the combination of inputs present,

000
0 00

23 Output
22 Output
0/1 21 Output
1 inputs DEC 2 inputs DEC 3 inputs DEC
1:2 1 2:4 3:8
11 111

In Decoder 2x4 for example, When A,B= 00, Y0 is 1. When A,B =01, Y1 is 1. And so forth. The outputs are called one-
hot, because exactly one is “hot” (HIGH) at a given time.
LSB 0 Y0 Y0=1
A

22 Output
Y1
2 inputs DEC
0 Y2
B 2:4
MSB Y3
 Chapter- 1 : Design of Transcoding circuits
Decoder implementation

Implement a 2:4 decoder with AND, OR, and NOT gates. A B Y0 Y1 Y2 Y3 Logic function
Solution: Figure below shows an implementation for the 2:4 decoder 0 0 1 0 0 0 𝑌0 = 𝐴ҧ𝐵ത
using four AND gates. Each gate depends on either the true or the
complementary form of each input. 0 1 0 1 0 0 ҧ
𝑌1 = 𝐴𝐵
➢ In general, an n: 2n decoder can be constructed from 2n n-input AND
1 0 0 0 1 0 𝑌2 = 𝐴𝐵ത
gates that accept the various combinations of true or complementary
inputs. Each output in a decoder represents a single minterm. 1 1 0 0 0 1 𝑌3 = 𝐴𝐵
➢ For example, Y0 represents the minterm 𝑨 ഥ𝑩ഥ.
This fact will be handy when using decoders with other digital building A B
blocks.
Decoders can be combined with OR gates to build logic functions. the two-input XNOR function
using a 2:4 decoder and a single OR gate. Because each output of a decoder represents a single
minterm, the function is built as the OR of all the minterms in the function.
Y0
A Y1
DEC
2:4
Y2 Y= 𝐴ҧ𝐵ത + 𝐴𝐵 = (𝐴 ⨁ 𝐵)
B Y3
 Chapter- 1 : Design of Transcoding circuits
3 to 8 Decoder Designing Steps
A 3:8 decoder has three inputs (A, B, C) and eight outputs (Y0 to Y7). A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Logic
Determining the eight outputs is contingent upon the values of the function
three inputs. Thus, the truth table for this 3-line to 8-line decoder is
presented below. From the truth table, it is seen that only one of eight 0 0 0 1 0 0 0 0 0 0 0 𝑌0 = 𝐴ҧ𝐵ത 𝐶ҧ
outputs (Y0 to Y7) is selected based on three select inputs.
0 0 1 0 1 0 0 0 0 0 0 𝑌1 = 𝐴ҧ 𝐵𝐶
ത
A B C
0 1 0 0 0 1 0 0 0 0 0 ҧ 𝐶ҧ
𝑌2 = 𝐴𝐵

0 1 1 0 0 0 1 0 0 0 0 ҧ
𝑌3 = 𝐴𝐵𝐶

1 0 0 0 0 0 0 1 0 0 0 𝑌4 = 𝐴𝐵ത 𝐶ҧ
000 0 0 1 0 0 ത
1 0 1 0 0 0 𝑌5 = 𝐴𝐵C
23 Output

A
1 1 0 0 0 0 0 0 0 1 0 𝑌6 = 𝐴𝐵 𝐶ҧ
B DEC
C 3:8 1 1 1 0 0 0 0 0 0 0 1 𝑌7 = 𝐴𝐵𝐶
111
Utilizing these Boolean expressions, the 3 to 8 decoder
circuit can be realized by incorporating three NOT gates
and eight three-input AND gates.
 Chapter- 1 : Design of Transcoding circuits
3:8 Decoder implementation with Enable (E)
Recognized as a binary-to-octal decoder, the 3 to 8 line decoder E A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Logic
circuit operates exclusively when the Enable pin (E) is in a high function
state. The three distinct inputs, labeled as A, B, and C, dictate the
0 X X X 0 0 0 0 0 0 0 0
activation of one of the eight outputs—Y0, Y1, Y2, Y3, Y4, Y5,
Y6, and Y7. 1 0 0 0 1 0 0 0 0 0 0 0 𝑌0 = 𝐴ҧ𝐵ത 𝐶ҧ
The truth table and functioning of this 3-line to 8-line decoder can
be comprehended by consulting its function table, detailed 1 0 0 1 0 1 0 0 0 0 0 0 𝑌1 = 𝐴ҧ𝐵𝐶
ത
A B C
1 0 1 0 0 0 1 0 0 0 0 0 ҧ 𝐶ҧ
𝑌2 = 𝐴𝐵
1 0 1 1 0 0 0 1 0 0 0 0 ҧ
𝑌3 = 𝐴𝐵𝐶

000 1 1 0 0 0 0 0 0 1 0 0 0 𝑌4 = 𝐴𝐵ത 𝐶ҧ
23 Output

A
B DEC 1 1 0 1 0 0 0 0 0 1 0 0 ത
𝑌5 = 𝐴𝐵C
C 3:8 1 1 1 0 0 0 0 0 0 0 1 0 𝑌6 = 𝐴𝐵𝐶ҧ
111
1 1 1 1 0 0 0 0 0 0 0 1 𝑌7 = 𝐴𝐵𝐶

E The 3 to 8 line decoder is recognized also as a

binary-to-octal decoder,
 Chapter- 1 : Design of Transcoding circuits
Cascading Decoder Designing Steps
➢ To create a 3-line to 8-line decoder, we use a pair of 2-line to 4-line decoders.
➢ It needs three inputs labeled as A B, and C, along with eight outputs ranging from Y7 to Y0.
To facilitate the realization of higher-order decoders through lower-order counterparts, to implement a single 3 to 8 decoder, two
2-line to 4-line decoders are essential (8/4=2). BC are considered as inputs, however A is considered as enable E3,
The block diagram illustrating this configuration, utilizing two 2 to 4 decoders, is presented below
A=E B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Logic
Y4 function
Y5 0 0 0 1 0 0 0 0 0 0 0 𝑌0 = 𝐴ҧ𝐵ത 𝐶ҧ
DEC
Y6 0 0 1 0 1 0 0 0 0 0 0 𝑌1 = 𝐴ҧ𝐵𝐶
ത
2:4
A E Y7
0 1 0 0 0 1 0 0 0 0 0 ҧ 𝐶ҧ
𝑌2 = 𝐴𝐵
0 1 1 0 0 0 1 0 0 0 0 ҧ
𝑌3 = 𝐴𝐵𝐶
B Y0 1 0 0 0 0 0 0 1 0 0 0 𝑌4 = 𝐴𝐵ത 𝐶ҧ
C Y1
1 0 1 0 0 0 0 0 1 0 0 ത
𝑌5 = 𝐴𝐵C
DEC Y2
2:4
1 1 0 0 0 0 0 0 0 1 0 𝑌6 = 𝐴𝐵 𝐶ҧ
E Y3 1 1 1 0 0 0 0 0 0 0 1 𝑌7 = 𝐴𝐵𝐶
Chapter- 1 : Design of Transcoding circuits
Creating a logical function using decoder
▪ A decoder with N input generates at its output 2N outputs.
▪ Each output is asserted for a unique input combination each output corresponds to a minterm
▪ Any Logic/Boolean function can be represented by a decoder followed by an OR gate sums all its minterms.

Example: we will introduce an updated version of the control system for our robot. Our approach involves employing a
decoder to identify the various possible combinations of push buttons. Consequently, each movement action will be linked to an
output of the decoder. Below, we have revisited the truth table of the robot's control system, retaining only the rows where at
least one output equals 1. Additionally, we have included an indication of the active decoder output for each row.

A B C D Output of MGA MGR MDA MD

Decoder R

1 0 0 0 D8 1 0 1 0
0 1 0 0 D4 0 1 0 1
MGA = 𝐴𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴ҧ𝐵ത 𝐶𝐷
ҧ + A𝐵ത 𝐶𝐷
ҧ 0 0 1 0 D2 0 1 1 0
ҧ 𝐶ҧ 𝐷
ഥ + 𝐴ҧ 𝐵𝐶
ത 𝐷 ҧ 𝐶𝐷
ഥ + 𝐴𝐵 ҧ 0 0 0 1 D1 1 0 0 1
MGR = 𝐴𝐵
1 0 1 0 D10 0 0 1 0
MDA = 𝐴𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴ҧ 𝐵𝐶
ത 𝐷ഥ + A𝐵𝐶
ത 𝐷ഥ 1 0 0 1 D9 1 0 0 0
0 1 1 0 D6 0 0 0 1
ҧ 𝐶ҧ 𝐷
MGR = 𝐴𝐵 ഥ + 𝐴ҧ 𝐵ത 𝐶𝐷
ҧ + 𝐴𝐵𝐶
ҧ 𝐷ഥ 0
0 1 0 1 D5 0 1 0 45
 Chapter- 1 : Design of Transcoding circuits
Implementing different logic circuits with decoder
To implement a full adder circuit using a decoder and two OR gates, you can follow these steps:
➢ Start by using the decoder to generate the sum outputs for each combination of input bits. The decoder will have three inputs
(A, B, and Cin) and eight outputs, where each output corresponds to a specific combination of A, B, and Cin.
➢ Use the outputs of the decoder as inputs to the OR gates. Connect the outputs of the decoder to the inputs of the OR gates in
such a way that each OR gate takes inputs from specific decoder outputs to generate the final sum and carry outputs of the
full adder.
Y0
A B 𝐶𝑖𝑛 S 𝐶𝑜𝑢𝑡
Y1
Y2 S 0 0 0 0 0
Cin Y3 0 0 1 1 0

B
DEC Y4 0 1 0 1 0
3:8 0 1 1 0 1
A Y5
Y6 C out
1 0 0 1 0
Y7 1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Chapter- 1 : Design of Transcoding circuits
Implementing different logic circuits with decoder
➢ A BCD to decimal decoder is a combinational logic circuit that takes a BCD input and generates a decimal output by
activating one of its output lines corresponding to the decimal value of the input. The decoder has four input lines for the BCD
code and 10 output lines for the decimal digits (0 to 9). A B C D Y Y Y Y Y Y Y Y Y Y
0 1 2 3 4 5 6 7 8 9

For example, when a BCD value of 1001 (decimal 9) is input

into the decoder, it activates the ninth output line, which 0 0 0 0 0 0 0 0 0 0 0 0 0 0
corresponds to the decimal number 9. Similarly, if the BCD 1
0 0 0 1 0 0 0 0 0 0 0 0 0
input is 0110 (decimal 6), the sixth output line will be activated,
representing the decimal number 6 0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0

0 1 0 0 0 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0

0 1 1 1 0 0 0 0 0 0 0 1 0 0

1 0 0 0 0 0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 0 0 0 0 0 0 1

A BCD to decimal decoder

Chapter- 1 : Design of Transcoding circuits
Implementing different logic circuits with decoder
➢ It is possible to operate a demultiplexer as a decoder. So at first lets obtain a 2:4 decoder by using 1:4 demux, we can
also obtain 3:8 decoder by using a 1:8 demux
➢ We have to look similarité between the two circuits, each one have 4 outputs, 2 inputs (we can consider the selection
lines of demux as inputs)
➢ And by applying din=1 and comparing the results of each circuit, we can find that the demux gives the same table of
decoder

S1 S0 Y0 Y1 Y2 Y3 A B Y0 Y1 Y2 Y3 Logic function
0 0 Din 0 0 0 𝑌0 = 𝑆ഥ1 𝑆0 Din 0 0 1 0 0 0 𝑌0 = 𝐴ҧ𝐵ത

0 1 0 Din 0 0 𝑌1 = 𝑆0 𝑆ഥ1 Din 0 1 0 1 0 0 ҧ

𝑌1 = 𝐴𝐵

1 0 0 0 Din 0 𝑌2 = 𝑆1 𝑆0 Din 1 0 0 0 1 0 𝑌2 = 𝐴𝐵ത

1 1 0 0 0 Din 𝑌3 = 𝑆1 𝑆0 Din 1 1 0 0 0 1 𝑌3 = 𝐴𝐵
 Chapter- 1 : Design of Transcoding circuits
Decoder Application
➢ One of the most popular used application of decoder is in ALU
- It’s Allows selecting the operation to be executed , weither addition , substraction, division or multiplication

▪ 𝑆2 𝑆1 𝑆0 =000, the output 𝑌0 =1, the other outputs are equals to zero , so
the function operated as S=ab
▪ 𝑆2 𝑆1 𝑆0 =001, the output 𝑌1 =1, the other outputs are equals to zero , so
the function operated as S=a+b
▪ And so on for the rest of operations

➢ Another application of decoder is in washing machine

Pre-wash
clock counter Rinsing
Decoder
2:4
Washing

Spin
 Chapter- 1 : Design of Transcoding circuits
Encoder
➢ An encoder is a combinational circuit that decodes the information on 2n input lines to a

2n inputs
maximum of n unique output lines, and its operation is exactly the opposite of decoder, Encoder n Output
➢ It will produce a binary code equivalent to the input, which is active High (1).
➢ There are different types of Encoders which are mentioned below.
4 to 2 Encoder
Octal to Binary Encoder (8 to 3 Encoder) E D0 D1 D2 D3 Y1 Y0 Output
Decimal to BCD Encoder description
Priority Encoder 0 0 0 0 0 x x Don’t works
• In encoder 2x4 for example, At any time, only one of these 4 inputs can
1 1 0 0 0 0 0 0
be ‘1’ in order to get the respective binary code at the output.
When D3,D2,D1,D0 = 0001, Y0 is 0 Y1 is 0. When D3,D2,D1,D0 = 0010, 1 0 1 0 0 0 1 1
Y0 =1, Y1= 0. And so forth.
The encoder generate a binary code equivalent to the number of input 1 0 0 1 0 1 0 2
activated, 1 0 0 0 1 1 1 3
22 inputs
D0 1
0 Y0 0 1 Other combinations x x Don’t care
D1 0 ENCO
2 Output
1 0
D2 0 2
4:2
0 3 Y1
D3
 Chapter- 1 : Design of Transcoding circuits
Encoder 22 inputs
D0 1
• At any time, only one of these 4 inputs can be ‘1’ in order to get the 0 Y0 0
respective binary code at the output. The Truth table of 4 to 2 encoder is D1 0 ENCO

2 Output
1 0
shown below. D2 0 4:2
2
• From Truth table, we can write the Boolean functions for each 0 Y1
D3 3
output as

𝑌1 00 01 11 10 𝑌0 01 11 10 E D3 D2 D1 D0 Y1 Y0 Out description
D1D0 D1D0 00
D3D2 D3D2

00 x 0 x 0 00 x 0 x 1 0 0 0 0 0 x x 0 Don’t works

01 1 x x x 01 1 x x x 1 0 0 0 1 0 0 0 𝑌0 = D1+D2
11 x x x x 11 x x x x 1 0 0 1 0 0 1 1 𝑌1 =D2+D3
10 1 x x x 10 0 x x x 1 0 1 0 0 1 0 2

𝑌0 = 𝐷1 + 𝐷2 1 1 0 0 0 1 1 3
𝑌1 = 𝐷2 + 𝐷3 𝐷2
1 Other combinations x x X Don’t care
𝐷1 𝑌0

𝐷3 𝑌1
 E D3(3) D2(2) D1(1) D0(0) Y1 Y0 Out description

Chapter- 1 : Design of Transcoding circuits 0 0 0 0 0 x x Don’t Works

1 0 0 0 1 0 0 0
Priority Encoder 1 0 0 1 0 0 1 1

➢ What if two inputs are 1 ? 1 0 0 1 1 0 1 1 ( the highest is

corresponding to D1
➢ Can use a priority encoder (1 in binary )
A 4 to 2 priority encoder has four inputs D3, D2, D1 & D0 and two 1 0 1 0 0 1 0 2(corresponding to
outputs Y1 &Y0. D2 ( in binary )

Here, the input, D3 has the highest priority, whereas the input, D0 has the 1 0 1 0 1 1 0 2(corresponding to
D2 ( in binary )
lowest priority. In this case, even if more than one input is ‘1’ at the same 1 0 1 1 0 1 0 2(corresponding to
time, the output will be the binary code corresponding to the input, D2 ( in binary )

which is having higher priority. 1 0 1 1 1 1 0 2(corresponding to

D2 ( in binary )
D1D0 00 01 11 10 D1D0 00 01 11 10 1 1 0 0 0 1 1 3(corresponding to
D3D2 D3D2 D3( in binary )
1 1 0 0 1 1 1 3(corresponding to
00 x 0 0 0 00 x 0 1 1 D3( in binary )
01 1 1 1 1 01 0 0 0 0 1 1 0 1 0 1 1 3(corresponding to
D3( in binary )
11 1 1 1 1 11 1 1 1 1 1 1 0 1 1 1 1 3(corresponding to
D3( in binary )
10 1 1 1 1 10 1 1 1 1 1 1 1 0 0 1 1 3(corresponding to
D3( in binary )
𝑌1 = 𝐷2 + 𝐷3 𝑌0 = 𝐷3 + 𝐷2𝐷1 1 1 1 0 1 1 1 3(corresponding to
D3( in binary )
𝑌0 1 1 1 1 0 1 1 3(corresponding to
D3( in binary )
1 1 1 1 1 1 1 3(corresponding to
𝑌1 D3( in binary )
Chapter- 1 : Design of Transcoding circuits
8 to 3 Priority Encoder
➢ This kind of encoder is also named an 8-bit or Octal to Binary priority encoder. This type of encoder consists of 8 inputs
and 3 outputs. When multiple inputs are active high at the same time, the input with the highest priority is considered to
represent the output.
• The output ‘Y2’ of a priority encoder is represented as
D7 D6 D5 D4 D3 D2 D1 D0 Y2 Y1 Y0 Out
active high or logic ‘1’ only when the inputs D4, D5, D6,
description
and D7 are active high.
0 0 0 0 0 0 0 1 0 0 0 0
• The output ‘Y1’ of an encoder is at logic 1 only when the
0 0 0 0 0 0 1 0 0 0 1 1 inputs D2, D3, D6, and D7 are active high.
• Similarly, the output ‘Y0’ is represented as logic ‘1’ only
0 0 0 0 0 1 0 0 0 1 0 2
when the inputs D1, D3, D5, and D7 are active high.
0 0 0 0 1 0 0 0 0 1 1 3

0 0 0 1 0 0 0 0 1 0 0 4 𝑌2

0 0 1 0 0 0 1 0 1 0 1 5 𝑌1
0 1 0 0 0 0 0 0 1 1 0 6
𝑌0
1 0 0 0 0 0 0 0 1 1 1 7
Chapter II: Sequential circuits

54