Table of Contents

1 List of Figure........................................................................................................ 4
2 EXPERIMENT 1: CMOS INVERTER..........................................................................5
2.1 Objective: Draw the schematic of a CMOS inverter. Obtain its DC transfer
characteristics and Transient response for nominal conditions...............................5
2.2 Theory............................................................................................................ 5
2.2.1 Inverter Schematic.................................................................................. 5
2.3 Draw the schematic of a CMOS inverter........................................................5
2.3.1 DC transfer characteristics......................................................................6
2.3.2 Transient Simulations..............................................................................7
2.4 The parametric analysis for different W/L ratios............................................7
2.4.1 Transition Voltages of the Inverter..........................................................8
2.4.2 Rising and falling delay for nominally sized inverter...............................8
2.5 Practice Questions:...................................................................................... 10
2.5.1 What is noise margin of a CMOS inverter?.............................................10
2.5.2 Explain sizing of an inverter?.................................................................10
2.5.3 Draw and explain the transfer curve of an inverter?.............................11
3 EXPERIMENT 2: Layout Design...........................................................................12
3.1 Objective:..................................................................................................... 12
3.2 Theory:......................................................................................................... 12
2.2.1 Pre Layout simulation:............................................................................... 12
2.2.2 Post Layout Simulation:.............................................................................12
3.3 LAYOUT VIEW OF AN INVERTER...................................................................13
3.3.1 Layout.................................................................................................... 13
3.3.2 Pre and Post Layout Simulation.............................................................13
3.3.3 Observation:.......................................................................................... 15
3.3.4 Calculation:............................................................................................ 15
3.4 Conclusion................................................................................................... 15
3.5 Practice Questions:...................................................................................... 16
3.5.1 Give five important design technique to follow when doing a layout
design of digital circuit?..................................................................................... 16
3.5.2 What do you mean by FEOL and BEOL process?...................................16
3.5.3 What should be the n-diffusion and p-diffusion layer in lambda rule?...16
4 EXPERIMENT 3.................................................................................................... 17
4.1 Objective:..................................................................................................... 17
 4.2 Theory:......................................................................................................... 17
4.3 Multi-stage Inverter with a FAN-OUT-4.........................................................17
4.3.1 Schematic.............................................................................................. 17
4.3.2 Observation........................................................................................... 18
4.4 Calculation................................................................................................... 19
4.5 Multi-stage Inverter with a FAN-OUT-1.........................................................19
4.5.1 Observation:.......................................................................................... 20
4.5.2 Conclusion............................................................................................. 20
4.6 Practice Questions....................................................................................... 21
4.6.1 What is propagation delay?...................................................................21
4.6.2 What happens to delay if load capacitance is increased?......................21
4.6.3 Why is rise time greater than fall time?.................................................21
5 EXPERIMENT 4: D-latch and D-Flip Flop..............................................................21
5.1 Theory:......................................................................................................... 21
5.1.1 D-latch................................................................................................... 21
5.1.2 D-Flip Flop.............................................................................................. 21
6 Assignment:....................................................................................................... 22
6.1 To Design a D latch using transmission gates as shown in fig.4 (a).............22
6.1.1 Conditions for Modelling:.......................................................................22
6.2 Observation:................................................................................................ 23
6.3 Conclusion:.................................................................................................. 23
6.4 To Design a D flip-flop using transmission gates as shown in fig.4 (b)........24
6.4.1 Schematic of D-flip flop.........................................................................24
6.5 Observation:................................................................................................ 25
6.6 Conclusion:.................................................................................................. 25
6.7 Practice Questions:...................................................................................... 26
6.7.1 What is the difference between D latch and D flip-flop?........................26
6.7.2 Write down the characteristic equation of D flip-flop?...........................26
6.7.3 Describe the operation of a negative edge triggered D flip-flop?..........27

1 EXPERIMENT 1: CMOS INVERTER

1.1 Objective: Draw the schematic of a CMOS inverter.
Obtain its DC transfer characteristics and Transient
response for nominal conditions.
1.2 Theory
A CMOS inverter contains a PMOS and a NMOS transistor connected at
the drain and gate terminals, a supply voltage V DD at the PMOS source
terminal, and a ground connected at the NMOS source terminal, where
VIN is connected to the gate terminals and V OUT is connected to the
drain terminals. It is important to notice that the CMOS does not
contain any resistors, which makes it more power efficient that a
regular resistor-MOSFET inverter. As the voltage at the input of the
CMOS device varies between 0 and 5 volts, the state of the NMOS and
PMOS varies accordingly.
1.2.1 Inverter Schematic

We Use 180 nm CMOS model from GPDK available in the library.

Assume maximum supply voltage for this technology is 1.8 V. The
nominal conditions are: wn = 1 μm, wp = 2 μm and channel length is
180 nm, Temperature is 27 ˚C.
1.3 Draw the schematic of a CMOS inverter.
Obtain its DC transfer characteristics and Transient response for
nominal conditions.
 Figure 1: Inverter schematic with wn = 1 μm, wp = 2 μm

Figure 2: Testbench of the inverter Obtain its DC transfer characteristics and Transient response
1.3.1 DC transfer characteristics

Figure 3: DC transfer characteristics of the inverter rise time of the input is 1 ms

1.3.2 Transient Simulations

1.4 The parametric analysis for different W/L ratios
PMOS of the inverter circuit. [Hint: Vary wp from 2 μm to 10 μm in step
size of 1 μm]

Figure 4: DC Transfer Characteristics PMOS of the inverter circuit. [Hint: Vary wp from 2 μm to 10 μm
in step size of 1 μm]

Figure 5: Parametric Simulation of temperature variations from -40 to 100 ˚C

1.4.1 Transition Voltages of the Inverter
Table 1: Midpoint voltage of the inverter with different aspect ratio

Aspect Ratio of
V (mV)
PMOS
2u 824.2
3u 848.6
4u 875.5
5u 897.2
6u 915.4
7u 947.4
8u 956.56
9u 968.45
10u 1.012

1.4.2 Rising and falling delay for nominally sized inverter.

Table 2: Rising and falling delay for nominally sized inverter.

Temperature
Fall time (ns) Rise Time (ns)
Value (˚C)
100 4.86 5.44
80 4.71 5.35
60 4.58 5.22
27 4.47 5.16
10 4.35 5.11
0 4.30 5.07
-10 4.21 4.98
-40 4.17 4.9
 Figure 6: DC Characteristic of the Inverter at different temperature

Figure 7: Rise and fall time of the inverter at different value of the Temperature
 Figure 8: Rise and Fall time w.r.t Sizing

1.5 Practice Questions:

1.5.1 What is noise margin of a CMOS inverter?
The noise margin of a CMOS inverter is a measure of its tolerance to noise in the
input signal. It indicates the range of acceptable input voltage levels that ensure
correct and reliable operation of the inverter. There are two types of noise margins:
High Noise Margin (NMH): It is the difference between the minimum input
voltage (VIL) that guarantees a low output and the maximum input voltage (VIH)
that guarantees a high output. Mathematically,
NMH = VIH - VIL.
Low Noise Margin (NML): It is the difference between the minimum input voltage
(VIL) that guarantees a high output and the maximum input voltage (VIH) that
guarantees a low output. Mathematically,
NML = VOL - VOH.
In a well-designed CMOS inverter, both NMH and NML should be sufficiently large to
ensure immunity to noise and variations in the input voltage.
1.5.2 Explain sizing of an inverter?
The sizing of an inverter refers to the selection of transistor widths (W) and lengths
(L) to achieve desired performance characteristics, such as speed, power
consumption, and noise margins. Here's an explanation of key aspects of inverter
sizing:
1.5.2.1 Transistor Width (W):
 Increasing the width (W) of transistors in an inverter enhances its drive
strength and speed.
 Larger W reduces resistance, allowing faster charging and discharging of
capacitive loads.
 However, larger W increases area and power consumption.
1.5.2.2 Transistor Length (L):
 Shorter lengths (L) reduce transistor switching times, improving speed.
 Shorter L also reduces power consumption due to lower resistance.
 However, shorter L can increase leakage current and susceptibility to process
variations.
1.5.2.3 Aspect Ratio (W/L):
 The aspect ratio (W/L) of transistors affects their performance.
 Increasing W/L improves drive strength and speed but may increase area and
power consumption.
 Balancing W/L based on design requirements optimizes performance and
efficiency.
1.5.2.4 Sizing Strategy:
 Designers use sizing strategies to optimize inverter performance.
 For example, aggressive sizing with larger W/L ratios improves speed but
may increase power consumption and area.
Conservative sizing with smaller W/L ratios reduces power and area but may
compromise speed.
Overall, inverter sizing involves trade-offs between speed, power, and area, and
designers select transistor dimensions based on specific design goals and
constraints.
1.5.3 Draw and explain the transfer curve of an inverter?
The curve shows a sharp transition from high to low and vice versa, indicating the
inverter's switching behavior. At the threshold voltage (Vth), the inverter transitions
from high to low or vice versa, resulting in a logic change at the output.
The transfer curve also illustrates key parameters like noise margins (NMH and
NML) and the input voltage range for reliable operation. Noise margins ensure the
inverter operates correctly despite noise or variations in Vin.
In summary, the transfer curve of an inverter provides valuable insights into its
logic levels, switching behavior, and operational characteristics, aiding in design
optimization and analysis.
2 EXPERIMENT 2: Layout Design
2.1 Objective:
Perform Layout design of a CMOS Inverter in Cadence Virtuoso Layout Editor.
Perform DRC, LVS and RCX. Obtain the DC transfer characteristics and
transient response for different widths and temperature conditions and
compare with the values obtained in Experiment 1.
2.2 Theory:
Design rule checking or check(s) (DRC) is the area of electronic design
automation that determines whether the physical layout of a particular
chip layout satisfies a series of recommended parameters called
design rules. The Layout Versus Schematic (LVS) is the class of
electronic design automation (EDA) verification software that
determines whether a particular integrated circuit layout corresponds
to the original schematic or circuit diagram of the design.
2.2.1 Pre Layout simulation: It is the functional verification of the
design without including the parasitics, which gets added to the design
when the design is physically implemented or laid out.
2.2.2 Post Layout Simulation: The parasitic capacitances extracted
according to how layout is designed might be critical in affecting the
actual performance of the design. In order to get an idea of how the
design would work from the layout, you should perform a post-layout
simulation from the extracted view.
2.3 LAYOUT VIEW OF AN INVERTER
2.3.1 Layout

Figure 9: Layout of the Inverter Cell in 180nm GPDK

2.3.2 Pre and Post Layout Simulation

Simulation Type Fall time (ns) Rise time (ns)

Pre layout 4.475 5.16
simulations
Post layout 4.63 5.3
simulations
Figure 10: Pre and post layout simulations of the fall time

Figure 11: Pre and post layout simulations of the rise time
 Figure 12:Pre and Post layout propagation delay

2.3.3 Observation:
The rise and fall time of the inverter is little bit higher in post layout simulations
because of parasitic capacitance of interconnect.

2.3.4 Calculation:

Pre-Layout Simulation value of fall time= 6.44 ns

Pre-Layout Simulation value of rise time= 6.98 ns
Post- Layout Simulation value of fall time= 6.94 ns
Post- Layout Simulation value of fall time= 7.57 ns
Pre-Layout Simulation value of propagation Delay = 4.96 ns
Post-Layout Simulation value of propagation Delay = 5.82 ns
2.4 Conclusion
The rise and fall time of the pre- layout simulation is less than the post layout
simulation of the inverter. And propagation delay of the inverter is higher in post
layout simulation as compared to the pre layout simulations. Because of the
parasitic capacitance of the inverter.
2.5 Practice Questions:
2.5.1 Give five important design technique to follow when

doing a layout design of digital circuit?

Signal Integrity: Minimize signal paths, use differential signaling, and

adhere to trace guidelines.
Power and Grounding: Design robust power distribution and
separate ground planes.
Clock Distribution: Ensure a clean clock network with minimal skew
and use clock gating.
Component Placement: Optimize component placement for signal
integrity and routing simplicity.
EMC/ESD Protection: Incorporate measures like shielding, filtering,
and ESD protection structures for reliability and electromagnetic
compatibility.
2.5.2 What do you mean by FEOL and BEOL process?

FEOL (Front-End Of Line) and BEOL (Back-End Of Line) processes are

key stages in semiconductor manufacturing:
2.5.2.1 FEOL (Front-End Of Line) Process:
 FEOL refers to the initial stages of semiconductor fabrication,
where transistors and other active components are formed on the
silicon wafer.
 Processes in FEOL include doping, oxidation, deposition, and
etching to create the transistor structures and interconnects.
2.5.2.2 BEOL (Back-End Of Line) Process:
 BEOL occurs after the FEOL process and involves the creation of
metal layers, interconnects, and insulation layers that connect
the transistors and form the integrated circuit's wiring.
 BEOL processes include metal deposition, patterning, dielectric
deposition, via formation, and interlayer dielectric (ILD)
deposition.
In summary, FEOL focuses on creating the semiconductor device's
active components, while BEOL focuses on interconnecting these
components to form a functional integrated circuit.
2.5.3 What should be the n-diffusion and p-diffusion layer

in lambda rule?
In the GPDK (Generic Process Design Kit) for a 180 nm technology node, the lambda
(λ) value is typically defined as 0.18 μm (180 nm). The n-diffusion and p-diffusion
layers in lambda rules for this technology node are commonly specified as follows:
n-diffusion width = 6 λ (6 * 0.18 μm = 1.08 μm)
p-diffusion width = 6 λ (6 * 0.18 μm = 1.08 μm)
These dimensions ensure proper spacing and isolation between n-type and p-type
diffusion regions, which is crucial for the correct functioning and performance of
CMOS integrated circuits fabricated using the GPDK 180 nm process.

3 EXPERIMENT 3
3.1 Objective:
Extraction of Logical effort and parasitic delay of a CMOS
inverter.
3.2 Theory:
Logical effort of a logic gate is defined as the ratio of its input
capacitance to that of an inverter that delivers equal output current.
The method of logic effort is an easy way to estimate delay in a CMOS
circuit. We can select the fastest candidate by comparing delay
estimates of different logic structures. The method also specifies the
proper number of logic stages on a path and the best transistor sizes
for the logic gates. Parasitic delay is the delay due to intrinsic delay of
gate mostly the drain capacitance. It is independent of output load and
sizing. The delay incurred by a logic gate is comprised of two
components:
 A fixed part called as the parasitic delay, p.
 A part that is proportional to the load on the gate’s output, called
the effort
delay or stage effort, f.
d=f+p
The effort delay depends on the load and on properties of the logic
gate driving
the load. We introduce two related terms for these effects:
 The logical effort, g captures properties of the logic gate.
 The electrical effort h characterizes the load.
f = gh
Therefore,
 d = gh +p.
3.3 Multi-stage Inverter with a FAN-OUT-4
3.3.1 Schematic

Schematic Representation of Multi-stage inverter logic network with a

fan-out- 4.

Figure 13: Schematic Representation of Multi-stage inverter logic network with a fan-out- 4.
 Figure 14: Propagation delay of the Multi-stage inverter logic network with a fan-out- 4

3.3.2 Observation

Rising propagation delay time (tpdr1) = 126.56 ps

Falling propagation delay time (tpdf1) = 116.35 ps
3.4 Calculation
FO4 delay = (tpdr1 + tpdf1)/2 = 5τ
τ= time constant in 24.291 ps

3.5 Multi-stage Inverter with a FAN-OUT-1

Schematic Representation of Multi-stage inverter logic network with a
fanout-of-1
 Figure 15: Schematic Representation of Multi-stage inverter logic network with a fanout-of-1

Figure 16: Propagation delay of Multi-stage inverter logic network with a fanout-of-1

3.5.1 Observation:

Rising propagation delay time (tpdr2) = 154.418 ps

Falling propagation delay time (tpdf2) = 1.4 ns
Calculation:
According to d = gh +p, now we have two equations,

(𝑡𝑝𝑑𝑟1 + 𝑡𝑝𝑑𝑓1)/2 = 𝑔𝑥4 + 𝑝

777.209 ps = g*1+p

(𝑡𝑝𝑑𝑟2 + 𝑡𝑝𝑑𝑓2)/2 = 𝑔𝑥1 + 𝑝

g = 903.7 – 56.3 ps = 847.4 ps

121.455 ps = g*1+p
g = 777.209 – 121.455 ps = 655.54 ps
By solving above 2 equations,
g = 655.54 ps
p = 10 ps
3.5.2 Conclusion
The rise and the fall tine of the fan out of 4 inverter is much less than the fan out of
1. Because the driving strength is greater than the fan out of 1.

3.6 Practice Questions

3.6.1 What is propagation delay?
Propagation delay in an inverter refers to the time taken for the output signal to
transition from one state to another in response to a change in the input signal. It
includes both the rising delay (time for output to switch from low to high) and falling
delay (time for output to switch from high to low). This delay is crucial in digital
circuits as it affects the overall speed and performance of the system.

3.6.2 What happens to delay if load capacitance is

increased?
If the load capacitance in a digital circuit is increased, the propagation delay
typically also increases. This is because the increased load capacitance requires
more charge to be transferred during each signal transition. As a result, it takes
longer for the output voltage to reach its final value, leading to a longer propagation
delay. This effect is especially noticeable in high-speed circuits where even small
changes in load capacitance can significantly impact the overall delay and
performance.

3.6.3 Why is rise time greater than fall time?

Rise time is often greater than fall time in digital circuits due to differences in the
characteristics of the transistors used for pulling the signal high (NMOS transistors)
and low (PMOS transistors). NMOS transistors typically have faster switching speeds
compared to PMOS transistors. As a result, when the input signal changes from low
to high, the NMOS transistors can turn on more quickly, leading to a shorter rise
time. Conversely, when the input signal changes from high to low, the PMOS
transistors take longer to turn on, resulting in a longer fall time.

4 EXPERIMENT 4: D-latch and D-Flip Flop.

Objective:Design and characterization of D-Latch and D-
FlipFlop in CMOS Technology.
4.1 Theory:
4.1.1 D-latch

Latch is an electronic device that can be used to store one bit of

information. The D latch is used to capture, or 'latch' the logic level
which is present on the Data line when the clock input is high or low
depending on the type of level triggering.
High level triggering: If the data on the D line changes state while the
clock pulse is high, then the output, Q, follows the input, D. When the
CLK input falls to logic 0, the last state of the D input is trapped and
held in the latch. Low level triggering: If the data on the D line changes
state while the clock pulse is low, then the output, Q, follows the input,
D. When the CLK input rises to logic 1, the last state of the D input is
trapped and held in the latch.
4.1.2 D-Flip Flop

The working of D flip flop is similar to the D latch except that the
output of D Flip Flop takes the state of the D input at the moment of a
positive edge at the clock pin (or negative edge if the clock input is
active low) and delays it by one clock cycle. That's why, it is commonly
known as a delay flip flop. The D flipflop can be interpreted as a delay
line or zero order hold. The advantage of the D flip-flop over the D-type
"transparent latch" is that the signal on the D input pin is captured the
moment the flip flop is clocked, and subsequent changes on the D
input will be ignored until the next clock event.

5 Assignment:

5.1 To Design a D latch using transmission gates as shown

in fig.4 (a).
5.1.1 Conditions for Modelling:

180 nm CMOS model from GPDK

wn = 1μm, wp = 2μm, channel length = 180 nm, temperature = 27 ˚C.
 Figure 17: D latch schematic in GPDK 180nm

Figure 18: Simulations waveforms of the D latch

5.2 Observation:
Clock Parameters: Rise time =___2 ns
Fall time = _2__ns,
Pulse width = _148__ ns,
Period = _300__ ns,
Input Parameters: Rise time = __1_ ns
Fall time =_1__ns,
Pulse width = _199__ ns,
Period =__400_ ns,
Output Parameters: Rise time = __30.801_ ps
Fall time =__340.454_ps,
Propagation delay = __345.263_ ps,

5.3 Conclusion:
The rise and fall times of the clock signal are balanced at 2 ns each,
indicating a symmetrical clock waveform. The input signal has faster
rise and fall times compared to the clock signal, suggesting a more
abrupt transition. The output parameters show that the D latch has a
relatively fast rise time but a significantly slower fall time, which may
be due to the circuit's design or load characteristics. The propagation
delay of 345.263 ps indicates the time taken for the output to respond
to changes in the input, reflecting the latch's overall speed and
performance.
In conclusion, the D latch exhibits acceptable performance
characteristics with a fast rise time but a slower fall time, which could
be further optimized depending on specific application requirements.
5.4 To Design a D flip-flop using transmission gates as
shown in fig.4 (b).
5.4.1 Schematic of D-flip flop

Figure 19: Schematic diagram of the D flip flop

Figure 20: Simulation waveforms of the D flip flop

5.5 Observation:
Clock Parameters: Rise time =___2 ns
Fall time = _2__ns,
Pulse width = _148__ ns,
Period = _300__ ns,
Input Parameters: Rise time = __1_ ns
Fall time =_1__ns,
Pulse width = _199__ ns,
Period =__400_ ns,
Output Parameters: Rise time = __30.69_ ps
Fall time =__29.63_ps,
Propagation delay = __428.29_ ns,
5.6 Conclusion:
 The clock signal has symmetrical rise and fall times of 2 ns each,
with a pulse width of 148 ns and a period of 300 ns.
 The input signal has faster rise and fall times compared to the
clock signal, indicating sharper transitions.
 The output parameters show that the D flip-flop has extremely
fast rise and fall times in the picosecond range, indicating high-
speed operation.
 The propagation delay of 428.29 ns reflects the time taken for
the flip-flop to capture and propagate changes from the input to
the output.
In conclusion, the D flip-flop exhibits very fast rise and fall times,
making it suitable for high-speed applications. However, the
propagation delay is relatively high, which may be a consideration for
timing-critical designs.
5.7 Practice Questions:
5.7.1 What is the difference between D latch and D flip-

flop?

The main difference between a D latch and a D flip-flop lies in their

behavior and functionality:
5.7.1.1 Functionality:
D Latch: It is level-sensitive and transparent, which means it updates
its output continuously based on the input as long as the clock signal is
active.
D Flip-Flop: It is edge-triggered and stores data only on the rising or
falling edge of the clock signal, depending on its design (positive-edge
or negative-edge triggered).
5.7.1.2 Control Input:
D Latch: It typically has a single input (D) for data and an optional
enable input to control its operation.
D Flip-Flop: It has a data input (D) and a clock input (CLK) to trigger
the storage of data.
5.7.1.3 Output Behavior:
D Latch: Its output changes immediately in response to changes in
the input as long as the clock signal is active, making it suitable for
continuous updates and feedback systems.
D Flip-Flop: Its output changes only on the edge of the clock signal,
providing a stable output between clock transitions, which is useful for
synchronous operations and timing control.
5.7.1.4 Timing Considerations:
D Latch: It is more prone to glitches and timing hazards due to its
continuous updating nature, especially in asynchronous designs.
D Flip-Flop: It offers better timing control and synchronization,
making it preferred for sequential logic designs and avoiding glitches.
Overall, while both D latches and D flip-flops store data, their
operational characteristics and timing behavior make them suitable for
different applications. D latches are simpler and more suitable for
continuous data updating, while D flip-flops offer better timing control
and synchronization for sequential logic operations.
5.7.2 Write down the characteristic equation of D flip-flop?

The characteristic equation of a D flip-flop describes how the next state

(Q_next) depends on the current state (Q), the D input, and the clock
input (CLK). For a positive-edge-triggered D flip-flop, the characteristic
equation is:
𝑄next = 𝐷
In words, this equation means that the next state of the D flip-flop
(Q_next) is equal to the D input when the clock input (CLK) transitions
from low to high (positive edge). This equation signifies that the D flip-
flop stores and updates its state based on the D input when triggered
by the rising edge of the clock signal.
5.7.3 Describe the operation of a negative edge triggered

D flip-flop?

A negative edge-triggered D flip-flop operates based on the falling

edge of the clock signal (CLK). Here's how it works:
Initial State: The flip-flop starts in an initial state, typically denoted as
Q (current state).
Clock Signal: The D flip-flop waits for the falling edge (transition from
high to low) of the clock signal to occur.
Data Input (D): At the moment of the falling edge of the clock signal,
the flip-flop samples and stores the value of the D input.
Output Update: After the falling edge of the clock, the flip-flop
updates its output (Q_next) based on the sampled value of the D input.
Next State: The updated output becomes the new state of the flip-
flop, ready for the next clock cycle.
The key difference between a negative edge-triggered and a positive
edge-triggered D flip-flop is the timing of when the input data is
sampled and stored. In a negative edge-triggered flip-flop, the data is
captured and updated on the falling edge of the clock signal, while in a
positive edge-triggered flip-flop, it's done on the rising edge of the
clock signal.