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A Quick Guide To Understanding Makefiles.

The document provides an overview of Makefile structure, including targets, dependencies, and commands. It explains the use of variables, phony targets, automatic variables, and pattern rules, along with examples. Additionally, it covers the inclusion of other Makefiles for modularization purposes.

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vitthal ghasti
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39 views3 pages

A Quick Guide To Understanding Makefiles.

The document provides an overview of Makefile structure, including targets, dependencies, and commands. It explains the use of variables, phony targets, automatic variables, and pattern rules, along with examples. Additionally, it covers the inclusion of other Makefiles for modularization purposes.

Uploaded by

vitthal ghasti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Makefile Notes

Makefile Workflow Diagram

Basic Structure of a Makefile

target: dependencies
command

- 'target' is the file to generate (e.g., executable, object file).


- 'dependencies' are files that the target depends on.
- 'command' is the shell command to run (must start with a tab).

Example Makefile

hello: hello.o
gcc -o hello hello.o

hello.o: hello.c
gcc -c hello.c

clean:
rm -f hello hello.o

- 'make hello' compiles the program.


- 'make clean' removes build files.
Makefile Notes

Variables in Makefiles

CC = gcc
CFLAGS = -Wall

hello: hello.o
$(CC) -o hello hello.o $(CFLAGS)

- Define variables for compiler and flags.


- Use $(VAR) to reference variables.

Phony Targets

.PHONY: clean

clean:
rm -f *.o hello

- '.PHONY' declares 'clean' as not a real file.


- Useful to avoid conflicts with files of the same name.

Automatic Variables

$@ - target name
$< - first dependency
$^ - all dependencies

Example:
%.o: %.c
$(CC) -c $< -o $@

- This builds .o files from .c files generically.

Pattern Rules (Wildcard Rules)

%.o: %.c
$(CC) -c $(CFLAGS) $< -o $@

- Defines a general rule for converting .c to .o files.


- Useful for larger projects with many files.
Makefile Notes

Including Other Makefiles

include common.mk

- Allows modularization of Makefiles.


- Use to reuse settings and rules.

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