Flip-Flops

 Sequential logic is a type of digital logic circuit where the

output depends not only on the current input but also on the
history of the input.
 This contrasts with combinational logic, where the output
depends only on the current inputs.
 Sequential logic circuits use storage elements like latches
and flip-flops to maintain a memory of past inputs, allowing
them to produce different outputs based on different
sequences of inputs.
Combinational Circuit Sequential Circuit
 In this output depends only  In this output depends upon
upon present input. present as well as past input.
 There is no feedback between  There exists a feedback path
input and output. between input and output.
 This is time independent.  This is time dependent. ( They
consider both past and present
 Elementary building blocks:
inputs to generate an output.)
Logic gates
 Elementary building blocks:
 Used for arithmetic as well as
Flip-flops
boolean operations.
 Mainly used for storing data.
Combinational Circuit Sequential Circuit
 Combinational circuits don’t  Sequential circuits have
have capability to store any capability to store any state or
state. to retain earlier state.(The
system memorizes the state in
 As combinational circuits don’t
which it is in).
have clock, they don’t require
triggering.  As sequential circuits are clock
dependent they need
 These circuits do not have any
triggering.
memory element.
 These circuits have memory
 It is easy to use and handle.
element.
 It is not easy to use and handle.
Combinational Circuit Sequential Circuit
Key Concepts in Sequential Logic:
 State: The current condition of the circuit, determined by the stored
information.
 Clock: A signal that synchronizes changes in the state of the circuit,
ensuring that updates occur at specific intervals.
 Flip-Flops: Basic storage elements used to store one bit of
information. They are triggered by clock signals.
 Latches: Similar to flip-flops but typically do not rely on clock
signals; instead, they change state based on the input signals.
Multivibrators
 Multivibrators are a class of sequential logic circuits used to implement
various types of timing and state-keeping functions. They are
categorized into three types based on their stability and how they
respond to inputs:
1. Bistable Multivibrators:
 Definition: Bistable devices have two stable states called SET and
RESET and remain in one state until an external trigger causes them to
switch to the other state.
 Example: Flip-flops are common bistable devices.
 Applications: Used in memory storage elements, registers, and
toggle switches.
2. Monostable Multivibrators:
•Definition: Monostable devices have one stable state and one unstable
state. When triggered, they temporarily switch to the unstable state and
then return to the stable state after a predetermined time.
•Example: One-shot pulse generators.
•Applications: Used in timers, pulse width modulation, and event
detection.
3. Astable Multivibrators:
•Definition: Astable devices have no stable states and continuously
oscillate between two states without requiring an external trigger.
•Example: Oscillators and clock generators.
•Latches are a type of temporary storage device with two stable
states (bistable).
•They are distinct from flip-flops, although they share similarities:
•Both are bistable devices, meaning they can reside in one of two
possible states.
•They use a feedback arrangement, where the outputs are
connected back to the opposite inputs.
•Key Difference: The primary difference between latches and flip-flops
lies in the method used for changing their state.
 Note on S-R Latches
 Latch Type: A latch is a bistable logic
device (or multivibrator).
 Active-HIGH S-R Latch:
 Formed with two cross-coupled NOR
gates.
 Active-LOW S-R Latch:
 Formed with two cross-coupled NAND
gates.
 Feedback:
 The output of each gate is connected to
the input of the opposite gate, creating
regenerative feedback, a key
characteristic of latches and flip-flops.
SR Latch Using NOR Gates(Active High)

 Set State (S = 1, R = 0):

 The Set input (S) is high. The output of the first NOR gate (Q) becomes low
(because NOR gate outputs low when any input is high).
 The output of the second NOR gate (Q') becomes high (since the other input is
now low).
 Reset State (S = 0, R = 1):
 The Reset input (R) is high. The output of the second NOR gate (Q') becomes
low.
 The output of the first NOR gate (Q) becomes high (since the other input is
now low).
 No Change (S = 0, R = 0):
 Both NOR gates maintain their previous outputs due to the feedback.

 Invalid State (S = 1, R = 1):

 Both inputs of each NOR gate are high, leading to both outputs being low,
which is an undefined or invalid state.
SR Latch Using NOR Gates(Active High)

 Set State (S = 1, R = 0):

 The Set input (S) is high. The output of the first NOR gate (Q) becomes low
(because NOR gate outputs low when any input is high).
 The output of the second NOR gate (Q') becomes high (since the other input is
now low).
 Reset State (S = 0, R = 1):
 The Reset input (R) is high. The output of the second NOR gate (Q') becomes
low.
 The output of the first NOR gate (Q) becomes high (since the other input is
now low).
 No Change (S = 0, R = 0):
 Both NOR gates maintain their previous outputs due to the feedback.

 Invalid State (S = 1, R = 1):

 Both inputs of each NOR gate are high, leading to both outputs being low,
which is an undefined or invalid state.
 SR Latch Using NAND Gates (Active Low)
 For NAND gates, the concept of active high is reversed:
 Inputs: The Set (S) and Reset (R) inputs are considered
active low. This means:
 Set State (S = 0, R = 1): When the Set input (S) is low, and the
Reset input (R) is high, the SR latch will set its output Q to high (1)
and Q' to low (0).
 Reset State (S = 1, R = 0): When the Set input (S) is high, and the
Reset input (R) is low, the SR latch will reset its output Q to low (0)
and Q' to high (1).
 No Change (S = 1, R = 1): When both inputs are high, the latch
retains its previous state.
 Invalid State (S = 0, R = 0): If both inputs are low, the latch is in
an undefined state.
•Enable Input (EN or G):
•The gated latch requires an enable input, often designated as EN or G.
•The S and R inputs control the latch’s state only when EN is HIGH.
•Level-Sensitive Operation:
•The gated latch is level-sensitive, meaning it responds to the state of the S and R inputs as long as EN is
HIGH.
•Output Control:
•When EN is HIGH, the latch’s output is controlled by the state of the S and R inputs:
•S = HIGH and R = LOW: Sets the latch (Q = 1, Q' = 0).
•S = LOW and R = HIGH: Resets the latch (Q = 0, Q' = 1).
•S = LOW and R = LOW: Retains the previous state (no change).
•S = HIGH and R = HIGH: Invalid state.
•Invalid State:
•The latch enters an invalid state when both S and R are HIGH simultaneously while EN is also HIGH.
 Single Data Input (D):
 The D latch has only one input in addition to the enable input (EN). This input is called the D (data)
input.
 Behavior:
 When D is HIGH and EN is HIGH, the latch will set (Q = 1).
 When D is LOW and EN is HIGH, the latch will reset (Q = 0).

 Output Follows Input:

 The output Q directly follows the state of the D input as long as EN is HIGH.

 Simplified Operation:
 Unlike the S-R latch, the D latch eliminates the possibility of an invalid state since it only has one input
(D) controlling the output.
 This makes the D latch a more straightforward and reliable choice for certain applications
where the output should follow the input when enabled.
•Definition: Flip-flops are synchronous bistable devices, also known as bistable
multivibrators.
•Synchronous Operation:
•The term "synchronous" refers to the fact that the output of a flip-flop changes
state only at a specific point on the triggering input, known as the clock (CLK).
•The output is synchronized with the clock, meaning changes occur at the leading
or trailing edge of the clock signal.
•Clock (CLK):
•The clock (CLK) is the control input that determines when the flip-flop will
change its state.
•Designated as input C in many diagrams.
Edge-Triggered:
•Flip-flops are edge-triggered, meaning they respond to changes in the
clock signal's edge (either rising or falling).
•This is in contrast to gated latches, which are level-sensitive and respond
to the level of the enable input.
•Comparison with Gated Latches:
•Flip-flops change states in synchronization with the clock edge, while
gated latches respond to the enable signal’s level.
•Application:
•Commonly used in digital circuits where precise timing and
synchronization are required.
Edge-Triggered Flip-Flops:
Behavior:
•An edge-triggered flip-flop changes its state at the transition of the clock pulse, either at
the positive edge (rising edge) or at the negative edge (falling edge).
•The flip-flop is sensitive to its inputs only during this clock transition.
Types of Edge-Triggered Flip-Flops:
•The two types covered are D flip-flops and J-K flip-flops.
•Both types can be either:
•Positive edge-triggered (rising edge, indicated by no bubble at the clock input).
•Negative edge-triggered (falling edge, indicated by a bubble at the clock input).
•Logic Symbols:
•The logic symbol for an edge-triggered flip-flop includes a small triangle at the clock
(C) input.
•This triangle is called the dynamic input indicator and signifies edge-triggered
behavior.
Edge-Triggered Flip-Flops:
Synchronous Input:
•The D input of the D flip-flop is a synchronous input, meaning data on the D input is transferred to
the flip-flop's output only at the triggering edge of the clock pulse.
Basic Operation:
•When D is HIGH: The Q output goes HIGH on the triggering edge of the clock pulse, and the flip-flop
is SET.
•When D is LOW: The Q output goes LOW on the triggering edge of the clock pulse, and the flip-flop
is RESET.
Triggering Edge:
•The flip-flop changes state only on the triggering edge of the clock pulse, which is typically the
positive edge for a positive edge-triggered D flip-flop.
Input Changes:
•The D input can be changed at any time when the clock input is LOW or HIGH without affecting the
output, except for a very short interval around the triggering transition of the clock.
•Key Point:
•The output Q follows the D input at the triggering edge of the clock, meaning the state of Q is
directly determined by the state of D at that moment.
Synchronous Inputs:
•The J and K inputs are synchronous, meaning the data on these inputs are transferred to the
flip-flop’s output only at the triggering edge of the clock pulse.
Operation Based on J and K Inputs:
•J HIGH, K LOW: The Q output goes HIGH (flip-flop is SET) on the triggering edge of the clock
pulse.
•J LOW, K HIGH: The Q output goes LOW (flip-flop is RESET) on the triggering edge of the
clock pulse.
•J LOW, K LOW: The output remains unchanged (no change in state).
•J HIGH, K HIGH: The flip-flop toggles its state (changes from HIGH to LOW or LOW to HIGH).
Triggering Edge:
•The flip-flop changes state only on the triggering edge of the clock pulse (positive edge for
positive edge-triggered flip-flops).
Input Changes:
•The J and K inputs can be changed at any time when the clock is LOW or HIGH, except for a
brief moment around the clock transition, without affecting the output.
 The Master-Slave flip-flop is a type of sequential circuit that consists of two flip-
flops connected in series: the Master flip-flop and the Slave flip-flop. This
configuration provides edge-triggered behavior and avoids the issues associated
with level-sensitive latches. Here's an overview:
 Operation
 Master Flip-Flop:
 The Master flip-flop captures the input data on the rising edge of the clock signal.
 It is active during the first half of the clock cycle (when the clock is HIGH).

 Slave Flip-Flop:
 The Slave flip-flop updates its output based on the data stored in the Master flip-flop.
 It is active during the second half of the clock cycle (when the clock is LOW).
Behavior
 Positive Edge-Triggered Operation:
 During the rising edge of the clock, the Master flip-flop captures and holds the input
data.
 The Slave flip-flop updates its output based on the state of the Master flip-flop when the
clock transitions from HIGH to LOW.
 Data Transfer:
 The Master flip-flop captures the input data during the high phase of the clock.
 The Slave flip-flop transfers this data to its output during the low phase of the clock.

 Prevention of Race Conditions:

 This design avoids race conditions and ensures that the output changes only on the clock
edge, providing stable and predictable behavior.
Applications of Flip-Flops
 Counters:
 Binary Counters: Flip-flops are used in binary counters to count pulses or events. They
can be configured in various ways (e.g., ripple or synchronous counters) to count up or
down.
 Frequency Dividers: Flip-flops divide the input frequency by 2, making them essential in
frequency synthesis and clock generation.
 Registers:
 Shift Registers: These are used to shift data bits in serial or parallel form and are used in
data storage, serial-to-parallel conversion, and data transfer applications.
 Storage Registers: Used in microprocessors and memory units to store data temporarily.
Applications of Flip-Flops
 Memory Units:
 Static RAM (SRAM): Flip-flops are used in SRAM to store each bit of data, providing fast
access times compared to dynamic RAM (DRAM).
 Data Synchronization:
 Clocked Flip-Flops: Used to synchronize data signals with a clock to prevent timing
issues and ensure reliable data transfer in digital systems.
 Sequential Circuits:
 Finite State Machines (FSMs): Flip-flops are used to implement state machines, which
are crucial in control systems, digital communication, and complex decision-making
processes.
 .
Applications of Latches
 Data Storage:
 Temporary Storage: Latches are used to hold data temporarily in digital circuits, such as
in data buffers and temporary storage elements.
 Level-Sensitive Memory Elements:
 Gated Latches: Useful in situations where data needs to be held or passed through based
on the level of an enable signal. For example, in digital switches and control circuits.
 Debouncing:
 Switch Debouncing: Latches can be used to stabilize the signal from mechanical
switches, reducing noise and ensuring clean transitions between states.
Applications of Latches

•Clock Gating:
•Power Management: Latches are used in clock gating to control the
clock signal to various parts of a circuit, reducing power consumption by
disabling the clock when it is not needed.
•Pulse Shaping:
•Pulse Generation: Latches can generate specific timing pulses or
delays based on input signals, useful in timing and control applications.