Module 3 Part 2
Module 3 Part 2
• Specification
• Formulation - Obtain a state diagram or state table
• State Assignment - Assign binary codes to the states
• Flip-Flop Input Equation Determination - Select flip-flop types and derive
flip-flop equations from next state entries in the table
• Output Equation Determination - Derive output equations from output
entries in the table
• Optimization - Optimize the equations
• Technology Mapping - Find circuit from equations and map to flip-flops
and gate technology
• Verification - Verify correctness of final design
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Formulation: Finding a State Diagram
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Circuit, State Diagram, State Table
Minimization
Binary Counter
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Circuit, State Diagram,
State Table
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Circuit, State Diagram, State Table
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Circuit, State Diagram, State Table
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Circuit, State Diagram, State Table
Terms:
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Circuit, State Diagram, State Table
Sequential circuit components:
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Circuit, State Diagram, State Table
State diagram:
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Circuit, State Diagram, State Table
State table:
Left column => current state Top row => input combination
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Circuit, State Table, State Diagram
Example:
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Circuit, State Table, State Diagram
Example:
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Circuit, State Table, State Diagram
Example:
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Circuit, State Table, State Diagram
Example:
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Circuit, State Table, State Diagram
Example:
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circuit
state table
state diagram
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0 0
1
00/0 01/0
1 1
11 /1 10 /0
1
0 0
circuit
state table
state diagram
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0 0
1
00/0 01/0
1 1
11 /1 10 /0
1
0 0
circuit
state table
state diagram
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Circuit, State Table, State Diagram
Example:
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Circuit, State Diagram, State Table
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Circuit, State Diagram, State Table
Example: state diagram = state
table
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Circuit, State Diagram, State Table
Example: Show the state diagram of following circuit
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Circuit, State Diagram, State Table
Example: Show the state diagram of following circuit
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Circuit, State Diagram, State Table
More Example: Binary Counter – show state diagram and
table
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Circuit, State Diagram, State Table
More Example: Binary Counter – show state diagram and
table
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Circuit, State Diagram, State Table
Quiz:
http://www.eelab.usyd.edu.au/digital_tutorial/part3/t-
diag.htm
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