Microprocessor Question Bank

Q.1 Draw and explain the block diagram of 8255. Also explain different operating modes of 8255. (M 2016) (M 2015)
(M 2018)

1. Figure shows the internal block diagram of 8255A. It consists of data bus buffer, control
logic and Group A and Group B controls.
2. Data Bus Buffer: This tri-state bi-directional buffer is used to interface the internal data lilts
of 8255 to the system data bus. Input or Output instructions executed by the CPU either
Read date from or Write data into the buffer. Output data from the CPU to the ports or
control register, and input data to the CPU from the ports or status register are all passed
through the buffer.

1. Control Logic: The control logic block accepts control bus signals as well as inputs from
the address bus, and issues commands to the individual group control blocks (Group A
control and Group B control). It issues appropriate enabling signals to access the required
data/control words or status word. The input pins for the control logic section are described
here.
2. Group A and Group B Controls: Each of the Group A and Group B control blocks receives
control words from the CPU and issues appropriate commands to the ports associated
 with it. The Group A control block controls Port A and PC_7-PC_4 while the Group B
control block controls Port B and PC_3-PC_0.
3. Port A: This has an 8-bit latched and buffered output and an 8-bit input latch. It can be
programmed in three modes: mode 0, mode 1 and mode 2.
4. Port B: This has an 8-bit data I/O latch/ buffer and an 8-bit data input buffer. It can be
programmed in mode 0 and mode 1.
5. Port C: This has one 8-bit unlatched input buffer and an 8-bit output latch/buffer. Port C
can be spitted into two parts and each can be used as control signals for ports A and B in
the handshake mode. It can be programmed for bit set/reset operation.

Q.2 Compare 8086 , 80386 and Pentium. (M 2016)

Parameter 8086 80386 Pentium

Year of Introduction 1978 1985 `1993

Data Bus 16 bit 32 bit 128 bit

`Address Bus 20 bit 32 bit 64 bit

Physical memory 1 MB 4 GB 4 GB

Register size 16 bit 32 bit 32 bit

Voltage required 5V 5V 3.3V ...

Q.3 Differentiate between real mode and protected mode. (M 2016)

Real Mode:

1. Following a system reset the 386 is initialized in Real Mode. In this mode the chip looks
virtually identical to an 8086. That is, it has the following features:
 o The address space is limited to 1 MB using address lines AO-A19 (the high address
lines A20-A31 are inactive).
o The segment memory addressing mechanism of the 8086 is retained with each
segment limited to 64 KB.
2. Two new features are available to the programmer in Real Mode—access to the 32-bit
register set of the 386 and the addition of two new segments called F and G. This will be
explained in more detail when the programming model is introduced later in this chapter.

Protected Mode:

1. The primary difference between Real Mode and Protected Mode is the latter's new
addressing mechanism and protection levels.
2. Although memory segments are still retained, each segment may range from a single byte
to 4 GB (the full physical address space of the 386).
3. The addresses stored in the segment registers are now interpreted as pointers into a
descriptor table.
4. Each segment's entry in this table is eight bytes long and identifies the 32-bit base address
of the segment, the segment size, and the access rights. Memory addresses are
computed by adding the offset specified by the instruction to the segment base address.

Q.4 Explain memory segmentation with Pros and cons(M 2016)

Advantages of memory segmentation:

 Allow the memory capacity to be 1 MB even though the addresses associated with the
individual instructions are 16 bits wide.
 Allow the use of separate memory areas for the program code and data and stack portion
of the program.
 Permit a program and/or its data to be placed into different areas of memory whenever the
program is end.
 Multitasking becomes easy
 The advantage of having separate code and data segments is that one program can work
on different sets of data This is possible by reloading the data segment register (DS) to the
point to the new data.
 The advantage of segment memory is that the reference logical addressed can be loaded
into the instruction pointer (IP) and run the program anywhere in the segment memory as
the logical address varies from 0000H to FFFFH.
 Programs are re-locatable so that programs can be run at any location in the memory.
Disadvantages of memory segmentation:

1. External fragmentation is present

2. Costly memory management algorithms.
3. Segmentation finds free memory area big enough.
4. Paging keep list of free pages.
5. Segments of unequal size not suited as well for swapping.

Q.5 Explain programming model of 8086. (M 2016)

PROGRAMMER'S MODEL OF 8086

March 21, 2019

The programming model for a microprocessor shows the various internal registers that are accessible to the
programmer.

The Following Figure is a model for the 8086. In general, each register has a special function.

In the programming model there are

- 4 General Purpose registers( Data Registers)

- 4 Segment registers

- 2 Pointer registers

- 2 Index registers

- 1 Instruction Pointer register

- 1 Flag register

General purpose registers:

AX Register (Accumulator): This is accumulator register. It gets used in arithmetic, logic and data transfer
instructions. In manipulation and division, one of the numbers involved must be in AX or AL.

BX Register (Base Register): This is base register. BX register is an address register. It usually contain a data pointer
used for based, based indexed or register indirect addressing.

CX Register (Counter register): This is Count register. This serves as a loop counter. Program loop constructions are
facilitated by it. Count register can also be used as a counter in string manipulation and shift/rotate instruction.

DX Register (Data Register): This is data register. Data register can be used as a port number in I/O operations. It is
also used in multiplication and division.

Segement Registers:

There are four segment registers in Intel 8086:

1. Code Segment Register (CS),

2. Data Segment Register (DS),

3. Stack Segment Register (SS),

4. Extra Segment Register (ES).

A segment register points to the starting address of a memory segment. Maximum capacity of a segment may be
up to 64 KB.

Code segment Register(CS):- It is a 16-bit register containing the starting address of 64 KB segment. The processor
uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register.
Stack segment Register (SS):- It is a 16-bit register containing address of 64KB segment with program stack. By
default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is
located in the stack segment. SS register can be changed directly using POP instruction.

Data segment Register (DS):- It is a 16-bit register containing address of 64KB segment with program data. By
default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI,
DI) is located in the data segment.

Extra segment Register (ES):- It is a 16-bit register containing address of 64KB segment, usually with program data.
By default, the processor assumes that the DI register references the ES segment in string manipulation
instructions. It is possible to change default segments used by general and index registers by prefixing instructions
with a CS, SS,DS or ES prefix.

Pointer Registers:

SP Register (Stack Pointer): This is stack pointer register pointing to program stack. It is used in conjunction with SS
for accessing the stack segment.

BP Register (Base Pointer): This is base pointer register pointing to data in stack segment. Unlike SP, we can use BP
to access data in the other segments.

Index Registers:

SI Register (Source Index): This is used to point to memory locations in the data segment addressed by DS. By
incrementing the contents of SI one can easily access consecutive memory locations.

DI Register (Destination Index): This register performs the same function as SI. There is a class of instructions called
string operations, that use DI to access the memory locations addressed by ES.

Instruction Pointer: The Instruction Pointer (IP) points to the address of the next instruction to be executed. Its
content is automatically incremented when the execution of a program proceeds further. The contents of the IP
and Code Segment Register are used to compute the memory address of the instruction code to be fetched. This is
done during the Fetch Cycle.

Flag Register: Status Flags determines the current state of the accumulator. They are modified automatically by
CPU after mathematical operations. This allows to determine the type of the result. 8086 has 16-bit status register.
It is also called Flag Register or Program Status Word (PSW). There are nine status flags and seven bit positions
remain unused.

8086 has 16 flag registers among which 9 are active. The purpose of the FLAGS register is to indicate the status of
the processor. It does this by setting the individual bits called flags. There are two kinds of FLAGS;

Status FLAGS and Control FLAGS. Status FLAGS reflect the result of an operation executed by the processor. The
control FLAGS enable or disable certain operations of the processor.

Q.6 Write a short note on 8288 bus controller(D 2016) (M 2015) (D2016)

1. The minimum mode signals, INTA, ALE, DEN, DT/ IT, M/ 10 , WR , HLDA, and HOLD (on
pins 24 to 31) that are essential for interfacing memory and I/O devices, are not available
in the system if the 8086 is operated in maximum mode.
2. An 8288 bus controller is used to generate the relevant signals for interfacing memory and
I/O devices in the maximum mode.
3. Figure (a) gives the block diagram of 8288. The bus controller has a command signal
generator and a control signal generator.
4. Figure (b) illustrates the maximum mode configuration of 8086 and the use of 8288 in
8086 based system.
5. The 8288 input and output signals:

 SO, SL and S2: The inputs (8086 Status outputs) are decoded to generate command
signals.
 AEN: A low Address Enable signal activates the memory control signals.
 CEN: The Control Enable signal enables the 8288 command outputs.
 IOB: High on the I/O Bus input operates the 8288 in the I/O bus mode in systems where
there are separate system bus and I/O bus.
 CLK: The Clock input
 DEN: The Data bus Enable signal controls the data bus buffers in the system. This signal
is active-high in contrast to the DEN signal in the minimum mode.

 ALE: The Address Latch Enable signal is used to de-multiplex address and data lines
signals.
 DT/R: The Data Transmit/Receive signal controls bidirectional data bus buffer.
  MRDC, MWTC, IORC and lOWC: The 8288 generates the normal Memory Read, Memory
Write, I/O Read, I/O Write Control signals.
 AMWC, and AIOWC: These are Advanced Memory and Advanced I/O Write Control
signals.
 INTA: The Interrupt Acknowledge output.
 MCE/PDEN: The Master Cascade Enable/Peripheral Data Enable output serves dual
function. If IOB input is low it selects cascading of interrupt controllers, and if high enables
the I/0 bus transceivers.

Q.7 Explain protection mechanism used in 80386. (M 2016) (D 2016)

Q.8 Compare between i3 ,i5 and i7(M 2016) (D 2016)

Q.9 Explain Interfacing of three 8259 with 8086 in minimum mode.

1. Figure below shows that how an 8259 can be interfaced with the 8086 microprocessor
system in minimum mode. In case of 8088 microprocessor same interfacing diagram can
be used except M/I0 signal.
2. In 8088, M/IO signal is represented by 10/M signal, therefore this signal is connected to G
(active high) signal of decoder to interface 8259A in I/O mapped I/O mode.
 Interfacing of 8259 with 8086 in minimum mode

1. The 74LS138 address decoder will assert the CS input of the 8259 when an I/O base
address is FFF0H or FFF2H on the address bus.
2. The A_0 input of the 8259A is used to select one of the two internal addresses in the
device. Ao of the 8259A is connected to system line Al. So the system addresses for the
two internal addresses are FFF0H and FFF2H.
3. The data lines of an 8259 are connected to the lower half of the system data bus; because
the 8086 expects to receive interrupt types on these lower eight data lines.
4. RD and WR signals are connected to the system RD and WR lines.
5. The interrupt request signal INT from the 8259 is connected to the INTR input of the 8086
and INTA from the 8086 is connected to INTA on the 8259A. As we are using single 8259
in the system SP/EN pin is tied high and CAS0-CAS2 lines are left open.
6. The eight IR inputs are available for interrupt signals.
7. Cascading :
8. The 8259 can be easily interconnected to get multiple interrupts. Fig below shows how
8259 can be connected in the cascade mode. In cascade mode one 8259 is configured in
Master mode and other should be configured in the Slave mode. In this figure 8259 is in
 the master mode and others are in slave mode. Each slave 8259 is identified by the
number which is assigned as a part of its initialization. Since the 8086 has only one INTR
input, only one of the 8259 INT pins is connected to the 8086 INTR pin. The 8259
connected directly into the 8086 INTR pm is referred as the master. The INT pins from
other 8259 are connected to the IR inputs of the master 8259. These cascaded 8259s are
referred as slave. The INTA signal is connected to both master and slave 8259.
9. The cascade pins CAS0 to CAS2 are connected from the master to the corresponding
pins of the slave. For the master these pins function as outputs, and for the slave these
pins function as inputs. The SP/EN signal is tied high for the master. However it is
grounded for the slave.
10. Each 8259A has its own addresses so that command words can be written to it and status
bytes read from it.

1. Address for 8259s

 1. Master and slave operation : When the slave receives an interrupt signal on one of its IR
inputs, it checks mask condition and priority of the interrupt request. If the interrupt is
unmasked and its priority is higher than any other interrupt level being serviced in the
slave, then the slave will send an NT signal to the IR input of a master. If that IR input of
the master is unmasked and if that input is a higher priority than any other IR inputs
currently being serviced, then the master will send an INT signal to the 8086 INTR input. If
the INTR interrupt is enabled, the 8086 will go through its INTR interrupt procedure and
sends out two INTA pulses to both the master and the slave. The slave ignores the first
interrupt acknowledge pulse but the master outputs a 3-bit slave identification number on
the CAS0-CAS2 lines. Sending the 3-bit ID number enables the slave. When the slave
receives the second INTA pulse from the 8086, the slave will send the desired type
number to the 8086 on the eight data lines. If an interrupt signal is applied directly to one
of the IR inputs of the master, the master will send the desired interrupt type to the 8086
when it receives the second INTA pulse from the 8086.

Q.10 Design a 8086 based system with following specifications

i) CPU at 10MHz in minimum mode operation

ii) 32 KB SRAM using 8 KB devices

iii) 64 KB EPROM using 16 KB devices

iv) One 8255 PPI for keyboard interface Design system with absolute decoding. Clearly
show memory address map and I/O address map. Draw a neat schematic for chip
selection logic.

ANS:

Step 1: Total EPROM required = 64 KB

Chip size available = 16 KB
∴Number of chips required=64KB16KB=4∴Number of chips required=64KB16KB=4
∴Number of sets required=NumberofchipsNumberofbanks=42=2∴Number of sets
required=NumberofchipsNumberofbanks=42=2
SET 1: Ending address of SET 1 = FFFFFH
SET size = Chip size x 2 = 16 KB x 2 = 32 KB
i.e. 00000011171111F1111F1111F00000011171111F1111F1111F
Starting address = Ending address – SET size=FFFFFH–
07FFFH=F8000HStarting address = Ending address – SET size=FFFFFH–07FFFH=F8000H
SET 2: Ending address of SET 2 = F7FFFH (previous ending - 1)
SET size = Chip size x 2 = 16 KB x 2 = 32 KB
i.e. 00000011171111F1111F1111F00000011171111F1111F1111F
Starting address = Ending address – SET size=F7FFFH–
07FFFH=F0000HStarting address = Ending address – SET size=F7FFFH–07FFFH=F0000H

Step 2: Total RAM required = 32 KB

Chip size available = 8 KB
∴Number of chips required=32KB8KB=4∴Number of chips required=32KB8KB=4
∴Number of sets required=NumberofchipsNumberofbanks=42=2∴Number of sets
required=NumberofchipsNumberofbanks=42=2
SET 1: Starting address = 00000H
SET size = Chip size x 2 = 8 KB x 2 = 32 KB
i.e. 00000001131111F1111F1111F00000001131111F1111F1111F
Ending address = Starting address – SET
size=04000H+03FFFH=07FFFHEnding address = Starting address – SET
size=04000H+03FFFH=07FFFH
SET 2: Starting address = 04000H (previous ending - 1)
SET size = Chip size x 2 = 8 KB x 2 = 32 KB
i.e. 00000001131111F1111F1111F00000001131111F1111F1111F
Ending address = Starting address – SET size=04000H–
03FFFH=07FFFHEnding address = Starting address – SET size=04000H–03FFFH=07FFFH
Step 4: Final Implementation:

Q.11 Design 8086 microprocessor based system using minimum mode with following specifications: i)
8086 microprocessor working at 10 MHz. ii) 128 KB EPROM using 32 KB Chip iii) 64 KB SRAM using 16
KB Chip
Diagram shows 8086 in minimum mode configuration with a crystal of 30 MHz
Memory Calculations:
EPROM:
Required Memory = 128 KB,
Available Memory = 32 KB
Number of chip required = 4
Number of Address Lines = 15 lines (A15 – A1)
RAM:
Required Memory = 64 KB,
Available Memory = 16 KB
Number of chip required = 4
Number of Address Lines = 14 lines (A14 – A1)
Memory Map:
Q.12 Explain memory banks of 8086 Microprocessor (M 2018)

The 8086 has 20-bit address bus, so it can address 2^20 or 1,048,576 addresses. Each address
represents a stored byte. To make it possible to read or write a word with one bus cycle, the
memory for an 8086 is set up in to 2 banks of up to 524,288 bytes each. See figure.
8086 Memory Banks
One memory bank contains all the bytes which have even addresses such as 00000h, 00002h,
and 00004h etc. the data lines of this bank is connected to the lower 8 bit data lines i.e. from D0
to D7 of 8086.
The other memory bank contains all bytes which have odd addresses such as 00001h, 00003h
and 00005h etc. the data lines of this bank is connected to the upper 8 bit data lines i.e. from D8
to D15 of 8086.
Address line A0 is used for enabling the memory device in the lower bank. An addressed
memory device in this bank will be enabled when A0 is low, as it will be for any even address.
Like address 00222h = 0000 0000 0010 0010 0010. Address lines A1 to A19 are used to select
the desired memory device in the bank and hence the desired byte in the device.
Address line A1 to A19 are also used to select the desired memory device in the upper bank and
hence the desired byte. An additional part of enabling the upper bank memory device is handled
by the BHE i.e. the bus high enable signal. This is multiplexed out from the 8086 at the same
time as an address is sent out. An external latch, strobbeed by the ALE signal, grabs the BHE
signal and holds it stable for the rest of the machine cycle like it does for the address.
So now if we read a byte from or write a byte to an even address the A0 will be low BHE will be
high enabling the lower bank and disabling the upper bank.
The main reason that the A0 and BHE signal work as they do is to prevent the writing of an
unwanted signal.

The 8086 has 20-bit address bus, so it can address 2^20 or 1,048,576 addresses. Each address
represents a stored byte. To make it possible to read or write a word with one bus cycle, the
memory for an 8086 is set up in to 2 banks of up to 524,288 bytes each. See figure.
8086 Memory Banks
One memory bank contains all the bytes which have even addresses such as 00000h, 00002h,
and 00004h etc. the data lines of this bank is connected to the lower 8 bit data lines i.e. from D0
to D7 of 8086.
The other memory bank contains all bytes which have odd addresses such as 00001h, 00003h
and 00005h etc. the data lines of this bank is connected to the upper 8 bit data lines i.e. from D8
to D15 of 8086.
Address line A0 is used for enabling the memory device in the lower bank. An addressed
memory device in this bank will be enabled when A0 is low, as it will be for any even address.
Like address 00222h = 0000 0000 0010 0010 0010. Address lines A1 to A19 are used to select
the desired memory device in the bank and hence the desired byte in the device.
Address line A1 to A19 are also used to select the desired memory device in the upper bank and
hence the desired byte. An additional part of enabling the upper bank memory device is handled
by the BHE i.e. the bus high enable signal. This is multiplexed out from the 8086 at the same
time as an address is sent out. An external latch, strobbeed by the ALE signal, grabs the BHE
signal and holds it stable for the rest of the machine cycle like it does for the address.
So now if we read a byte from or write a byte to an even address the A0 will be low BHE will be
high enabling the lower bank and disabling the upper bank.
The main reason that the A0 and BHE signal work as they do is to prevent the writing of an
unwanted signal.

Q.13 Explain Flag register of 8086(M 2018)

The 8086 flag register contents indicate the results of computation in the ALU. It also contains
some flag bits to control the CPU operations.

1. A 16 bit flag register is used in 8086. It is divided into two parts . o Condition code or
status flags o Machine control flags
2. The condition code flag register is the lower byte of the 16-bit flag register. The condition
code flag register is identical to 8085 flag register, with an additional overflow flag.
3. The control flag register is the higher byte of the flag register. It contains three flags
namely direction flag (D), interrupt flag (I) and trap flag (T).

Figure below shows the details of the 16 bit flag register of 8086 CPU.
 1. It consists of 9 active flags out of 16. The remaining 7 flags marked ‘U’ are undefined
flags.
2. These 9 flags are of two types:

 6 Status flags
 3 Control flags

Status flags:

1. Carry flag (CY)-

 It is set whenever there is a carry or borrow out of the MSB (most significant bit) of a
result. D7 bit for an 8 bit operation and D15 bit for a 16 bit operation.

1. Parity flag (PF)-

2. It is set if the result has even parity. If parity is odd, PF is reset.
3. This flag is normally used for data transmission errors.
4. Auxiliary carry flag (AC)-
5. It is set if a carry is generated out of the lower nibble.
6. It is used only in 8 bit operations like DAA and DAS.
7. Zero flag (ZF)-
8. It is set if the result is zero.
9. Sign flag (SF)-
10. It is set if the MSB of the result is 1. For signed operations such a number is treated as
negative.
11. Overflow flag (OF)-
12. It will be set if the result of a signed operation is too large to fit in the number of bits
available to represent it.
 13. It can be checked using the instruction INTO (Interrupt on Overflow).

Control flags:

1. Trap flag (TF)-

2. It is used to set the trace mode i.e. start single stepping mode.
3. Here the microprocessor is interrupted after every instruction so that the program can be
debugged.
4. Interrupt enable flag (IF)-
5. It is used to mask (disable) or unmask (enable) the INTR interrupt.
6. If user sets IF flag, the CPU will recognize external interrupt requests. Clearing IF disables
these interrupts.
7. Direction flag (DF)-
8. If this flag is set, SI and DI are in auto-decrementing mode in string operations.

Q.14 Explain virtual mode (VM86) of 80386. (M 2018) (D2016) (M 2016)

1. In protected mode of operation, 80386DX provides a virtual 8086 operating environment to

execute the 8086 programs.
2. The real mode can also use to execute the 8086 programs along with the capabilities of
80386, like protection and a few additional instructions.
3. Once the 80386 enters the protected mode from the real mode, it cannot return back to
the real mode without a reset operation.
4. Thus, the virtual 8086 mode of operation of 80386, offers an advantage of executing 8086
programs while in protected mode.
5. V86 Mode is also known as Virtual Mode of 80386.
6. V86 Mode is a Dynamic Mode.
7. It can switch repeatedly & rapidly between V86 Mode & Protected Mode.
8. To execute an 8086 program, the CPU enters in V86 Mode from Protected Mode.
9. CPU Leaves V86 Mode and enters protected mode to continue executing a native 80386
program.
10. The address forming mechanism in virtual 8086 mode is exactly identical with that of 8086
real mode.
11. In virtual mode, 8086 can address 1MB of physical memory that may be anywhere in the
4GB address space of the protected mode of 80386.
12. Like 80386 real mode, the addresses in virtual 8086 mode lie within 1MB of memory.
13. In virtual mode, the paging mechanism and protection capabilities are available at the
service of the programmers.
14. The virtual mode allows the multiprogramming of 8086 applications.
15. The virtual 8086 mode executes all the programs at privilege level 3.

Q.15 Explain Interrupt structure of 8086. (M 2018)

1. An interrupt is a special condition that arises during the working of a microprocessor. The
microprocessor services it by executing a subroutine called Interrupt Service Routine
(ISR).
 2. There are three sources of interrupts for 8086:
3. Hardware interrupt-
These interrupts occur as signals on the external pins of the microprocessor. 8086 has two
pins to accept hardware interrupts, NMI and INTR.
4. Software interrupt-
These interrupts are caused by writing the software interrupt instruction INT n where ‘n’
can be any value from 0 to 255 (00H to FFH). Hence all 256 interrupts can be invoked by
software.
5. Error conditions (Exception or types)-
8086 is interrupted when some special conditions occur while executing certain
instructions in the program. Example: An error in division automatically causes the INT 0
interrupt.
Interrupt Vector Table (IVT):

1. The interrupt vector (or interrupt pointer) table is the link between an interrupt type code
and the procedure that has been designated to service interrupts associated with that
code. 8086 supports total 256 types i.e. 00H to FFH.
2. For each type it has to reserve four bytes i.e. double word. This double word pointer
contains the address of the procedure that is to service interrupts of that type.
3. The higher addressed word of the pointer contains the base address of the segment
containing the procedure. This base address of the segment is normally referred as NEW
CS.
4. The lower addressed word contains the procedure’s offset from the beginning of the
segment. This offset is normally referred as NEW IP.
 5. Thus NEW CS: NEW IP provides NEW physical address from where user ISR routine will
start.
6. As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are required; therefore
interrupt pointer table occupies up to the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of low
memory.
7. The total interrupt vector table is divided into three groups namely,
A. Dedicated interrupts (INT 0…..INT 4)
B. Reserved interrupts (INT 5…..INT 31)
C. Available interrupts (INT 32…..INT 225)
A. Dedicated interrupts (INT 0…..INT 4):
1. INT 0 (Divide Error)-
o This interrupt occurs whenever there is division error i.e. when the result of a
division is too large to be stored. This condition normally occurs when the divisor is
very small as compared to the dividend or the divisor is zero.
o Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
2. INT 1 (Single Step)-
o The microprocessor executes this interrupt after every instruction if the TF is set.
o It puts microprocessor in single stepping mode i.e. the microprocessor pauses after
executing every instruction. This is very useful during debugging.
o Its ISR generally displays contents of all registers. Its ISR address is stored at
location 1 x 4 = 00004H in the IVT.
3. INT 2 (Non mask-able Interrupt)-
o The microprocessor executes this ISR in response to an interrupt on the NMI (Non
mask-able Interrupt) line.
o Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
4. INT 3 (Breakpoint Interrupt)-
o This interrupt is used to cause breakpoints in the program. It is caused by writing
the instruction INT 03H or simply INT.
o It is useful in debugging large programs where single stepping is efficient.
o Its ISR is used to display the contents of all registers on the screen. Its ISR address
is stored at location 3 x 4 = 0000CH in the IVT.
5. INT 4 (Overflow Interrupt)-
o This interrupt occurs if the overflow flag is set and the microprocessor executes the
INTO (Interrupt on Overflow) instruction.
o It is used to detect overflow error in signed arithmetic operations.
o Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

B. Reserved interrupts (INT 5…..INT 31):

1. These levels are reserved by Intel to be used in higher processors like 80386, Pentium
etc. They are not available to the user.

C. Available interrupts (INT 32…..INT 225):

 1. These are user defined, software interrupts.
2. ISRs for these interrupts are written by the users to service various user defined
conditions.
3. These interrupts are invoked by writing the instruction INT n. Its ISR address is obtained
by the microprocessor from location n x 4 in the IVT.

Hardware Interrupts:
1. NMI (Non mask-able interrupt)-
o This is a non-mask-able, edge triggered, high priority interrupt.
o On receiving an interrupt on NMI line, the microprocessor executes INT
o Microprocessor obtains the ISR address from location 2 x 4 = 00008H from the IVT.
o It reads 4 locations starting from this address to get the values for IP and CS to
execute the ISR.
2. INTR-
o This is a mask-able, level triggered, low priority interrupt.
o On receiving an interrupt on INTR line, the microprocessor executes
2 INTA¯¯¯¯¯¯¯¯¯¯¯¯¯¯INTA¯ pulses.
o 1st INTA INTA¯ pulse – The interrupting device calculates (prepares to send) the
vector number.
2nd INTA INTA¯ pulse – The interrupting device sends the vector number ‘N’ to
the microprocessor.

o Now microprocessor multiplies N x 4 and goes to the corresponding location in the

IVT to obtain the ISR address. INTR is a mask-able interrupt.
o It is masked by making IF = 0 by software through CLI instruction.
o It is unmasked by making IF = 1 by software through STI instruction.

Q.16 Explain the need of DRAM controller for interfacing DRAM with 8086. Draw and explain interfacing DRAM with 8086.
(D2016)
Q.17 Draw and explain timing diagram of write operation for maximum mode. (M 2018)

Bus Timing Diagram of 8086:

The Bus Timing Diagram of 8086 of input and output transfers are shown in
the Fig. 10.10 (a) and (b) respectively.
These are explained in steps.
1. S0,S1,S2 are set at the beginning of bus cycle. On detecting the change on passive state S0 = S1 = S2 = 1, the 8288 bus
controller will output a pulse on its ALE and apply a required signal to its DT/R pin during T1.
2. In T2, 8288 will set DEN = 1 thus enabling transceiver. For an input, 8288 it will activates MRDC or IORC. These signals are
activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3
to T4.
3.The status bits S0 to S2 remain active until T3, and become passive during T3 and T4.
4.If ready input is not activated before T3, wait state will be inserted between T3 and T4.

Q.18 Explain operating modes of 8259 PIC. (M 2018) (M 2016)

Operating modes of 8259 PIC
Last Updated : 07 Jul, 2021
Prerequisites: 8259 PIC
8259 PIC is designed for the 8085 and 8086 microprocessor’s series.

Need For PIC in 8085 and 8086 :

In 8086 we have two pins for interrupt handling i.e. NMI and INTR. If we use NMI for data corruption or non-recoverable
hardware errors and one interrupt pin, INTR for other software interrupts.
In a system when we have multiple interrupts from different input or output devices, then we need a PIC(priority interrupt
controller) that can handle multiple interrupts from different devices and prioritize them according to system requirements, and
sends them to a single interrupt pin on the processor.
Characteristics of 8259 :

A single 8259 handles 8 interrupts, while a cascaded configuration of it in which 1 master and 8 slaves can handle up to 64
interrupts.
It can handle both edge-level triggering interrupts.
Its priority structure can be easily altered.
In 8259, interrupts can be masked individually.
The vector address of the interrupts is easily programmed.
It must be initialized by giving commands, to determine various properties like vector numbers, priority, masking, triggering etc.
Operating modes of 8259 :
The different modes of operation of 8259 can be programmed by altering the bits of ICW or OCW commands of 8259.

Fully nested mode :

It is the default mode of operation of 8259.

Here, IR0 has the highest priority and IR7 has the lowest priority. When any interrupt requests occurs then the highest priority
interrupt request is serviced first and its vector address is placed on data bus and its corresponding bit in ISR register is set until
the processor executes the EOI command before returning the interrupt service routine or AEOI(Automatic end of interrupt bit is
set) until the falling of the last INTA’.
When the ISR bit is set for an interrupt, then all the equal and lower priority interrupts are masked, but a higher level interrupt
request can occur and which will be acknowledged only if the microprocessor interrupt enables flag IF= 1.
It is suitable for a single 8259 configuration.
The priority mechanism can be easily programmed.
Special fully nested mode (SFNM) :
This mode is used by master 8259 in a cascaded mode. Its priority structure is fixed and is the same as fully nested mode (i.e.
IR0 has the highest priority and IR7 has the lowest priority).

In a special fully nested mode, the master will only serve higher priority interrupt from a slave, whose another interrupt is
currently in service.

Rotating priority modes :

There are two rotating priority modes –

1. Automatic rotation mode

It is used when various interrupt sources are of the same priority. In this mode, after a device is serviced, it gets the lowest
priority. All other priorities rotate according to it.
Example: If IR4 has just been serviced, it will get the lowest priority.
2. Specific Rotation Mode

Here, the programmer can alter priorities by programming the lowest priority and thus fixing all other priorities.
For example: If IR6 is programmed as the lowest priority, then IR7 will have the highest priority.
Special mask mode (SMM) :

In SMM, 8259 enables interrupts of all levels (lower or higher) except the one that is currently in service.
Because we are especially masking the request of the priority level of interrupt, which is the same as the current interrupt priority
level, therefore it is called special mask mode.
Poll mode :
Here the INT pin of 8259 is not used, so, 8259 cannot interrupt the µp. Instead, the µP will provide a poll command to 8259
using OCW3. In response, 8259 provides a poll word to the µP. The poll word indicates the highest priority interrupt which
needs service from µP. Thereafter, the µP services the interrupt.

Advantage :
The µP’s program is not interrupted. It can be used when ISR is common for many interrupts. It can be used to increase the
number of interrupts beyond 64(i.e. in case of a cascaded configuration).

Drawback :
If the polling interval is long, then the interrupts will be serviced after a long period. If the polling interval is short, then the time
may be wasted on unnecessary polls.

EOI – (End Of Interrupt) :

When the microprocessor acknowledges an interrupt request by sending the first INTA signal, the 8259 sets the corresponding
bit in the In Service Register (ISR). This starts the service of the interrupt.
When this bit in the ISR is cleared, then it is known as the end of interrupt (EOI).

EOI Modes:
1. Normal EOI Mode –
Here, an EOI command is compulsory. The EOI command is written by the programmer at the end of the ISR. It makes 8259 to
reset the bit from ISR. Further EOI command is of two types :

Non Specific EOI Command Here the programmer doesn’t specify the bit number to be reset in the ISR. 8259 itself resets the
highest priority bit from ISR.
Specific EOI Command: Here the programmer determines the bit number to be reset from ISR.
2. Automatic EOI mode (AEOI) –
In this mode, the EOI command is not required. Instead, 8259 will itself clear the corresponding bit from ISR at the end of the
2nd INTA pulse.

Edge and level-triggered mode :

If the LTIM bit of ICW1 =0 then the edge-triggered interrupt mode is set, otherwise the interrupts are level triggered.

Reading 8259 Status :

The status of the registers can be read by this mode. Here, the OCW3 is used to read IRR and ISR and OCW1 is used to read
IMR.

Buffered Mode :
8259 sends a buffer enabled signal on the SP’/ EN’ pin when data is placed on the data bus.

Q.19 Explain segment descriptors of 80386. (M 2018) (D2016)

1. In protected mode, memory management unit (MMU) uses the segment selector to access
a descriptor for the desired segment in a table of descriptors in memory.
2. Segment descriptor is a special structure which describes the segment. Exactly one
segment descriptor must be defined for each segment of the memory.
3. Descriptors are eight type quantities which contain attributes about a given region of linear
address space (i.e. a segment).
4. These attributes include the 32-bit base linear address of the segment, the 20-bit length
and granularity of the segment, the protection level, read, write or execute privileges, the
default size of the operands (16-bit or 32-bit), and the type of segment.
5. Fig. below shows the general format of a descriptor. As shown in Fig. segment descriptor
has following fields.
6. Base: It contains the 32-bit base address for a segment. Thus defines the location of the
segment within the 4 gigabyte linear address space. The 80386 concatenates the three
fragments of the base address to form a single 32-bit address.
7. Limit: It defines the size of the segment. The 80386 concatenates the two fragments of the
limit field to form a 20 bit value. The 80386 interprets this 20-bit value in two ways,
depending on the setting of the granularity bit (G) :
o If G bit 0: In units of one byte, to define a limit of up to 1 M byte (220)
 If G bit 1: In units of 4 kilobytes, to define a limit of up to 4 gigabytes.
8. Granularity Bit: It specifies the units with which the limit field is interpreted. When bit is 0,
the limit is interpreted in units of one byte; otherwise limit is interpreted in units of 4
Kbytes.
9. D (Default size): When this bit is cleared, operands contained within this segment are
assured to be 16 bits in size. When it is set, operands are assumed to be 32-bits.
BASE Base Address of the segment
LIMIT The length of the segment
P Present Bill: 1= Present 0= Not present
DPL Descriptor privilege Level 0 – 3
S Segment Descriptor : 0 = System Descriptor 1 = Code or Data Segment Descriptor
TYPE Type of segment
A Accessed Bit
G Granulaty Bit: 1= Segment length is page granular 0 = Segment length is byte granular
D Default Operation Size (recognized in code segment descriptors only) 1 =32-bit segment 0 =
16 – bit segment
0 Bit must be zero (0) for compatibility with future processors
AVL Available field for user or OS
Note:
In a maximum – size segment (i.e. a segment with G = 1 and segment limit 19……
0=FFFFFFH).
The lowest 12 bits of the segment base should be zero. (i.e. segment base 11…..000=000H)
General Segment Descriptor Format

 0 (Reserved by Intel): It neither can be defined nor can be used by user. This bit must be
zero for compatibility with future processors.
 AVL/U (User Bit) : This bit is completely undefined, and 80386 ignores it. This is available
field/bit for user or operating system. Access Rights Byte:
 P (Present Bit): The present P bit is 1 if the segment is loaded in the physical memory, if P
= 0 then any attempt to access this segment causes a not present exception (exception
11).
 DPL (Descriptor Privilege Level): It is a 2-bit field defines the level of privilege associated
with the memory space that the descriptor defines- DPL0 is the most privileged whereas
DPL3 is the least privileged.
 S (System Bit): The segment S bit in the segment descriptor determines if a given
segment is a system segment or a code or a data segment. If the S bit is I then the
segment is either a code or data segment, if it is 0 then the segment is system segment.
 Type: This specifies the specific descriptors among various kinds of descriptors. (Detail
explanation is given in the following sections).
 A (Accessed Bit): The 80386 automatically sets this bit when a selector for the descriptor
is loaded into a segment register. This means that 80386 sets accessed bit whenever a
memory reference is made by accessing the segment.

Q.20 Explain data cache memory architecture and organization of Pentium Processor. (M 2018) (D 2017) (D2016) (M 2016)
(M 2016)
Pentium Processor Overview

The Pentium processor is the successor to the Intel486 processor. Originally released with a 66MHz clock speed, it
is a 16-bit based superscalar processor capable of executing two instructions in parallel during a single clock. It uses
a CISC (Complex Instruction Set Computer) type instruction set, and uses the little-endian type format to store
bytes in memory. A 64-bit external bus, separate data and instruction caches, write buffers, and a pipelined
floating-point unit combine to sustain a high executing rate. Caching along with pipeline and instruction flow are
discussed below in detail.

3. Cache Structure

This section will discuss in-depth the cache of the original Pentium processor. Topics include cache organization,
operation modes, and methods to ensuring cache consistency.

The Pentium processor has only one level of cache, referred to as Level 1 (L1). The L1 cache is located on-chip and is
divided into separate pieces; one for data and one for code, each at 8KB. This division is done to maximize both
flexibility and performance by allowing both code and data caches to readily cross page boundaries without having
to overwrite one another.

3.1 Cache Organization

L1 cache on the Pentium processor is 2-way set-associative in structure. In a set-associative structure the cache is
divided into equal sections called cache ways. The cache page size is equal to the size of the cache way and each
cache way is treated like a small direct mapped cache. In a 2-way scheme, two lines of memory may be stored at
any time.

The Pentium processor’s cache line size is 32 bytes and is filled by a burst of four reads on the processor’s 64-bit
data bus. Each cache way contains 128 cache lines and the cache page size is 4K, or 128 lines.

3.2 Cache Operation Modes

The data cache is configurable as a write-back or write-through on a line-by-line basis. The configuration of these
two operation modes is initiated by either hardware or software with either the NW (Not Write-Through) bit set to
0 for the write-through mode or the NW bit set to 1 for the write-back mode. When the cache is configured as
write-back, the cache acts like a buffer by receiving data from the processor and writing data back to main memory
whenever the system bus is available. The advantage to the write-back process is that the processor is freed up to
continue with other tasks while main memory is updated at a later time. However the disadvantage to this
approach is that by having cache handle writes back to memory, the cost and complexity of cache subsequently
increase. The second alternative is to configure the Pentium cache as write-through. In a write-through cache
scheme the processor handles writes to main memory instead of the cache. The cache may update its contents as
the data comes through from the processor however the write operation does not end until the processor has
written the data back to main memory. The advantage to this approach is that the cache does not have to be as
complex, which thus makes it less expensive to implement. The disadvantage of course is that the processor must
wait until the main memory accepts the data before moving on to its next task.

Along with the NW (Not Write-Through) bit mentioned above, the other bit that allows for the control of the cache
is the CD (Cache Disable) bit. As the name suggests, this bit allows for the hardware or the software to disable the
cache. When the CD bit is set to 1 the cache is disabled and enabled when it is set to 0.

3.3 Cache Consistency

Cache consistency on the Pentium processor is maintained using the MESI protocol. The protocol is used to decide
if a cache entry should be updated or invalidated. Furthermore, consistency is ensured by using two additional
functions known as inquire cycles and cache flushing. Each technique is described in detail below.

3.3.1 Cache Consistency Protocol (MESI Protocol)

The data cache supports the Cache Consistency Protocol, which is a set of rules by which states are assigned to
cached entries or lines. The protocol consists of four states that define whether a line is valid (HIT or MISS), if it is
available in other caches, and if it has been modified. The four states, which make up what is referred to as the
MESI protocol, are the M (Modified), E (Exclusive), S (Shared) and the I (Invalid) states. The following is a
description of each state:

An M-state line is modified meaning that it is different from main memory. An M-state line can also be
accessed (read/written to) without sending a cycle out on the bus.
 An E-state line is not modified. An E-state line can also be accessed (read/written to) without generating a
bus cycle, with a write causing the line to become modified.

An S-state indicates that the line is potentially shared with other caches meaning that the same line may
exist in more than one cache. Reading from this line does not generate bus activity however a write will
generate a write-through cycle on the bus and may also invalidate this line in other caches. A write to an S-
state line updates the cache.

An I-state indicates that the line is not available in cache. Reading from this line may cause a MISS and
cause the processor to execute a LINE FILL where the whole line is fetched from main memory and placed
back into cache. Writing to an INVALID line causes the processor to execute a write-through cycle on the
bus.

The other piece of L1 cache, the code side, supports a subset of the MESI protocol, the S (Shared) and I (Invalid)
states in order to prevent code from accidentally being corrupted since it is inherently write protected.

3.3.2 Inquire Cycles

Inquire cycles are initiated by the system to determine if a particular line is present in the code or data caches and
what state the line is in. Inquire cycles are driven to the processor when the bus master initiates a read to
determine if the data cache contains the most recent information. If the line is in the data cache in the modified
state, then the cache has the most recent information and must schedule a write-back of the data. Inquire cycles
are also driven to the processor when the bus master initiates a write to determine if the processor’s code or data
caches contain the line and to invalidate the line if it is present.

3.3.3 Cache Flushing

Cache flushing is the mechanism by which the Pentium processor clears its cache. A cache flush may be initiated by
either external hardware or software instructions. During a cache flush, the data cache writes back all of its
modified or dirty lines. State bits in both data and code caches are then marked causing lines to become invalid or
unavailable. After all write backs have been completed, the processor generates a special bus cycle known as the
Flush Acknowledge Cycle.

Q.21 Draw and explain floating point pipeline for Pentium processor. (M 2018)
• The floating point pipeline has 8 stages as follows:
1. Prefetch(PF) :
 – Instructions are prefetched from the on-chip instruction cache
2. Instruction Decode(D1):
– Two parallel decoders attempt to decode and issue the next two sequential instructions
– It checks whether the instructions can be paired
– It decodes the instruction to generate a control word
– A single control word causes direct execution of an instruction
– Complex instructions require microcoded control sequencing
3. Address Generate (D2):
– Decodes the control word
– Address of memory resident operands are calculated
4.Memory and Register Read (Execution Stage) (EX):
– Register read or memory read performed as required by the instruction to access an operand.
5 . Floating Point Execution Stage 1(X1):
1. Information from register or memory is written into FP register.
2. Data is converted to floating point format before being loaded into the floating point unit
6.Floating Point Execution Stage 2(X2):
3. Floating point operation performed within floating point unit.
7.Write FP Result (WF):
o Floating point results are rounded and the result is written to the target floating point register.
8. Error Reporting(ER)
1. If an error is detected, an error reporting stage is entered where the error is reported and FPU status
word is updated

Instruction Issue for Floating Point Unit:

• The rules of how floating-point (FP) instructions get issued on the Pentium processor are :
1. FP instructions do not get paired with integer instructions.
2. When a pair of FP instructions is issued to the FPU, only the FXCH instruction can be the second instruction of
the pair.
The first instruction of the pair must be one of a set F where F = [ FLD,FADD, FSUB, FMUL, FDIV,
FCOM, FUCOM, FTST, FABS, FCHS].
1. FP instructions other than FXCH and instructions belonging to set F, always get issued singly to the FPU.
2. FP instructions that are not directly followed by an FXCH instruction are issued singly to the FPU.

Q.22 Explain integer pipeline of Pentium processor(M 2017) (M 2016)

Pentium uses a 5 stage pipeline with the following stages in the pipeline.
 1. Prefetch stage - Pentium instructions are variable length and are stored in a prefetch
buffer. There is a 256 bit path from instruction cache to the prefetch buffer.
2. Decode 1 stage - In this stage the processor decodes the instruction and finds the opcode
and addressing information, check which instructions can be paired for simultaneous
execution and participates in branch address prediction.
3. Decode 2 stage - Addresses for memory reference are found in this stage.

1. Execute stage - In this stage, data cache fetch or ALU or FPU operation may be carried
out. Observe that two operations can be carried out.
2. Write back stage - Registers and flags are updated based on results of execution.

Q.23 Explain string instructions of 8086(M 2017)

The String Instruction in 8086 are namely,

 REP/REPE/REPZ/REPNE/REPNZ
 MOVS/MOVSB/MOVSN
 CMPS/CMPSB/CMPSW
  SCAS/SCASB/SCASW
 LODS/LODSB/LODSW
 STOS/STOSB/STOSW
REP/REPE/REPZ/REPNE/REPNZ Instruction :

REP is a prefix which is written before one of the String Instruction in 8086. These instructions repeat until
specified condition exists.

MOVS/MOVSB/MOVSW Instruction :

This instruction copies a byte or word from a location in the data segment to a location in the extra
segment. The offset of the source byte or word in the data segment must be in the SI register. The offset of
the destination in the extra segment must be contained in the DI register. For multiple byte or multiple
word moves the number of elements to be moved is put in the CX register so that it can function as a
counter. After the byte or word is moved SI and DI are automatically adjusted to point to the next source
and the next destination. If the direction flag is 0, then SI and DI will be incremented by 1 after a byte
move and they will incremented by 2 after a word move. If the DF is a 1, then SI and DI will be
decremented by 1 after a byte move and they will be decremented by 2 after a word move. MOVS affects
no flags.

The way to tell the assembler whether to code the instruction for a byte or word move is to add a “B” or a
“W” to the MOVS mnemonic. MOVSB, for example, says move a string as bytes. MOVSW says move a
string as words.
After move SI will be one greater than offset of last byte in source string. DI will be one greater than offset
of last byte of destination string. CX will be 0.

CMPS/CMPSB/CMPSW Instruction :

A String Instruction in 8086 is a series of the same type of data items in sequential memory locations. The
CMPS instruction can be used to compare a byte in one string with a byte in another string or to compare a
word in one string with a word in another string. SI is used to hold the offset of a byte or word in the source
string and DI is used to hold the offset of a byte or a word in the other string. The comparison is done by
subtracting the byte or word pointed to by DI from the byte or word pointed to by SI. The AF, CF, OF, PF,
SF, and ZF flags are affected by the comparison, but neither operand is affected.

After the comparison SI and DI will be automatically incremented or decremented according to direction
flag to point to the next element in the two strings (if DF = 0, SI and DI ↑ ) CX functions as a counter
which is decremented after each comparison. This will go on until CX = 0

SCAS/SCASB/SCASW Instruction :

SCAS compares a string byte with a byte in AL or a string word with word in AX. The instruction affects
the flags, but it does not change either the operand in AL (AX) or the operand in the String Instruction in
8086. The string to be ‘scanned must be in the extra segment and DI must contain the offset of the byte or
the word to be compared.

After the comparison DI will be automatically incremented or decremented according to direction flag, to
point to the next element in the two strings (if DF = 0, SI and DI ↑ ) CX functions as a counter which is
decremented after each comparison. This will go on until CX = 0. SCAS affects the AF, CF, OF, PF, SF
and ZF flags.
SCASB says compare String Instruction in 8086 as bytes and SCASW says compare strings as words.

LODS/LODSB/LODSW Instruction :

This instruction copies a byte from a string location pointed to by SI to AL, or a word from a string
location pointed to by SI to AX. LODS does not affect any flags. LODSB copies byte and LODSW copies
a word.

STOS/STOSB/STOSW Instruction :

The STOS instruction copies a byte from AL or a word from AX to a memory location in the extra
segment. DI is used to hold the offset of the memory location in the extra segment. After the copy, DI is
automatically incremented or decremented to point to the next string element in memory. If the direction
flag, DF, is cleared, then DI will automatically be incremented by one for a byte string or incremented by
two for a word String Instruction in 8086. If the direction flag is set, DI will be automatically decremented
by ono for a byte string or decremented by two for a word string. STOS does not affect any flags. STOSB
copies byte and STOSW copies a word.
Q.24 Explain Data transfer modes of DMA controller(M 2017) (M 2016) (D 2016)

DMA controller has four modes for data transfer:

1. Single Byte Transfer Mode/ Cycle Stealing

 Once the DMAC becomes the bus master, it will transfer only ONE BYTE and return the
bus back to the microprocessor. As soon as the microprocessor performs one bus cycle,
DMAC will once again take the bus back from the microprocessor.
 Both DMAC and microprocessor are constantly stealing bus cycles from each other. It is
the most popular method of DMA, because it keeps the microprocessor active in the
background.
 After a byte is transferred, the CAR and CWCR are adjusted accordingly. The system bus
is returned to the µP. For further bytes to be transferred, the DREQ line must go active
again, and then the entire operation is repeated.

2. Block Transfer Mode.

 In this mode, the DMAC is programmed to transfer all the bytes in one complete DMA
operation. After a byte is transferred, the CAR and CWCR are adjusted accordingly.
 The system bus is returned to the µP, only after all the bytes are transferred. i.e. TC is
reached or EOP signal is issued. It is the fastest form of DMA but keeps the
microprocessor inactive for a long time.
 The DREQ signal needs to be active only in the beginning for requesting the DMA service
initially. Thereafter DREQ can become low during the transfer.
3. Demand Transfer Mode
 It is very similar to Block Transfer, except that the DREQ must active throughout the DMA
operation.
 If during the operation DREQ goes low, the DMA operation is stopped and the busses are
returned to the µP.
  In the meantime, the µP can continue with its own operations. Once DREQ goes high
again, the DMA operation continues from where it had stopped.
4. Cascade Transfer Mode
 In this mode, more than one DMACs are cascaded together. It is used to increase the
number of devices interfaced to the µP. Here we have one Master DMAC, to which one or
more Slave DMACs are connected.
 The Slave gives HRQ to the Master on the DREQ of the Master, and the Master gives
HRQ to the µP on the HOLD of the µP.

Q.25 Explain with neat diagram address translation mechanism implemented on 80386. (M 2017) (D 2017)

1. Figure below shows the protected mode addressing mechanism.

1. The selector is used to specify an index into a table defined by the operating system. The
table includes the 32-bit base address of a given segment. The physical address is
obtained by summing the base address obtained from the table with the offset.
2. With the paging mechanism enabled, the 80386 provides an additional memory
management mechanism. The paging feature manages large 80386 segments. The
paging mechanism translates the protected linear addresses from the segmentation unit
into physical addresses. Figure below shows this translation scheme.
3. Segmentation provides both memory management and protection. All information about
the segments is stored in an 8-byte data structure called a descriptor. All the descriptors
are stored in tables identified by the 80386 hardware. There are three types of tables
holding 80386 descriptors: global descriptor table (GDT), local descriptor table (LDT), and
interrupt descriptor table (I DT).
  The GDT contains descriptors which are available to all the tasks in the system. In
general, the GDT contains code and data segments used by the operating system, task
state segments, and descriptors for LDTs in a system.
 LDTs store descriptors for a given task. Each task has a separate LDT, while the GDT
contains descriptors for segments which are common to all tasks.
 The IDT contains the descriptors which point to the location of up to 256 interrupt service
routines. Every interrupt used by a system must have an entry into the IDT. The IDT
entries are referenced via INT instructions, external interrupt vectors, and exceptions.

The 80386 provides four protection levels for supporting a multitasking operating system to
isolate and protect user programs from each other and the operating system.
The privilege level controls the use of privileged instructions, I/O instructions, and access to
segments and segment descriptors. The 80386 includes the protection as part of its memory
management unit. The four-level hierarchical privilege system is shown in Figure below.
 1. It is an extension of the user/ supervisor privilege mode used by minicomputers. Note that
the user/supervisor mode is supported by the 80386 paging mechanism. The Privilege
Levels (PL) is numbered 0 to 3. Level 0 is the most privileged level.
2. procedures between levels of a task:
o Data stored in a segment with a privilege level x can be accessed only by code
executing at a privilege level at least as privileged as x.
o A code segment/procedure with privilege level x can only be called by a task
executing at the same or a higher privilege level than x.
3. The 80386 supports task gates (protected indirect calls) to provide a secure method of
privilege transfers within a task. The 80386 also supports a rapid task switch operation via
hardware.
4. Paging is another type of memory management for virtual memory multitasking operating
systems. The main difference between paging and segmentation is that paging divides
programs/data into several equal-sized pages, while segmentation divides programs/data
into several variable-sized segments.
5. There are three elements associated with the 80386 paging mechanism. These are page
directory, page tables, and the page itself (page frame). The paging mechanism does not
have memory fragmentation since all pages have the same size of 4K bytes.
6. The 80386 takes care of the page address translation process, relieving the burden from
an operating system in a demand-paged system. The operating system is responsible for
setting up the initial page tables and the handling of any page faults.
7. The operating system initializes the tables by loading CR3 with the address of the page
directory and allocates space for the page directory and the page tables. The operating
system also implements a swapping policy and handles all of the page faults.

Q.26 Draw and explain block diagram of Pentium processor. (M 2017) (M 2016)

The Pentium family of processors originated from the 80486 microprocessor. The term ''Pentium
processor'' refers to a family of microprocessors that share a common architecture and
instruction set. It runs at a clock frequency of either 60 or 66 MHz and has 3.1 million transistors.
Some of the features of Pentium architecture are:
  Complex Instruction Set Computer (CISC) architecture with Reduced Instruction Set
Computer (RISC) performance.
 64-Bit Bus
 Upward code compatibility.
 Pentium processor uses Superscalar architecture and hence can issue multiple
instructions per cycle.
 Multiple Instruction Issue (MII) capability.
 Pentium processor executes instructions in five stages. This staging, or pipelining, allows
the processor to overlap multiple instructions so that it takes less time to execute two
instructions in a row.
 The Pentium processor fetches the branch target instruction before it executes the branch
instruction.
 The Pentium processor has two separate 8-kilobyte (KB) caches on chip, one for
instructions and one for data. It allows the Pentium processor to fetch data and
instructions from the cache simultaneously.
 When data is modified, only the data in the cache is changed. Memory data is changed
only when the Pentium processor replaces the modified data in the cache with a different
set of data
 The Pentium processor has been optimized to run critical instructions in fewer clock cycles
than the 80486 processor.

The Pentium processor has two primary operating modes -

1. Protected Mode - In this mode all instructions and architectural features are available,
providing the highest performance and capability. This is the recommended mode that all
new applications and operating systems should target.
2. Real-Address Mode - This mode provides the programming environment of the Intel 8086
processor, with a few extensions. Reset initialization places the processor in real mode
where, with a single instruction, it can switch to protected mode.

The Pentium's basic integer pipeline is five stages long, with the stages broken down as follows:
 1. Pre-fetch/Fetch: Instructions are fetched from the instruction cache and aligned in pre-
fetch buffers for decoding.
2. Decode1: Instructions are decoded into the Pentium's internal instruction format. Branch
prediction also takes place at this stage.
3. Decode2: Same as above, and microcode ROM kicks in here, if necessary. Also, address
computations take place at this stage.
4. Execute: The integer hardware executes the instruction.
5. Write-back: The results of the computation are written back to the register file.

Floating Point Unit:

There are 8 general-purpose 80-bit Floating point registers. Floating point unit has 8 stages of
pipelining. First five are similar to integer unit. Since the possibility of error is more in Floating
Point unit (FPU) than in integer unit, additional error checking stage is there in FPU. The floating
point unit is shown as below
Where, FRD - Floating Point Rounding
FDD - Floating Point Division
FADD - Floating Point Addition
FEXP - Floating Point Exponent
FAND - Floating Point And
FMUL - Floating Point Multiply

Q.27 Explain control registers of 80386. (M 2017) (D2016) (M 2016)

4.1.3 Control Registers

Figure shows the format of the 80386 control registers CR0, CR2, and CR3. These registers are
accessible to systems programmers only via variants of the MOV instruction, which allow
them to be loaded from or stored in general registers; for example:
MOV EAX, CR0
MOV CR3, EBX
CR0 contains system control flags, which control or indicate conditions that apply to the
system as a whole, not to an individual task.

EM (Emulation, bit 2)

EM indicates whether coprocessor functions are to be emulated.

ET (Extension Type, bit 4)

ET indicates the type of coprocessor present in the system (80287 or 80387 ) .

MP (Math Present, bit 1)

 MP controls the function of the WAIT instruction, which is used to coordinate a
coprocessor .

PE (Protection Enable, bit 0)

Setting PE causes the processor to begin executing in protected mode. Resetting PE

returns to real-address mode .

PG (Paging, bit 31)

PG indicates whether the processor uses page tables to translate linear addresses into
physical addresses .

TS (Task Switched, bit 3)

The processor sets TS with every task switch and tests TS when interpreting
coprocessor instructions .

CR2 is used for handling page faults when PG is set. The processor stores in CR2 the linear
address that triggers the fault .

CR3 is used when PG is set. CR3 enables the processor to locate the page table directory for
the current task .

Q.28 Write instruction issue algorithm used in Pentium processor(D 2017) (M 2016)

The Pentium has superscalar organizations. It enables 2-instructions to be executed in parallel.

Figure below (a) shows that the resources for address generation and ALU functions have been
replicated in independent integer pipeline, called U- and V-.
The ????P in the PF and D1 stages can fetch and decode 2-simple instructions in parallel and
issue them to the U- and V-pipelines. Additionally, the ????P for complex instructions in D1 can
generate micro coded sequences that control both U- and V-pipelines. Several techniques are
used to resolve dependencies between instructions that might be executed in parallel. Most of
the logic is contained in the instruction issue algorithm as indicated in Figure (b) of D1.

Resource Dependency
When 2-instructions require a single functional unit or data path, a resource dependency occurs.
The ????P during the D1 stage issues 2-instructions for parallel execution if both belong to the
class of simple instructions, thereby eliminating most resource dependencies. The instructions
must be directly executed that does not require micro-coded sequencing. The instruction being
issued to the V-pipe can be an ALU operation, memory referencing or a jump. The instruction
being issued to the U-pipe can be from the same categories or from an additional set that uses a
functional unit available only in the U-pipe, such as the barrel shifter. Although, the set of
instructions identified as 'simple' might seem restrictive, more than 90% of the instructions
executed in the integer SPEC benchmark suite are simple.
Data dependencies
When one instruction writes a result that is read or written by another instruction, a data
dependency occurs. Logic in D1 ensures that the source and the destination registers of the
instruction issued to the V-pipe differ from the destination register of instruction issued to the U-
pipe. This arrangement eliminates read-after-write (RAW) and write-after-write (WAW)
dependencies. Write-after-read (WAR) dependencies need not be checked because reads occur
in an earlier stage of the pipelines than writes. The design includes logic that enables instruction
with certain special types of data dependency to be executed in parallel. For example, a
conditional branch instruction that tests the flag results can be executed in parallel with a
compare instruction that sets the flags.
 Control dependencies
When the result of one instruction determines whether another instruction will be executed, a
control dependency occurs. The ????P in D1 never issues an instruction to the V-pipe when a
jump instruction is issued to the U-pipe, thereby eliminating control dependencies.

Q.29 Explain power on reset circuit used in 8086 system. (D 2017) (D 2016)
Q.30 Explain maximum mode of 8086 processor. (D 2017)

Maximum mode configuration of 8086 microprocessor (Max mode)

 Difficulty Level : Medium
 Last Updated : 29 Dec, 2021
8086 microprocessor characteristics:
 It contains 20 bit address bus.
 It contains 16-bit data bus, therefore 8086 is called as 16-bit microprocessor.
 It is 2-stage pipelined processor. It can prefetch 6 bytes from memory and store into
queue to increase the speed of the execution.
 It’s control bus carries signals for executing operations such as read ,write etc.
 It has Memory Banks. 2 banks of 512KB each. These banks are called as lower Bank
(even) and higher Bank (odd).
 In 8086 the entire memory is divided into four memory segments which are
code ,stack, data and extra segment.
 8086 has 16 bit IO address.
 It has 256 interrupts.
8086 has two operating Modes:
1. Minimum mode
2. Maximum mode
Minimum mode:
 In this 8086 is the only processor in the system . In a minimum mode 8086 system.
 8086 is operated in minimum mode when MN/MX’ pin to logic 1.
 In this mode, all the control signals are given out by the 8086 itself.
Maximum mode:
 In this we can connect more processors to 8086 (8087/8089).
 8086 max mode is basically for implementation of allocation of global resources and
passing bus control to other coprocessor(i.e. second processor in the system),
because two processors can not access system bus at same instant.
 All processors execute their own program.
 The resources which are common to all processors are known as global resources.
 The resources which are allocated to a particular processor are known as local or
private resources.
 Maximum mode circuit

Circuit explanation:
 When MN/ MX’ = 0 , 8086 works in max mode.
 Clock is provided by 8284 clock generator.
 8288 bus controller- Address form the address bus is latched into 8282 8-bit latch.
Three such latches are required because address bus is 20 bit. The ALE(Address
latch enable) is connected to STB(Strobe) of the latch. The ALE for latch is given
by 8288 bus controller.
 The data bus is operated through 8286 8-bit transceiver. Two such transceivers are
required, because data bus is 16-bit. The transceivers are enabled the DEN signal,
while the direction of data is controlled by the DT/R signal. DEN is connected
to OE’ and DT/ R’ is connected to T. Both DEN and DT/ R’ are given by 8288 bus
controller.

 Control signals for all operations are generated by decoding S’ 2, S’1 and
S’0 using 8288 bus controller.

 Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ 0/GT0 has more
priority than RQ1/GT1.
 INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.
 In max mode, the advanced write signals get enabled one T-state in advance as
compared to normal write signals. This gives slower devices more time to get ready
to accept the data, therefore it reduces the number of cycles.
Advantages of max mode of 8086:
 It helps to interface more devices like 8087.This interface is also called a closely
coupled co-Processor configuration. In this 8086 is called as the host and 8087 as
Co-processor.
 It supports multiprocessing, Therefore it helps to increase the efficiency.
 The 8087 was the first floating-point coprocessor for the 8086 series of
microprocessors. The purpose of the 8087 was to increase calculations for floating
point operations, such as add, sub, multiply, divide, and square root.
Disadvantages of max mode over min mode :
 It has more complex circuit than min mode.

Q.31 Discuss control word format for BSR mode of 8255 PPI. (D 2017)

The BSR mode stands for "Bit Set Reset Mode". The first bit, i.e. the Most
Significant Bit (MSB) of the Control word decides the mode in which the 8255 IC will
be. For the IC to be in the BSR mode, the MSB must be reset, i.e. it must be 0. The
BSR mode works only for port C. In this mode, we can select any bit of the port C and
then assign it any value: either 0 or 1. The following diagram illustrates the control
word layout for the BSR mode:

The control word in the BSR mode is as follows,

 Here, you can see that the D7 bit is reset which indicates the BSR mode.
 The next three bits, i.e. D6, D5, and D4 are the don’t care cases which means
that no matter what value they contain, either 0 or 1, the processor does not
consider them for any kind of operations.
  The Next three bits: D3, D2, and D1 decide which bit of the port C must be
selected. This is done in the following manner:

 The last bit of the control word, bit D0 is responsible for the selected bit to be
set or reset. The processor sets the selected bit of the port C to either 0 or 1
according to the value of D0.

Q.32 Explain EFLAG register format of 80386 processor. (D 2017) (D2016)

Flag Register of 80386 micro processor

Flag Register of 80386

 [ source: Intel386 DX Manual]

Note in these descriptions, ``set'' means ``set to 1,'' and ``reset''

means ``reset to 0.''

VM (Virtual 8086 Mode, bit 17)

The VM bit provides Virtual 8086 Mode within Protected Mode. If set while the 80386 is in Protected Mode, the
80386 will switch to Virtual 8086 operation, handling segment loads as the 8086 does, but generating exception 13
faults on privileged opcodes.

RF (Resume Flag, bit 16)

The RF flag is used in conjunction with the debug register breakpoints. It is checked at instruction boundaries before
breakpoint processing. When RF is set, it causes any debug fault to be ignored on the next instruction. RF is then
automatically reset at the successful completion of every instruction.

NT (Nested Task, bit 14)

This flag applies to Protected Mode. NT is set to indicate that the execution of this task is nested within another task.
If set, it indicates that the current nested task's Task State Segment (TSS) has a valid back link to the previous task's
TSS. This bit is set or reset by control transfers to other tasks.

IOPL (Input/Output Privilege Level, bits 12-13)

This two-bit field applies to Protected Mode. IOPL indicates the numerically maximum CPL (current privilege level)
value permitted to execute I/O instructions without generating an exception 13 fault or consulting the I/O Permission
Bitmap. It also indicates the maximum CPL value allowing alteration of the IF (INTR Enable Flag) bit when new
values are popped into the EFLAG register.

OF (Overflow Flag, bit 11)

OF is set if the operation resulted in a signed overflow. Signed overflow occurs when the operation resulted in
carry/borrow into the sign bit (high-order bit) of the result but did not result in a carry/borrow out of the high order bit,
or vice-versa. For 8/16/32 bit operations, OF is set according to overflow at bit 7/15/31, respectively.

DF (Direction Flag, bit 10)

DF defines whether ESI and/or EDI registers post decrement or post increment during the string instructions. Post
increment occurs if DF is reset. Post decrement occurs if DF is set.

IF (INTR Enable Flag, bit 9)

The IF flag, when set, allows recognition of external interrupts signaled on the INTR pin.

When IF is reset, external interrupts signaled on the INTR are not recognized. IOPL indicates the maximum CPL
value allowing alteration of the IF bit when new values are popped into EFLAGS or FLAGS.

TF (Trap Enable Flag, bit 8)

TF controls the generation of exception 1trap when single-stepping through code. When TF is set, the 80386
generates an exception 1 trap after the next instruction is executed. When TF is reset, exception 1 traps occur only
as a function of the breakpoint addresses loaded into debug registers DR0±DR3.

SF (Sign Flag, bit 7)

SF is set if the high-order bit of the result is set, it is reset otherwise. For 8-, 16-, 32-bit operations, SF reflects the
state of bit 7, 15, 31 respectively.

ZF (Zero Flag, bit 6)

ZF is set if all bits of the result are 0. Otherwise it is reset.

AF (Auxiliary Carry Flag, bit 4)

The Auxiliary Flag is used to simplify the addition and subtraction of packed BCD quantities. AF is set if the operation
resulted in a carry out of bit 3 (addition) or a borrow into bit 3 (subtraction). Otherwise AF is reset. AF is affected by
carry out of, or borrow into bit 3 only, regardless of overall operand length: 8, 16 or 32 bits.

PF (Parity Flags, bit 2)

PF is set if the low-order eight bits of the operation contains an even number of ``1's'' (even parity). PF is reset if the
low-order eight bits have odd parity. PF is a function of only the low-order eight bits, regardless of operand size.

CF (Carry Flag, bit 0)

CF is set if the operation resulted in a carry out of (addition), or a borrow into (subtraction) the high-order bit.
Otherwise CF is reset. For 8-, 16- or 32-bit operations, CF is set according to carry/borrow at bit 7, 15 or 31,
respectively.

Q.33 Draw and explain timing diagram of read operation for minimum mode. (D 2017) (M 2016) (M 2015)
The timing diagram for read operation in minimum mode is shown in fig below:

These are explained in steps.

1. When processor is ready to initiate the bus cycle, it applies a pulse to ALE during T1.
Before the falling edge of ALE, the address, BHE, M/IO, DEN and DT/R must be stable i.e.
DEN = high and DT/R = 0 for input or DT/R = 1 for output.
2. At the trailing edge of ALE, ICs 74LS373 or 8282 latches the address.
3. During T2 the address signals are disabled and S3-S7 ale available on AD16/S3-AD19/S6
and BHE/S7. Also DEN is lowered to enable transceiver.
4. In case of input operation, RD is activated during T2 and AD° to AD15 go in high
impedance preparing for input.
5. If memory or I/O interface can perform the transfer immediately; there are no wait states
and data is output on the bus during T3.
6. After the data is accepted by the processor, RD is raised high at the beginning of T4.
7. Upon detecting this transition during T.4, the memory or I/O device will disable its data
signals.
8. For an output operation, processor applies WR = 0 and then the data on the data bus
during T2.
9. In T4, WR is raised high and data signals are disabled.
10. For either input or output operation, DEN is raised during 14 to disable the transceiver.
Also M/I0 is set according to the next transfer at this time or during next T1 state. Thus
length of bus cycle in 8086 is four clock cycle. If the bus is to be inactive after completion
of bus cycle, then the gap between the successive cycles is filled by ideal state clock
cycles.

When the memory or I/O device is not able to respond quickly during transfer, wait states (Tw)
are inserted between T3 and T4 by disabling the READY input of the 8086. The bus activity
during wait state is same as during T3.

Q.34 Compare Pentium I, Pentium II and Pentium III processors (D2016)

 Pentium Pentium Pro Pentium II Pentium III Pentium 4
Processor Processor Processor Processor Processor
Introduced 03/23/93 11/01/95 05/07/97 02/26/99 11/20/00
Operations Per 2 3 3 5 6
Clock Cycle
Max Clock 60MHz system 60MHz system 66MHz system 100MHz system 400MHz system
Speed bus: bus: bus: bus: bus:
150MHz 180MHz 333MHz 1.0GHz 2.40GHz

66MHz system 66MHz system 100MHz system 133MHz system 533MHz system
bus: bus: bus: bus: bus: 2.53GHz
200MHz 200MHz 450MHz 1.4GHz
Bus Frequency 60MHz, 60MHz, 66MHz 66MHz, 100MHz, 400MHz
66MHz 100MHz 133MHz (100 * 4),
533MHz
(133 * 4)
Number of 3,100,000 5,500,000 7,500,000 24,000,000 42,000,000
Transistors (0.8 micron) (0.35 micron) (0.35 micron) (0.13 micron) (0.13 micron)
L1 Cache 16KB 16KB 32KB 32KB 12k µop + 8KB
Data
L2 Cache - 1MB 512KB 512KB 512KB
(on chip) (off chip) (on chip) (on chip)
Addressable 4GB 64GB 64GB 64GB 64GB
Memory
Integer Pipelines 2 2 2 2 4
Floating Point 1 1 1 1 2
Pipelines
Brief Superscalar Intel’s first true Dual independent Data Prefetch Capable of
Description architecture server / bus, dynamic Logic, Level 2 delivering 4.2GB
brought 5X the workstation chip execution, Intel Advanced of data-per-second
performance of MMX technology Transfer Cache into and out of the
the 33MHz processor
Intel486 DX
processor

Q.35 List addressing modes of 8086. (D2016)

Addressing modes in 8086 microprocessor

The way of specifying data to be operated by an instruction is known as addressing

modes. This specifies that the given data is an immediate data or an address. It also
specifies whether the given operand is register or register pair.
Types of addressing modes:
Register mode – In this type of addressing mode both the operands are registers.
Example:
MOV AX, BX
XOR AX, DX
ADD AL, BL
Immediate mode – In this type of addressing mode the source operand is a 8 bit or
16 bit data. Destination operand can never be immediate data.
Example:
MOV AX, 2000
MOV CL, 0A
ADD AL, 45
AND AX, 0000
Note that to initialize the value of segment register an register is required.
MOV AX, 2000
MOV CS, AX
Displacement or direct mode – In this type of addressing mode the effective
address is directly given in the instruction as displacement.
Example:
MOV AX, [DISP]
MOV AX, [0500]
Register indirect mode – In this addressing mode the effective address is in SI, DI
or BX.
Example: Physical Address = Segment Address + Effective Address
MOV AX, [DI]
ADD AL, [BX]
MOV AX, [SI]
Based indexed mode – In this the effective address is sum of base register and
index register.
Base register: BX, BP
Index register: SI, DI
The physical memory address is calculated according to the base register.
Example:
MOV AL, [BP+SI]
MOV AX, [BX+DI]
Indexed mode – In this type of addressing mode the effective address is sum of
index register and displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]
Based mode – In this the effective address is the sum of base register and
displacement.
Example:
MOV AL, [BP+ 0100]
 Based indexed displacement mode – In this type of addressing mode the effective
address is the sum of index register, base register and displacement.
Example:
MOV AL, [SI+BP+2000]
String mode – This addressing mode is related to string instructions. In this the
value of SI and DI are auto incremented and decremented depending upon the value
of directional flag.
Example:
MOVS B
MOVS W
Input/Output mode – This addressing mode is related with input output operations.
Example:
IN A, 45
OUT A, 50
Relative mode –
In this the effective address is calculated with reference to instruction pointer.
Example:
JNZ 8 bit address
IP=IP+8 bit address

Q.36 Explain branch prediction mechanism is on Pentium processor(D2016) (M 2016) (D 2016)

Why do we need branch prediction?

1. The gain produced by Pipelining can be reduced by the presence of program transfer
instructions eg JMP, CALL, RET etc
2. They change the sequence causing all the instructions that entered the pipeline after
program transfer instructions invalid
3. Thus no work is done as the pipeline stages are reloaded.
Branch prediction logic:
To avoid this problem, Pentium uses a scheme called Dynamic Branch Prediction. In
this scheme, a prediction is made for the branch instruction currently in the pipeline. The
prediction will either be taken or not taken. If the prediction is true then the pipeline will
not be flushed and no clock cycles will be lost. If the prediction is false then the pipeline
is flushed and starts over with the current instruction.
It is implemented using 4 way set associated cache with 256 entries. This is
called Branch Target Buffer (BTB). The directory entry for each line consists of:
 Valid bit: Indicates whether the entry is valid or not.
 History bit: Track how often bit has been taken.
Source memory address is from where the branch instruction was fetched. If the
directory entry is valid then the target address of the branch is stored in corresponding
data entry in BTB.
Working of Branch Prediction:
1. BTB is a lookaside cache that sits to the side of Decode Instruction(DI) stage of 2
pipelines and monitors for branch instructions.
2. The first time that a branch instruction enters the pipeline, the BTB uses its source
memory to perform a lookup in the cache.
3. Since the instruction was never seen before, it is BTB miss. It predicts that the
branch will not be taken even though it is unconditional jump instruction.
4. When the instruction reaches the EU(execution unit), the branch will either be taken
or not taken. If taken, the next instruction to be executed will be fetched from the
branch target address. If not taken, there will be a sequential fetch of instructions.
5. When a branch is taken for the first time, the execution unit provides feedback to the
branch prediction. The branch target address is sent back which is recorded in BTB.
6. A directory entry is made containing the source memory address and history bit is set
as strongly taken.

The diagram is explained by the following table:

History Resulting Prediction

Bits Description made If branch taken If branch not taken

Remains in same Downgraded to weakly

11 Strongly Taken Branch Taken state taken

10 Weakly Taken Branch Taken Upgraded to Downgraded to weakly

History Resulting Prediction
Bits Description made If branch taken If branch not taken

strongly taken not taken

Weakly Not Branch Not Upgraded to Downgraded to

01 Taken Taken weakly taken strongly not taken

Strongly Not Branch Not Upgraded to

00 Taken Taken weakly not taken Remains in same state