0% found this document useful (0 votes)
0 views

Architecture Notes

The document explains the role of buses in computer systems, detailing how CPU, caches, memory, and IO devices communicate through a system bus. It discusses bus arbitration methods including daisy chaining, polling, and independent requesting, highlighting their advantages and drawbacks. Each method varies in complexity, control line requirements, and the ability to manage competing requests for bus access.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
0 views

Architecture Notes

The document explains the role of buses in computer systems, detailing how CPU, caches, memory, and IO devices communicate through a system bus. It discusses bus arbitration methods including daisy chaining, polling, and independent requesting, highlighting their advantages and drawbacks. Each method varies in complexity, control line requirements, and the ability to manage competing requests for bus access.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 41

Buses:

The various processor-level components, CPU, caches, main memory, and IO (peripheral) devices within a computer system
communicate via buses. The term bus in this context covers not only the physical links among the components,

but also, the mechanisms for controlling the exchange of signals over the bus. Figure 7.1 depicts the most basic computer bus
structure. Here a single bus, the system bus, handles all intra system communication. All units share the system bus.

therefore, at any time only two units can communicate with each other. A typical system bus transaction is a memory read
(load) operation that involves the transfer of one or more data words over the system bus from the memory (cache or main)

M to the CPU. A memory writes (store) operation transfers data over the system bus in the opposite direction. Input-output
operations normally involve data transfers between an IO device and M. In all the preceding operations M is a passive or slave
device with respect to system bus transactions, whereas the CPU can actively control the system bus, that is, serve as a bus
master. IO devices are normally thought of as slave units, but they can be made into bus masters via control units such as
specialized IO controllers or general-purpose IO processors. As Figure 7.1 indicates, the system bus consists of three main
groups of lines: address, data, and control. (Not shown are the lines that distribute electrical power to the bus units.) The
address lines, typically 8 to 32 in number, transmit the addresses of data items stored in the system's main memory or IO
address space. The data lines, typically 16 to 128 in number, transmit data words over the bus. Finally, the control lines perform
such functions as identifying the transaction type (memory read, memory write, IO interrupt, and so forth) and synchronizing
communication between fast and slow units.

Bus arbitration.

The possibility exists that several master or slave units connected to a shared bus will request access to the bus at the same
time. A selection mechanism called bus arbitration is therefore required to enable the current master, which we will refer to
as the bus controller, to decide among such competing requests. We discuss three representative arbitration schemes: daisy
chaining, polling, and independent requesting. These methods differ in the number of control lines they require and in the
speed with which the bus controller can respond to bus-access requests of different priorities. Some bus systems combine
several distinct arbitration techniques. illustrates daisy-chaining arbitration. This method involves three control signals to
which we assign the generic names BUS REQUEST, BUS GRANT, and BUS BUSY. All the bus units are connected to the BUS
REQUEST line. When activated, it merely serves to indicate that one or more units are requesting use of the bus. The bus
controller responds to a BUS REQUEST signal only if BUS BUSY is inactive. This response takes the form of a signal placed on
the BUS GRANT line. On receiving the BUS GRANT signal, a requesting unit enables its

physical bus connections and activates BUS BUSY for the duration of its new bus activity. The main distinguishing feature of
daisy chaining is the way the BUS GRANT signal is distributed; it is connected serially from unit to unit as shown in Figure.
When the first unit requesting access to the bus receives BUS GRANT, it blocks further propagation of that signal, activates
BUS BUSY, and begins to use the bus. When a non-requesting unit receives the BUS GRANT signal, it forwards

the signal to the next unit. Thus, if two units simultaneously request bus access, the one closer to the bus controller, that is,
the one that receives BUS GRANT first, gains access to the bus. Selection priority is therefore determined by the order in

which the units are linked (chained) by the BUS GRANT lines. Daisy chaining requires very few control lines and embodies a
simple, fixed arbitration scheme. It can be used with an essentially unlimited number of bus units. Since priority is wired in, a
unit's priority cannot be changed under program control. If it generates bus requests at a sufficiently high rate, a high-priority
unit like U1 can lock out a low-priority device like Un. A further difficulty with daisy chaining is its susceptibility to failures
involving the BUS GRANT lines and their associated circuitry. If unit Ui, is unable to propagate the BUS GRANT signal, then no
Uj where j > i can gain access to the bus.

The bus-arbitration scheme called polling replaces the BUS GRANT line of the daisy-chain method with a set of poll-count lines
that are connected directly to all units on the bus, as depicted in Figure. As before, the units request access to the bus via a
common BUS REQUEST line. In response to a signal on BUS REQUEST, the bus controller proceeds to generate a sequence of
numbers on the poll-count lines. Each unit compares these numbers, which may be thought of as unit addresses, to a unique
address assigned to that unit. When a requesting unit Ui finds that its address matches the number on the poll-count lines, Ui
activates BUS BUSY. The bus controller responds by terminating the polling process, and Ui connects to the bus.

The priority of a bus unit is determined by the position of its address in the polling sequence. This sequence can be
programmed if the poll-count lines are connected to a programmable register; hence selection priority can be altered under
software control. A further advantage of polling over daisy chaining is that in polling a failure in one unit need not affect the
other units. This flexibility is achieved at the cost of more control lines (k poll-count lines instead of one BUS GRANT line). Also,
the number of units that can share the bus is limited by the addressing capability of the poll-count lines.

The third arbitration technique, independent requesting, has separate BUS REQUEST and BUS GRANT lines for every unit
sharing the bus. This approach, which is depicted in Figure, provides the bus controller with immediate identification

of all requesting units and enables it to respond rapidly to requests for bus access. The bus-control unit determines priority,
which is programmable. The main drawback of bus control by independent requesting is the fact that In BUS REQUEST and
BUS GRANT lines must be connected to the bus controller in order to control n devices. In contrast, daisy chaining requires
two such lines, while polling requires approximately log2 n lines.

You might also like