Department of Electrical & Electronic Engineering

Bangladesh University of Engineering & Technology

EEE466 Analog Integrated Circuits and Design Laboratory
Lab. 1:
Study of the basic current-versus voltage curve, threshold voltage,
transconductance and figure of merit of the MOS transistor in the process
technology library (pdk)

Objectives:
 To login, start a shell tool and start the Cadence virtuoso software
 To learn about PDK and add the PDK library to the Library Manager
 To create a working library and getting familiar with technology
 To study the IV characteristics of the MOS transistor in the technology library

1-1. Getting Started

1. Run Xming from the desktop. Then run putty.exe from your desktop. Under the Saved Sessions
dialog box click on VLSI and then click on Load. (Server IP address : (172.17.0.29) port22 and
click X forwarding) Next click on Open tab. Log in to Cadence workstation using the username and
password provided. Your user name will be vlsix and your password will also be vlsix, where x is any
number from 1 to 19 for Sec 1 and 21 to 39 for Sec 2. vlsi20, vlsi40 and the rest are reserved for the
instructors.

2. After successful login type cd cds_work and then press enter.

3. Run $csh. The following should appear

4. Type virtuoso & and virtuosos Command Interpreter Window (CIW) appears at the bottom of the
screen.
v
1-2. Creation of a Design Project and adding Library to the design

A unique directory should be created for each circuit design project. For you, the directory cds_work
is created by the administrator. So all your project works must be performed under this directory.
First of all we will add the generalized 45 nm process design kit from cadence known as gpdk045 to
our library path as follows.

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Adding the gpdk045 library to your library path

The Cadence® Library Path Editor helps you to define the libraries being used in your design. You
can set your cds.lib file or lib.defs file, or both, to point to the reference and design libraries you want
to use in your design.

1. In the CIW, execute Tools → Library Path Editor → Edit → Add Library. The add Library
form appears.
2. Add the “gpdk090” library from “home/eda/cadence/tech/process/gpdk090_v4.6/libs.oa22” and
press ok.

3. In the library path editor execute File →Save as. Make sure that both cds.lib and lib.defs are
selected.
Click OK the new paths will be saved and you will be able to use the above library.

4. Following the above procedure add the analogLib library from the following location
/home/eda/Cadence/IC615/tools.lnx86/dfII/etc/cdslib/artist

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5. Similarly add the library basic from the following location
/home/eda/Cadence/IC615/tools.lnx86/dfII/etc/cdslib

1-3. Learning the Fundamentals of Process Design Kit (PDK)

Objective : To learn about PDK and add the PDK library to the Library Manager
All VLSI design whether analog or digital, starts with a Process Design Kit known briefly as PDK.
A PDK contains the process technology and needed information to do device-level design in the
Cadence Design Framework II (DFII) environment. The following diagram shows the relationship
of the various components of the PDK and their relationship to the Cadence Design System (CDS)
Tool .

Throughout the labs we will use a generic, foundry independent 90 nm CMOS mixed-signal process
kit developed by Cadence. We will call it generic PDK 90 nm briefly as gpdk090. As seen from the

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figure above a PDK contains all the necessary design and technology data to successfully design and
simulate a VLSI chip on a particular foundry. The foundry provides the necessary technological data,
design rules, and the device models. Also PDK contains schematic symbols with all necessary views,
as well as device extraction rules for Layout versus Schematic (LVS) check. It also provides parasitic
extraction rules.

1-4. Starting the Online Help

In the CIW window Scroll the Help menu and select 'Cadence Documentation'. The Cadence on-line
help documents appear. Alternately you can type cdshelp in the Linux window and the same
documentation will appear.

Lab 1-5. Schematic Entry

To create a library and getting familiar with the technology : MOS I-V characteristics

Creating a library
Now we will create a working library to store our design and attach it to desired technology library.
1. In the CIW, execute File New  Library
2. The new Library form appears. In the name field of the New Library type gpdktraining.

3. In the field under the Directory Section, verify that the path to the library is set to
/var/home/vlsixx/
4. Select Attach to an existing tech file and click ok.
5. Attach Library to Technology Lib appears.

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 6. Select the gpdk90 technology library and click OK.
7. In the Library Manager window verify that the gpdktraining library is listed.

Getting Familiar with Technology: MOS IV Characteristics

In this exercise, you will learn how to enter simple schematic and run a simulation to obtain
characteristics of transistors for our technology (gpdk090).
Entering Design Schematic

1. In the Command Interpreter Window (CIW) or Library manger execute File -->New --
>Cellview.
2. Set up the create new file form as follows –
Library Name – gpdktraining, Cell Name – MOS_IV,
View name – schematic, Type – Schematic,
Application Open with – Schematic L

3. Click Ok when done.

A blank schematic window for the MOS_IV design appears.

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 In the schematic window , execute CreateInstance.

4. Next, we will create simple schematic consisting of an NMOS, a PMOS, and a few bias
voltage sources. To create an instance, you can click Add  Instance in the Virtuoso
schematic editor or simply use shortcut key “i”. The following dialog will appear:

Click Browse to select a library component

Another window will show up. Choose gpdk090 library, nmos1v cell, symbol view. (note:
while you are doing this, the Add Instance window is getting updated as well).

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 5. Similarly add pmos1v cell. Make sure that the view name field in the form is set to symbol.
You will update the Library Name, Cell Name, and the property values given in the table
below as you place each component.
6. Now we can adjust the size of the transistors by editing instance properties. Left click on the
NMOS to select the component. Then, press “q” to modify its properties or in schematic
window select Edit  Properties  Object. Modify the transistor width and set Total Width

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 to 240nm (this is 2x the minimum channel width), then press Tab key and the Finger Width
will be set to the same value. Click OK

7. Repeat this for PMOS to set Total Width and Finger Width to 480nm. To deselect the object
press keyboard command contrl-d.

8. Next, instantiate DC voltage source (cell vdc from analogLib library) to bias the transistors.

Place VDC in a suitable place in the schematic window to simulate Drain-Source Voltge
VDS. Similarly place VDC to simulate Gate –Source Voltage VGS. Since we are going to
sweep values of gate and drain voltages, specify parametric values VGS and VDS as DC
voltage under object properties.

9. Use Add  Wire menu or simply press “w” key to enter wiring mode / Esc to exit. It is a
good practice to periodically save your work by clicking on Check and Save button (the
checkmark button just below of the Tools menu). You can also save your work from the
drop-down menu Design Save.
10. The last step is to add zero valued voltage sources in series with the transistors in order to be
able to probe the currents. The final schematic looks like this:

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 Click Close and point your mouse cursor over the Virtuoso editing window.

1-6. Netlist Creation and Simulation using Spectre and observation of MOS I-V
Characteristics
Opening the Analog Design Environment

1. In the Schematic window execute Launch → ADE L

Analog Design Environment (ADE) window will open.

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 2. Select your design by executing Setup → Design → MOS_IV
3. Select the directory where the simulation data will be saved by executing Setup →
Simulator/Directory/host. The default directory is created in your working directory with
name 'simulation'. You can choose this directory or choose any other directory.
4. Set up the model libraries by executing Setup → Model Libraries. Select the following model
library /usr/local/cadence/local/gpdk090_v4.6/models/spectre/gpdk090_mos.scs

5. In this model libraries there are models to simulate various corners like fast-fast (FF), fast-
slow (FS), typical-typical(TT) etc. We will choose the section typical from the section scroll
bar and select the section 'TT_s1v'. These will enable us to use the TT models of the 1.2 V
MOS transistors.

6. Now open Analog Design Environment (ADE) GXL window. Execute Variables  Edit to
specify initial values for VDS and VGS parameters. Enter VDS in the Name field and 0.5 in the

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 Value (Expr) field and click Add to save the variable settings. Repeat this for VGS, you
should get the window as shown on the left and click OK.

1. Now choose the analysis to be done. Select DC analysis. In the DC analysis window select
Design Variable and put Variabel Name VDS. Select Sweep range as start 0 stop 1, Step type
Linear, Step Size 0.05.

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 2. Your Analog Design Environment window should now look like this:

3. Select the output to be plotted by executing Outputs → To be plotted → Select on schematic

in the ADE window. Schematic window will pop up, click on the positive terminal of dummy
voltage sources to select IDS for NMOS and PMOS.

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 The Analog Design Environment window should now look like this:

4. Before closing the Virtuoso Analog Environment window, it is a good idea to save design
settings in a state file, so we can load it up next time. To do this, click on Session  Save
State and save state name in the Save As field as state_MOS_IV. Next time you run Cadence,
you can simply load the simulation settings from this file.
Note: when you are loading up the file, don’t forget to specify the correct path (in our case,
it is: Var/home/GRPxxx/.state_MOS_IV).

5. The settings so far would generate I-V curve for a single value of VGS variable (0.5V). In
order to sweep VGS, go to Tools Parametric Analysis… and set the parameters as shown
below:

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 Here select sweep 1 variable VGS, From 0.2 to 1 Step control Linear, Total Steps 5.

12. It is a good idea to save design settings again in a state file, so we can load it up next time.
To do this, click on Session  Save State and set State Save Directory to
~/.artist_states
and save state name in the Save As field as state_MOS_IV. Next time you run Cadence, you
can simply load the simulation settings from this file.
Note: when you are loading up the file, don’t forget to specify the correct path (in our case, it
is: ~.artist_states).

13. Now in Parametirc analysis window perform Analysis  Start-selected. to create netlist and
run parametric simulation. After the simulation finishes, you will get a plot of overlapped I-
V curves for NMOS and PMOS that look like this:

Finally, we are going to separate the plots into two sub-graphs. Click on the New Subwindow
button as shown in the figure above. Left click on the V4 curves, one by one, and drag over to the
right plot. We can format the axis to display currents on the same scale. Double-click on the Y-
axis labels for the NMOS (left plot) and enter the Y-axis setting from 0 to 175 µA. Do the same for
PMOS (right plot) to plot both currents on a 0-175µA scale. You can also color the lines and add
labels (Graph > Label > Add).

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The final plot should look like as shown below.

1-7. Measuring the threshold voltage of MOS transistor

The practical way of measuring the threshold voltage of a MOS transistor is to plot the (IDS) vs.
VGS curve by keeping the transistor in saturation region (VGS=VDS). The slop of the curve is
linear. The interception of the slope of the curve with VGS axis is taken as the threshold voltage
of the device. Find the threshold voltage of the TT, FF, SS MOS model corners. Also find the
threshold voltage of the high threshold voltage (high vt) and high voltage (2.5 volts) NMOS
transistors.

VGS

IDS

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1-8. Measuring the Figure of Merit of MOS transistor
Save operating point of MOS.
(1) Plot gm vs Vgs plot of NMOS transistor. Remember that gm can be plotted by using either of
the three equations. However since exact value of process parameters Kn is not known to us,
gm can be conveniently plotted with the equation below:
2I D 2I
gm   D (4.71)
VGS  Vt VOV
(2) Now plot gm per unit current i.e. gm/ID of the NMOS transistor. This parameter is a dc figure
of merit of the transistor.
Create a file save_op.scs in the simulation directory. In the file simply write Save MO:all. Now
include this file in ADE by choosing spectre simulation file setup and showing the path of the file.
You can now plot various curve of interest.

1-9 Extra Exercise:

[Note: Details about different types of devices available in the gpdk and their rules are available in
the following location :[ /home/eda/cadence tech/gpdk090_v4.6/docs/gpdk090_DRM.pdf and in
gpdk090_pdk_referenceManual.pdf

Report :
All the Reports relating to EEE 466 have to be submitted in the form of the standard lab report
template for EEE466. In addition to the requirements in the template answer the following questions:

(1) For same W and L i.e. W=240nm and L=100nm find the mobility ratio of NMOS and PMOS
i.e. µn/µp at (Vgs=0.6 V, Vds=0.8 V), (Vgs=0.4 V, Vds=1 V), (Vgs= 1 V, Vds= 1 V). Give
your comments on the values obtained.
(2) What value of threshold voltage have you obtained in experiment 1-7 for NMOS and PMOS.
Comment on the value of the value of the threshold voltage.
(3) Plot ro vs Vgs of the NMOS transistor and comment on the ro values at different operating
condition.
(4) Give your comment on the gm vs. Vgs curve obtained in experiment 1-8 (1).
(5) Give your comment on gm/ID curve obtained in experiment 1-8 (2). Which region of operation
will be the most efficient (i.e. Weak inversion, moderate inversion and strong inversion) ?
(6) Observe the BSIM3v3 MOS models of the different MOS transistors available in the gpdk090
technology library and try to understand the meaning of different parameters. In a Table
summarize the values of the critical parameters for different types of MOS transistors and
make comment about the difference. (see ../gpdk090_v4.6/models/spectre/gpdk090_mos.scs)
(7) Repeat the above simulation with Slow and Fast NMOS by selecting the SS and FF model
corners. Explain the difference in I-V curve.

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