Allegro Sigrity SI

Streamlining the creation of high-speed interconnect on digital PCBs

and IC packages

The Cadence® Allegro® Sigrity™ signal integrity (SI) integrated high-speed design and analysis
environment streamlines creation of high-speed interconnect on digital printed circuit board (PCB)
systems and IC packages. A range of capabilities—from basic to advanced—enable designers and
electrical engineers to explore, optimize, and resolve issues related to electrical performance at
all stages of the design cycle. By enabling an electrical constraint-driven design flow, this unique
environment accelerates the time to design success while reducing the overall cost of end products.

Allegro Sigrity SI Solution can be converted to power-aware using 3D-full-wave field solvers and
IBIS models, enabling transistor-level a number of methods in between.
Cadence Allegro Sigrity SI provides a
accuracy in a fraction of the simulation Utilizing both buffer models and
scalable, cost-effective pre- and post-
time. interconnect models, analysis can
layout system interconnect design and
be performed early to refine design
analysis environment. Included are Modeling interconnect is accom-
intent, during the design process to
both first-order and advanced analysis plished through multiple methods.
validate progress, and as the design is
for the board, package, and system Depending on the detail available
finalized to ensure electrical specifica-
levels. The Allegro Sigrity SI base and the expertise of the user, signals
tions are met.
integrates tightly with Cadence PCB can be modeled with ideal trans-
and IC package layout editors, and mission line parameters defined by the
Cadence Allegro Design Authoring— user or with extracted S-parameters
enabling front-to-back, constraint-
driven, high-speed PCB and IC
package design.

Allegro Sigrity SI addresses the design

challenges presented by increasing
design density, faster data throughput,
and shrinking product design
schedules by enabling designers to
address high-speed issues throughout
the design process. This approach
allows design teams to eliminate time-
consuming iterations at the back-end
of a design process.

Modeling of the I/O buffer is accom-

plished by using the IBIS modeling
standard. Transistor-level models

Figure 1: Electrical constraints guide the design process and reduce design
iterations. SI analysis can be performed throughout the design process
with signal, power, and ground coupled together for final signoff.
 Allegro Sigrity SI

Key Capabilities
• Highly integrated design and analysis
environment removes the need for
error-prone and time-consuming
manual design translation

• Intuitive pre-route analysis tools enable

a design methodology that streamlines
post-route design verification through
a consistent front-to-back electrical
constraint management environment

• Timing budgets of complex source-

synchronous parallel interfaces can be
efficiently and accurately validated with
power-aware analysis that considers
simultaneous switching noise (SSN)

• Serial-link design methodology support

Figure 2: SI analysis with ideal power and ground (blue) compared to SI analysis with
pre- and post-route techniques that
non-ideal power and ground (green). Analysis with ideal power and ground may create
guide physical implementation, screen a false sense of security. Analysis with non-ideal power and ground catches ringback and
routed designs, and guide the designer timing push-out issues.
to the appropriate signals to perform
fast, accurate, and detailed million-bit extracted, and simulated as one electrical level of accuracy as transistor-level
simulations using the latest industry- net from either schematic or layout. The models, but simulate 50 to 100 times
standard IBIS-AMI SerDes models SigXplorer module integrates with logical faster than the transistor-level version.
• IC package designs are easily assessed or physical design tools and provides a
2. Interconnect modeling is performed
for design quality and characterized for graphical view of I/O buffers, transmission
using fast and accurate hybrid solver
use in die-to-die system analysis lines, and vias such that complex topol-
technology or with detailed 3D
ogies can be modified in a what-if fashion
full-wave solving technology. All
Features without having to change the actual
extractions include signal, power, and
design. SigXplorer also allows engineers
The Allegro design canvas features ground coupled together.
to sweep various parameters within the
included with Allegro Sigrity SI can be topology to identify a topology solution 3. Interconnect and I/O models are
used to both view and modify a design as space, which can then be captured in connected together in a topology
analysis is performed on an Allegro PCB the constraint management system and canvas. Interconnect models may
or IC package design. In addition, users guide PCB designers to first-pass electrical consist of chip, package, board,
can start with a blank canvas, mock up a compliance. I/O buffers can be modeled connector, or cable models. These
design, and perform what-if power-aware using industry-standard IBIS and SPICE interconnect models may be either
analysis to learn early how signal, power, models (encrypted or unencrypted). simple pre-route transmission lines
and ground or the detailed extractions discussed
will interact with different stackup Parallel bus design and power-aware
in Step 2. Using Model Connection
configurations. SI analysis methodology
Protocol (MCP) headers in the
Integrated high-speed design and Allegro Sigrity SI provides a detailed interconnect models, each fabric can
and thorough methodology to perform be intuitively connected to the proper
analysis
analysis of all the signals associated with signals in the connecting fabric. The
To eliminate the risk of design translation a source-synchronous bus such as DDR3. graphical user interface (GUI) allows
issues, Allegro Sigrity SI is seamlessly Utilizing a four-step process, the time to for a simplified way of cascading
integrated with the Allegro PCB and IC accurately simulate various configurations S-parameter interconnect models of
package layout editors and allows for (read/write, active, idle) associated with each part of the system (e.g., package,
constraints and models to be tightly the functioning of source synchronous PCB, DIMM) and connecting signal,
integrated with the design file. The buses with or without on-die termination power, and ground from each model
integrated design and analysis system is (ODT) is shortened. These steps are as together using a spreadsheet-type
aware of multi-net electrical constructs follows: interface enabled through MCP.
from logical design authoring to physical
1. Power-aware IBIS models are converted 4. Parallel bus analysis is performed using
implementation. For example, differ-
from transistor-level models. These IBIS the power-aware connected models
ential pairs and extended nets (nets with
5.1-compliant models provide the same discussed in Step 3. The simulation
a series termination) are recognized,

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 Allegro Sigrity SI

discussed in Step 3. Noise can be

injected into the VRM to allow the
simulation to consider less than ideal
power and ground.

The simulation results are captured and

post processed according to the selected
serial link standard (e.g., PCI Express®
3.0). Compliance checks are made and
collected into an easy-to-read HTML
report file.

IC packaging assessment and model

extraction methodology

Figure 3: SI for serial data channels includes IBIS-AMI models to represent the transceivers, Allegro Sigrity SI provides an environment
as well as sophisticated modeling techniques for all fabrics (chip-package-board) of the for the assessment, characterization,
topology. Results are reported in 2D, 3D, and in HTML report formats. and simulations of IC package (.mcm
or .sip) interconnect. Engineers can
make tradeoffs to minimize cost while
fully considers SSN. The simulation is serial data channel. The time to accurately maximizing performance of the package
aware of DDR3 test and measurement simulate and establish compliance is accel- module interconnect.
criteria and (based on slew rate) erated with the following four steps:
The electrical-assessment features are
properly derates setup and hold
1. IBIS-AMI models are connected to the most commonly used by the package
margins through user-defined derating
transceivers. These IBIS 5.1-compliant designer to gain a quick first-order
tables for different signals in the source
models provide the ability to optimize evaluation of the electrical quality of
synchronous bus.
parameters based on the channel that the package design. Available as part
The simulation results are captured and will be simulated. of the assessment capability is signal
post processed according to the parallel analysis (trace impedance and coupling
2. Interconnect modeling is performed
bus standard (e.g., DDR3). Timing checks checks), power/ground analysis (net-pair
using fast and accurate hybrid solver
are made between signals such as data and per-pin properties), and DC current
technology or with detailed 3D
and strobe and anything out of spec is analysis (DC current and IR drop analysis).
full-wave solving technology. All
highlighted in the waveform display. The assessment capability is accomplished
extractions include signal, power, and
with minimal electromagnetic expertise.
Serial link design and analysis ground coupled together.
HTML-based reports can be created
methodology showing the level of analysis that has
3. Interconnect and I/O models are
When engineers face today’s demands for connected together in a topology been performed along with the results.
faster data throughput, each section of canvas. Interconnect models may
The IC package assessment and model
the interface takes on greater complexity. consist of chip, package, board,
extraction methodology can prove partic-
Transceivers feature dynamic equalization connector, or cable models. These
ularly valuable when package design is
and clock and data recovery algorithms interconnect models may be either
outsourced. The electrical performance
that require advanced modeling simple pre-route transmission lines
assessment features provide a quick and
techniques. IC package and PCB inter- or the detailed extractions discussed
thorough means to assess the package
connect models must be extracted with in Step 2. Using MCP headers in the
design, which reduces the time before
more accuracy than ever before in order interconnect models, each fabric can
providing feedback to the package
to accurately characterize interconnect be intuitively connected to the proper
designers. When the assessment provides
from die to die. Interconnect struc- signals in the connecting fabric. The
good results, the extraction technology
tures must be carefully characterized GUI allows for a simplified way of
provides an efficient means for devel-
so signal loss, frequency-dependent cascading S-parameter interconnect
oping either full-package models or highly
materials, and impedance disconti- models of each part of the system (e.g.,
accurate package-section models for
nuities are all accurately represented package, PCB) and connecting signal,
use in high-frequency system-level time-
through broadband S-parameter inter- power, and ground from each model
domain simulation.
connect models. The Allegro Sigrity SI together using a spreadsheet-type
solution provides a detailed and thorough interface enabled through MCP. For more advanced analysis, package
methodology (similar to the parallel bus characterization engineers have access to
4. Channel analysis is performed using the
methodology described in the previous integrated hybrid (2D/3D) and full-wave
IBIS-AMI buffer models and coupled
section) to perform analysis of all the 3D field solver engines. These solvers can
signal, power, the interconnect models
signals associated with a high-speed be used to create full-package models

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 Allegro Sigrity SI

greatest, such as where a trace has been

pushed out over a void area in a power
or ground shape on a neighboring layer.
If not detected early, such conditions
may not be found until final post-route
analysis, which could impose a delay on
the schedule.

Similarly, the coupling checks point out

the largest coupling coefficients on the
PCB or IC package design, and allow
designers to explore alternative routing
schemes to minimize the possibility of a
crosstalk error being found during post-
route analysis.

While the impedance and coupling checks

provide a physical location that should
probably be edited, PCB and IC package
designers are often faced with the
Figure 4: Package assessment and extraction is tightly integrated with the package design dilemma of bending or breaking design
environment. A first-order assessment can be accomplished to provide quick feedback of rules in order to get a design completed.
the overall package performance. Detailed full-package models or 3D package sections can To provide an electrical assessment of
be extracted. The solution is rounded out with IR drop and thermal analysis capability.
potentially problematic nets, Allegro
Sigrity SI provides SI performance
or a smaller section of the package routing, planes, and decoupling capac- metrics. Without setting up detailed IBIS
can be extracted to create high-fidelity itors to derive working configurations for models, SI performance metric checks
S-parameter models. These models can implementation. can be run on large groups of signals,
be analyzed independently or passed off utilizing time-domain simulation and
Constraint-driven design
to system analysts to include the package considering non-ideal power and ground
model in their system topologies. methodology
rails. An extensive HTML-based report
Allegro Sigrity SI technology works can be created that will empower the
In addition, thermal and thermally aware
seamlessly with the constraint layout designer to assess the physical
IR drop analysis is available as part of the
management system of the Allegro layout from an electrical standpoint, and
solution.
PCB and IC Packaging Design tools. address a significant category of SI issues
Virtual prototyping environment Constraints derived through simulation in-design, thus accelerating the design
can be put into an Electrical Constraint flow.
Engineers can evaluate placement strat-
Set (EC Set) from within the topology
egies when used in conjunction with
canvas, SigXplorer. These EC Sets Benefits
Allegro design authoring tools, and assign
can then be applied to other nets in
design intent by embedding constraints • Pre- and post-route SI analysis
the design through the constraint
in the front-end design database. In integrated with the physical design flow
management system found in Allegro
addition, physical layouts can be quickly provides optimum methodology
Sigrity SI, Allegro Design Authoring, and
mocked up and advanced analysis can be
Allegro PCB Editor. Designers can use the • Rapid evaluation of feasibility, cost, and
performed to enable optimization. These
constraints developed through simulation performance tradeoffs through virtual
physical structures can be shared with
and exploration, and enable a front- to prototyping environment
PCB and IC- package designers to commu-
backend constraint-driven design process.
nicate physical design intent. • Electrical constraint capture enables
SI layout checks constraint-driven physical design
The value of the virtual prototyping
methodology
environment can be seen in memory Bridging the gap between implemen-
interface analysis. To understand the tation and analysis, Allegro Sigrity SI • Scalable crosstalk analysis, from
effects of SSN, structures that include provides unique layout checks that utilize segment-based crosstalk DRCs to
power, ground, and a memory bus must fast SI screening algorithms. The trace detailed time-domain simulation
be constructed. With these structures, impedance and coupling checks provide
• Hybrid (2D/3D) and full-wave 3D
which can be constructed in the Allegro insight into common SI problems without
solvers provide extraction scalability,
Sigrity SI environment, SI engineers can having to run detailed analysis. The trace
and enable power-aware SI analysis by
experiment with the stack-up, power impedance check can point a designer
extracting a power-distribution system
distribution system (including I/O models), directly to locations in the layout where
coupled with signals
the impedance discontinuities are the

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 Allegro Sigrity SI

• Advanced parallel-bus (DDR) and Operating System Support • Cadence certified instructors teach
serial-link (SerDes) analysis more than 70 courses and bring
Allegro platform technology: their real-world experience into the
• Electrical assessment of IC packages
• Linux classroom
quickly identifies electrical faults and
baselines performance metrics • Windows • More than 25 Internet Learning Series
(iLS) online courses allow you the
• Includes a SPICE-based simulation
Cadence Services and Support flexibility of training at your own
engine and embedded integration with
computer via the Internet
hybrid (2D/3D) and full-wave 3D field • Cadence application engineers can
solvers answer your technical questions by • Cadence Online Support gives you
telephone, email, or Internet—they can 24x7 online access to a knowledgebase
• Reads/writes Cadence Allegro PCB
also provide technical assistance and of the latest solutions, technical
(.brd), APD (.mcm) and Digital SiP
custom training documentation, software downloads,
Layout (.sip) files
and more

Allegro Sigrity SI Product Summary

Sigrity products Allegro Sigrity SI Base Power-Aware SI System Serial Link Package Assessment/
Option Option Extraction Option
Broadband SPICE® • •

Transistor to Behavioral Model • •

Conversion
CAD Design/Data Translators • • •

PowerDC™ •

PowerSI™ • •

PowerSI 3D EM Full-Wave • • •

Extraction
SPEED2000 ™ •

SystemSI™ - Serial Link Analysis •

SystemSI - Parallel Bus Analysis •

XtractIM ™ •

Note: An option license provides access to one product at a time

Allegro Sigrity SI Feature Summary

Features Allegro Sigrity SI Base Power-Aware SI System Serial Link Package Assessment/
Option Option
IBIS 5.1 support • • •

Graphical topology editor •

Bus-level topology editor • •

Generate estimated crosstalk •

tables
Detailed HTML simulation • • • •

reports
Differential pair extraction •

from Allegro Design canvas

Differential pair extraction •

from Allegro Design Entry HDL

Multi-terminal black boxes in • • •

topologies

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 Allegro Sigrity SI

Features Allegro Sigrity SI Base Power-Aware SI System Serial Link Package Assessment/
Option Option
Post-layout selection from •

Allegro PCB Editor

HSPICE interface • • •

Differential signal constraint •

capture
Sweep simulations • • •

Constraint development and • • •

capture of topologies
Constraint-driven floorplanning •

and placement
Allegro Constraint Manager •

Color-coded real-time feedback •

on violations
Spectre transistor-level model •

support
Source-synchronous bus analysis •

SSN analysis •

Batch simulation • • •

Constraint-driven routing •

Allegro route by pick •

Thermally-aware static IR drop •

analysis
Time domain simulation of • • •

S-parameters
Coupled via model generator • • •

for pre-layout explorations

High-capacity channel •

simulation
Optimum pre-emphasis bit •

configurations (“tap settings”)

BER prediction •

Bathtub curves •

Channel compliance—statistical •

analysis
2D (static and full-wave) •

extraction
Hybrid-solver (2D/3D) • • •

extraction
3D full-wave extraction • • •

Signal-quality screening of • • • •

routed nets
Impedance requirements •

calculator
Frequency domain analysis • • • •

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® 2013 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro and Broadband SPICE are registered trademarks and
Sigrity, PowerDC, PowerSI, SPEED2000, SystemSI, and XtractIM are trademarks of
Cadence Design Systems, Inc. All others are properties of their respective holders. 1595 10/13 SA/DM/PDF