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Digital and Logic Circuit Design, Questions

The assignment for EC-210 requires students to design a combinational circuit and implement a Boolean function using a multiplexer and external gates, with a strict emphasis on original thinking and valid approaches. Plagiarism is prohibited and will incur penalties, while submissions must be made as a single PDF file by the deadline of April 25, 2025. Additionally, students must analyze an exclusive-OR circuit with specified gate delays and determine output signals over a time range.

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7 views1 page

Digital and Logic Circuit Design, Questions

The assignment for EC-210 requires students to design a combinational circuit and implement a Boolean function using a multiplexer and external gates, with a strict emphasis on original thinking and valid approaches. Plagiarism is prohibited and will incur penalties, while submissions must be made as a single PDF file by the deadline of April 25, 2025. Additionally, students must analyze an exclusive-OR circuit with specified gate delays and determine output signals over a time range.

Uploaded by

eeshaamir2004
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 01

EC-210 Assignment (Syndicates A & B)

Deadline: 25 April 2025, 23:59H

Instructions:

• Please do not make use of any LLM tool. Solve it based on your own thinking and
logics. Correct answer is not important, the approach should be valid.
• Plagiarism is strictly prohibited and will result in a penalty of -5 absolute marks if
detected in any submission.
• Please ensure timely submission by the due date, and the assignment must be
submitted on LMS. For multiple pages, please make a single PDF file for online
submission.

Q1. Design a combinational circuit with three inputs, x , y , and z , and three outputs, A, B ,
and C . When the binary input is 0, 1, 2, or 3, the binary output is one greater than the
input. When the binary input is 4, 5, 6, or 7, the binary output is two less than the input.
Q2. Implement the following Boolean function with a 4 x 1 multiplexer and external gates.
𝐹(𝐴, 𝐵, 𝐶, 𝐷) = *(1, 2, 5, 7, 8, 10, 11, 13, 15)
Connect inputs A and B to the selection lines. The input requirements for the four data
lines will be a function of variables C and D . These values are obtained by expressing
F as a function of C and D for each of the four cases when AB 00, 01, 10, and 11. These
functions may have to be implemented with external gates.
Q3. The exclusive-OR circuit of the following Fig. has gates with a delay of 3 ns for an
inverter, a 6 ns delay for an AND gate, and a 8 ns delay for an OR gate. The input of the
circuit goes from xy = 00 to xy = 01. Determine the signals at the output of each gate
from t = 0 to t = 50 ns.

Figure: Exclusive-OR circuit

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