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Contents
Communication Systems Laboratory-II Experiments

1. PCM modulation and demodulation

2. Delta modulation and demodulation
3. Generation and detection of amplitude shift keying signals
4. Generation and detection of frequency shift keying signals
5. Generation and detection of phase shift keying signals
6. Generation and detection of quadrature PSK signals
7. Generation and detection of differential PSK signals
8. Simulation of ASK, FSK and PSK modulation techniques
9. Simulation of QPSK and DPSK modulation techniques
10. Simulation of Direct Sequence Spread Spectrum (DSSS) techniques
11. Write a simulation code to analyze the performance of binary modulation scheme in the
AWGN channel
12. Study of Huffman coding for encoding the source symbols

************

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DO’S AND DON’TS IN THE LAB

DO’S:-
1. Proper dress has to be maintained while entering in the Lab.
2. Students should carry observation notes and record completed in all aspects.
3. Do the connections neatly and firmly tightened.
4. Correct specifications of the equipment have to be mentioned in the circuit diagram.
5. Student should be aware of operating equipment.
6. Students should be at their concerned experiment table, unnecessary moment is restricted.
7. Student should follow the indent procedure to receive and deposit the equipment from the Lab Store
Room.
8. After completing the connections Students should verify the circuits by the Lab Instructor.
9. The reading must be shown to the Lecturer In-Charge for verification.
10. Students must ensure that all switches are in the OFF position, all the connections are removed.
11. All stools should be placed at their original positions.

DON’Ts:-
1. Don’t come late to the Lab.
2. Don’t eat, drink or use mobile in laboratories.
3. Don’t keep unwanted materials in the work table.
4. Avoid unnecessary talking while doing the experiment.
5. Don’t make or remove the connections with power ON.
6. Don’t switch ON the supply without verifying by the Staff Member.
7. Don’t switch OFF the machine with load.
8. Don’t leave the lab without the permission of the Lecturer In-Charge.

The following safety precautions and guidelines shall be followed in laboratory:

• Always wear a protective lab coat/overall and safety shoes.

• Locate and identify the positions of main switches, circuit breakers and emergency switches.
• Make sure of the availability and access to first aid kits, fire extinguishers and other safety
equipments.

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Power Supply Connections for Connecting +5V, -5V

Power Supply Connections for connecting +12v, -12v

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COURSE DESIGN, DELIVERY AND ASSESSMENT

Course code and Title: ECL66 Communication Systems Laboratory – II Course Credits :0:0:1
CIE : 50 Marks SEE : 50 Marks
Total No of Theory / Tutorial / Lab Hours : 14
Prepared by : T D Senthilkumar Date :01.03.2024
Reviewed by : Lakshmi S Date :02.03.2024
Prerequisites
Prerequisite Courses with codes
ECL56-Communication Systems Laboratory – I

List of Experiments

1. PCM modulation and demodulation

2. Delta modulation and demodulation
3. Generation and detection of amplitude shift keying signals
4. Generation and detection of frequency shift keying signals
5. Generation and detection of phase shift keying signals
6. Generation and detection of quadrature PSK signals
7. Generation and detection of differential PSK signals
8. Simulation of ASK, FSK and PSK modulation techniques
9. Simulation of QPSK and DPSK modulation techniques
10. Simulation of Direct Sequence Spread Spectrum (DSSS) techniques
11. Write a simulation code to analyze the performance of binary modulation scheme in the AWGN
channel
12. Study of Huffman coding for encoding the source symbols

Textbooks:
1. Simon Haykin, “Digital Communications”, John Wiley, Reprint 2014.
2. J. G. Proakis and M. Salehi, “Contemporary Communication Systems using MATLAB”,
1st Edition, PWS Publishing Company, 2007.
3. Cory L Clark, “Labview Digital Signal Processing and Digital Communications”, 1st
Edition, McGraw Hill Education, 2016.

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Concept map:

Digital Communication lab

DEALS WITH INVOLVES DEALS WITH

INVOLVES INVOLVES

Digital Waveform
Sampling Multiplexing Modulation Coding
Process Techniques Techniques Simulation

1.Natural sampling Time Division

1.FSK, ASK 1.PCM 1. BASK
2.Flat top Sampling Multiplexing
2.DPSK, QPSK 2.Delta modulation 2. BFSK
3.Signal Recovery 3. BPSK

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Course Contents and Experiments Schedule

Lesson No/ CO No. of

Topics
Session No Mapping hours

CYCLE - I
1. CO1 2 Hours
Pulse code modulation and demodulation

2. Delta modulation and demodulation CO1 2 Hours

Generation of Amplitude Shift Keying signals using IC 4016 and
3. CO2 2 Hours
recovery of the ASK signals using detector circuits.
CYCLE - II
Generation of Frequency Shift Keying signals using MUX CD
4. 4051 and recovery of the FSK signals using frequency CO2 2 Hours
discriminators.
Generation of Phase Shift Keying signals using MUX CD 4051
5. and detection of PSK signals using phase discriminating circuits. CO2 2 Hours

Generation and detection of Differential Binary signal using

6. CO2 2 Hours
DPSK kit.
7. Generation and detection Quadrature PSK using QPSK kit CO2 2 Hours
CYCLE - III
Simulation of ASK, FSK, PSK modulation and demodulation
8. CO2 2 Hours
technique using MATLAB

9. Simulation of QPSK and DPSK modulation techniques CO2 2 Hours

Simulation of Direct Sequence Spread Spectrum (DSSS)

10. CO3 2 Hours
techniques
Write a simulation code to analyze the performance of binary
11. CO4
modulation scheme in the AWGN channel
Study of Huffman coding for encoding the source symbols
12. CO5

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Course Outcomes:

1. Implement PCM and delta modulation scheme (POs – 3, 4, 5, 7, 11, PSO – 3)

2. Implement ASK, PSK, FSK, DPSK digital modulation schemes (POs – 3, 4, 7, 11, PSO – 3)
3. Understanding the concepts of DSSS systems. (POs – 2, 4, 11, PSO – 3)
4. Analyze the performance of various digital modulation techniques (POs – 2, 4, 11, PSO – 3)
5. Understanding the importance of source coding techniques in the communication system. (POs – 2, 4,
11, PSO – 3)

Mapping Course Outcomes with Program Outcomes:

Course Program Outcomes PSO

Outcomes 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
1 3 2 2 2 2 1 2 3
2 2 3 2 3
3 3 3 2 2 2 3
4 3 3 2 2 2 3
5 2 3 1 3

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Course Assessment and Evaluation:

Questions for CIE and SEE will be designed to evaluate the various educational components
(Bloom’s taxonomy) such as:

Continuous
Test Record Conduction Total
assessment
Test 1
10 20 20 50
Test 2

CIE and SEE evaluation

Semester-End
Sl.No Bloom’s Category Test 1 & Test II
Examination
1 Remember 10 10
2 Understand 10 10
3 Apply 40 40
4 Analyze 20 20

5 Evaluate 20 20
6 Create 0 0

CO mapping:

Lab record CO1, CO2, CO3, CO4, CO5

Test I CO1, CO2

Test II CO3, CO4, CO5

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Experiment no.1

PCM Generation and Detection

Aim:
To study the performance of the given CODEC chips in implementing generation and detection of
PCM wave.

Components required:
 IC-44233,
 IC-7493 (2no.s)
 Resistors-1kΩ, 560Ω
 Function generators, power supply,
 Oscilloscope.

Theory:
PCM is a digital representation of an analog signal where the magnitude of the signal was sampled
regularly at uniform intervals, then quantized to a series of symbols in a numeric (usually binary) code.
It refers to a system in which the standard values of a quantize wave are indicated by a series of
coded pulses. When these pulses are decoded, they indicate the standard values of the original quantized
wave. These codes may be binary, in which the symbol for each quantized element will consist of pulses
and spaces: ternary, where the code for each element consists any one of three distinct kinds of values
(such positive pulses, negative pulses, and spaces); or n-ary, in which the code for each element consists of
any number (n) of distinct values. The entire range of amplitude (frequency or phase) values of the analog
Wave can be arbitrarily divided into a series of standard values. Each pulse of a train, as shown in fig takes
the standard value nearest its actual value when modulated. The modulating wave can be faithfully
reproduced, as shown in fig 4.1. the amplitude range has been divided into 5 standard values in fig. each
pulse is given whatever standard value is nearest its actual instantaneous value. The greater the number of
standard levels used, the more closely the quantized wave approximates the original; an infinite number of
standard levels exactly duplicates the conditions of non quantization (the original analog waveform).
Although the quantization curve of fig is based on 5-level quantization in actual practice the levels
are usually established at some exponential value of 2. Such as 4(22), 8(23), 16(24), 32(25)…..N (2n).
Quantized FM is similar in every way to quantized AM. That is the range of frequency deviation equal to
the standard value nearest the actual deviation. At the sampling instant. Similarly for phase modulation,
quantization establishes a set of standard values. Quantization is used mostly in amplitude and frequency-
modulated pulse systems.
Fig shows the relationship between decimal numbers, binary numbers and a pulse code waveform that
represents the numbers. For a 16-level code; that is, 16 standard values of a quantized wave could be
represented by these pulse groups. Only the presence or absence of the pulses is important. The next setup
would be a 32-level code, represent by a 5-digit binary code and so forth.
Pulse coding can be performed in a number of ways. One of the ways is shown in the block diagram of
fig.4.3 here, the pulse samples are applied to a holding circuit (capacitor which stores pulse amplitude
information) and the modulator converts PAM to PDM. The PDM pulses are then used to gate the output
of a precision pulse generator that controls the number of pulses applied to a binary counter. The duration
of the gate pulse is not necessary an integral number of the repetition pulses from the precisely timed clock
pulse generator. Therefore the clock pulses gated into the binary counter by the PDM pulse may be a
number of pulses plus the leading edge of an additional pulse. This “partial” pulse may have sufficient
duration to trigger the counter, or it may be not. The counter thus responds only to integral numbers,
effectively quantizing the signal while, at the same time, encoding it,. Each Bistable stage of the counter
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stores ZERO or a ONE for each binary digit it represents (binary 1110 or decimal 14 is shown in fig 4.2.)
an electronic commutator samples the 20,21,22,and 23 digit positions in sequence and transmits a mark or
space bit (pulse or no pulse) in accordance with the state of each counter stage. The holding circuit is
always discharged and reset to zero before initiation of the sequence for the next pulse sample.
The PCM demodulator will reproduce the correct standard amplitude represented by the pulse code
group. However, it will reproduce the correct standard only if it is able to recognize correctly the presence
or absence of pulses in each position. For this reason, noise introduces no error at all if the signal-to-noise
ratio is such that largest peaks of noise are not mistaken for pulses. When the noise is random (circuit and
tube noise), the probability of the appearance of a noise peak comparable in amplitude to the pulses can be
determined. It is found that for 105 pulses per second, the approximate error rate for three values of signal
power to average noise power is:

17dB-10errors per second

20dB-1error every 20 minutes
22dB-1error every 2,000hour
Above threshold of signal-to-noise ratio of approximately 20dB, virtually no error occurs. Thus the
advantages of PCM are two-fold. First, noise interface is almost completely eliminated when the pulse
signals exceed noise levels by a value of 20dB or more. Second, regenerative repeaters can be used at
regular intervals in along distance communication link. At each regenerative repeater station, the binary
signal is reconstructed and retransmitted. Any number of regenerative repeaters may be used at regular
intervals without introducing much distortion into the signal.

Applications:
PCM has been used in digital telephone systems and electronic musical keyboards. It is also the
standard form for digital video. For example, using ITU-R BT601. However, uncompressed PCM is not
typically used for video in standard definition consumer applications such as DVD or DVR because the bit
rate required is far too high.

Implementation:
Figure 4.4 shows a PCM circuit using CODEC IC 44233, and the chip details of the IC are given in
figure 4.5(a). It is a monolithic silicon gate CMOS companding encoder/decoder chip designed to
implement the per channel voice frequency codes used in PCM systems. The chip contains band linking
filters and analog/digital conversion circuits that confirm A-law companding characteristic.
This chip supports 32 channels for multiplexing, out of which one channel will be used for marker
slot. The bandwidth of speech signal is 3400 Hz. Then the sampling rate (engineer’s design) will be 3.4kHz
x 2.2 =8.4 kHz, which can be approximated to 8 kHz. There are 8k samples/sec/channel and each sample is
encoded into 8 bits. Hence in each channel, the bit rate is 8 x 8 = 64k bits/sec. In order to multiplex 32
channels, we need a clock frequency of 32 x 64 = 2.048 MHz
Either a crystal of 2 MHz may be used to generate the clock or a function generator with a TTL
output at 2 MHz can be used as clock. Two mod-16 counters (÷ 256 from a 2 MHz clock) are used to
produce synchronized clock of 8 kHz, which will be applied to synchronized clock pins 11 & 12 of the
CODEC IC. The gain control pins 2 and 3 are shorted to achieve a unity gain. The PCM wave form is
available at pin 15 and the detected message at pin 5, which is shown in Figure 4.6(a). Figure 4.6(b) shows
the expanded version, where we can see that each PCM pulse shown in Figure 4.6(a) actually consists of 8-
bits in it as shown in Figure 4.6b).

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Circuit Diagram of PCM:

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Procedure:
 Connections are made as per circuit diagram shown in fig.
 D.C.power supply is switched on and applied the specified voltages.
 A TTL clock of 2 MHz is applied to the counter IC7493 at pin number 14 observe the output using
an oscilloscope at pin number 11 that should be 125 kHz (divided by 16 of 2 MHz).
 Check the output at pin number 11 of the 2nd IC 7493, that will approximately 8 KHz (divided by
256 of 2 MHz).
 Apply a sinusoidal message frequency of 1 kHz, 1v at pin no.1 of IC44233.
 Observe the PCM output at pin number of IC44233.
 Observe PCM output at pin number 8 of IC44233. You may have to change the time range of
oscilloscope to convenient range to observe the frame time (50µs range) and the 8 bit word length
(0.5µs range).
 Observe the changes at the PCM output and demodulated output by changing the frequency and
amplitude of the message signal.

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PCM Wave form (b) Expanded version

Result:
Generation of PCM signal wave forms using codec chip is observed on both frames and expanded
version and plotted on a graph sheet.

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Experiment no.2
Delta Modulation and Demodulation

Aim:
To Generate Delta Modulated signal and its Demodulation

Apparatus required:
 Op-Amp-IC741,
 IC7474,
 zener diode,
 Signal Generator (02 No.s)
 10kΩ potentiometer,
 0.1µf capacitor,
 DC power supply and
 CRO.
Theory:
Delta modulation is a simple and efficient method of analog to digital conversion where is to be
transmitted via a serial digital communications channel. ∆ Modulation can be used for digitizing voice for
secure, reliable communications and for I/O in data processing. Delta modulation has the advantage that its
signal to noise ratios (SNR) do not vary with distance in digital transmission and multiplexing and the
switching and repeating hardware is more economical and easier to design than with purely analog
systems.
Delta modulation is a method of encoding analog signals using a 1-bit (two - level) quantizer. ∆-
modulation can be viewed as a simplified variant of DPCM signal amplitude instead of the signal
amplitude itself. Figure 2.1 illustrates how an analog signal is approximated using delta modulation. at each
step, the analog message signal m(t) is compared to the quantized approximation mq(t). If the analog signal
is greater than the approximation. Then the approximation is incremented by a constant step size (∆S) and a
binary 1 is generated. If the analog signal is less than the approximation, then the approximation is
decremented by ∆S and a binary 0 is generated. In this way, a bit stream is generated that can be used to
reconstruct the message signal.

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A block diagram of a delta modulation system is shown in figure 2.2. The output of the accumulator
is an approximation to the message signal and it is the sum of all previous signal changes.
Practical implementations of a delta modulator using a comparator, a D flip flop and an integrator is
shown in figure 2.3. the modulator consists of a comparator in the forward path and an integrator in the
feedback path of a simple control loop. The digital output (Vd) is either high (logic 1) or low (logic 0) at
any given time. If Vd is high, the integrator output Vs is will be ramping up. Conversely, if Vd is low, the
integrator output Vs will be ramping down. When Vs is ramped to a value greater than m (t). Vd goes low
and Vs begins to ramp down until its once again less than m(t) and the process repeats itself. The digital
output Vd is therefore the differential of the input and contains information about the direction of signal
change for one level compared to the previous time interval.

Figure 2.4 shows the output plots. A 2nd order Butterworth low pass filter with a cut off frequency
of 4 khz was used to filter the reconstructed message signal.
An important characteristics of delta modulation is that the waveform that needs to be modulated
needs to be oversampled, i.e. the sampling rate for delta modulation needs to be very similar and there will
be a lot of redundancy in the information contained in each. Since delta modulation transmits a signal
related to the difference between signal values, transmission efficiency is achieved. A low pass filter at the
receiving circuit output will eliminate most of the quantizing noise. Generally, the lower the bit rate, the
higher the order of the filter. Two types of distortion limit the performance of the delta- modulation
encoder: slope overload and granular noise.

Slope Overload:
Slope Overload occurs when the modulating signal m(t) changes faster than the step size for each
clock period allows, i.e the step size delta is too small to follow portions of the waveform that have a steep
slope.
Granular Noise:
Granular noise is caused by a excessively large step size for signal parts with a small slope. It can
be reduced by decreasing the step size.

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Circuit diagram:

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Procedure:
 The circuit connections are made as shown in the figure 3.1.
 the sinusoidal signal is set at 100Hz, 1vp-p with an offset of 0.5v
 The pulse train p(t) is set at 10kHz and it is taken from the TTL or SYNC output of the signal
generator which provides a constant 5v peak and a variable frequency.
 The IC7474 when is fed with m(t) and p(t) are connected as shown in the fig 3.1 and it gives the
delta modulated output at pin.5.
 as obtained in the waveform the output DM wave has a greater on fine for increasing amplitude of
message signal m(t) and the on time decreases for the –ve wave of the input m(t)
 The reconstructed output of the m (t) which is taken from the output DM and fed through 10k pot
and a 0.1µf capacitor. Is also shown in the waveform which is comparable to the message signal
m(t).

Result and conclusion:

The waveforms of delta modulation and demodulations signal is observed and also seen the
distortions.

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Experiment no.3
Generation and Detection of ASK
Aim:
1. To generate ASK signal using CMOS switches.
2. To demodulate the ASK signal to get back the binary data.

Apparatus required:
 CMOS switches: ICCD4016
 CMOS Inverter: IC CD4049,
 Potentiometer: 10kΩ, Resistors: 1kΩ (02no.s),
 Capacitors: 1µf, 0.22µf,
 Signal generator-2 No.s
 Op-amp µa741.
 ±12v DC supply,
 0 to 5 volts DC supply,
 Diode: IN4001 and
 CRO.

Brief theory:
Amplitude shift keying abbreviated as ASK is a digital modulation scheme where the amplitude of
the sinusoidal carrier wave is switched between two different levels “a1” and “a2” corresponding to the
respective binary symbols “1” and “0”, keeping the frequency and phase constant as shown in the
waveforms for an arbitrary data 1011. If the amplitude “a2” is made equal to zero, the resulting waveform
is termed as “ON-OFF keying” or “OOK” signal.
Ask signal can be generated by using two CMOS switches CD4016, a CMOS inverter CD4049 and
a potentiometer as shown in figure-3.2. When the input binary is “1”, then the first CMOS switch is ON,
the second CMOS is OFF and the output V0(t) will be the carrier wave as it is. When the input is binary
“0”, then the first CMOS switch is OFF, but the second CMOS switch is ON due to inverter. The carrier
signal now passes through the potentiometer on its way to the output. By adjusting the potentiometer, any
desired amplitude for binary “0” can be obtained.
For demodulation of ASK signal, non-coherent detection is used such as an envelope detector as
shown in fig-3.3, followed by a comparator. The envelope detected signal is compared with a dc voltage in
the comparator. If the incoming signal the dc voltage, then the op-amp will be in saturation at +vsat and
other wise it will be at –vsat. Thus the binary waveform can be obtained at the output.

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Figure 3.1 Waveform at different stages of ASK

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Circuit Diagram:

Fig 3.2 ASK Modulator

Fig 3.3 ASK Demodulator

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Fig 3.4 pin diagram of IC741

Fig 3.5 Pin Diagram of IC4016

Fig 3.6 pin diagram of IC4049

Design of Demodulator:
The R1C1 components are chosen that
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1 1
<< R 1C1 <<
fc fm
1
Let R1C1=
10f m
Let R1=1kΩ,
given fm=500 Hz
1
Therefore, C1=
10x500x1x103 = 0.2µ f
Choose C1=0.22µf (standard value)

Procedure:
For ASK modulator:
1) The circuit connections are made as shown in the circuit diagram of figure-3.2.
2) The square wave generator is switched ON and the frequency is adjusted to less than 500 Hz at 6
volts (peak-to-peak).
3) The carrier signal generator is switched ON and the frequency is adjusted to 10 kHz at 5 volts (peak-
to-peak).
4) The ASK output V0 (t) is observed on CRO. By adjusting the potentiometer, the amplitude “a2”
shown in the waveform of fig-3.1 can be varied to get a suitable value.
5) The output waveform is recorded.

For ASK demodulator:

1) The circuit connections are made as shown in the circuit diagram of fig-3.3.
2) The ASK output V0(t) from ASK modulator of fig-3.2, is fed as input to the op-amp peak detector as
shown in fig-3.3.
3) The peak detector along with R1C1 acts as an envelope detector. The waveform at point ‘P’ in fig-3.3
is observed on CRO and then recorded.
4) The final demodulated output at pin 6 of the second op-amp (comparator) is also observed on CRO.
By varying the dc supply voltage, a perfect square wave is obtained on the CRO and is recorded.

Result and conclusion:

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All the waveforms are observed on CRO and it is perfectly matching with the theoretical
waveforms shown in figure 3.1.

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Experiment no.4
Generation and detection of FSK
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Aim:
To generate FSK signal (binary) and demodulate FSK and study the performance.

Theory:
As its name suggests, a frequency shift keyed transmitter has its frequency shifted by the message.
Although there could be more than two frequencies involved in an FSK signal, in this experiment the
message will be a binary bit stream, and so only two frequencies will be involved. The Word “keyed”
suggests that the message is of the “on-off” (mark-space) variety, such as one (historically) generated by a
Morse key, or more likely in the present context, a binary sequence.
Conceptually, and in fact, the transmitter could consist of two oscillators (on frequencies f1 and f2), with
only one being connected to the output at any one time.
Unless there are special relationships between the two oscillator frequencies and the bit clock there will be
abrupt phase discontinuities of the output waveform during transitions of the message.
Bandwidth: Practice is for the tones f1 and f2 to bear special inter-relationships, and to be integer multiples
of the bit rate. This leads to the possibility of continuous phase, which offers advantages, especially with
respect to bandwidth control.
FSK signals can be generated at base band, and transmitted over telephone lines (for example). In this case,
both f1 and f2 would be audio frequencies. Alternatively, this signal could be translated to a higher
frequency. Yet again, it may be generated directly at “carrier‟ frequencies. Other forms of FSK
Minimum-shift keying
Minimum frequency-shift keying or minimum-shift keying (MSK) is a particularly spectrally
efficient form of coherent FSK. In MSK the difference between the higher and lower frequency is identical
to half the bit rate. Consequently, the waveforms used to represent a 0 and a 1 bit differs by exactly half a
carrier period. This is the smallest FSK modulation index that can be chosen such that the waveforms for 0
and 1 are orthogonal. A variant of MSK called GMSK is used in the GSM mobile phone standard. FSK is
commonly used in Caller ID and remote metering applications Audio frequency-shift keying (AFSK) is a
modulation technique by which digital data is represented by changes in the frequency (pitch) of an audio
tone, yielding an encoded signal suitable for transmission via radio or telephone. Normally, the transmitted
audio alternates between two tones: one, the "mark", represents a binary one; the other, the "space",
represents a binary zero.
AFSK differs from regular frequency-shift keying in performing the modulation at base band frequencies.
In radio applications, the AFSK-modulated signal normally is being used to modulate an RF carrier (using
a conventional technique, such as AM or FM) for transmission.

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Circuit diagram:-
Modulator:-

Fig 4.1 Circuit Diagram of FSK Modulator

Demodulator:-

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Fig 4.2 Circuit Diagram of FSK Demodulator

Design:-
LPF-1:
Let
The cut-off frequency=2 kHz
1
=2 kHz
2π RC

Let
C1=0.01μf,
R1=8kΩ.

1 1
RC FILTER << RC <<
fc fm
1
Let RC=
10f m
Let R=10KΩ
1
C=
10f m R
C=0.2 μf or greater.

Procedure:-
 The connections are made as shown in the diagram fig 4.1.
 The modulating signal m(t) is of low frequency (300-500Hz) pulse wave form with amplitude 5v
TTL.
 The two carriers C1(t) =6-10 kHz C2(t) =1-2 kHz
 FSK output is observed on the CRO.
 FSK input is given to demodulator circuit.
 Varying the dc input (0-5v), observe the demodulated waveform.

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(t)

C2

FSKP1

P2

P4

Fig 4.3 Typical Waveform of Modulator and Demodulator

Result:- All the waveforms are observed on CRO and it is perfectly matching with the theoretical
waveforms shown in figure 4.3.

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Experiment no.5
Generation and Detection of PSK
Aim:
To Generate PSK signal and Demodulate PSK signal

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Apparatus Required:
 IC: CD4051, IC741-2no.s
 Diode: OA79
 Resistors: 10kΩ-3no.s, 8.2kΩ, 10kΩ pot.
 Capacitors: 0.01µf, 0.2µf
 Variable power supply(0-30v)
 Regulated power supply ±12v
 Function generators-2n0.s
 CRO.
Theory:

Phase-shift keying (PSK) is a digital modulation scheme that conveys data by changing, or
modulating, the phase of a reference signal (the carrier wave). A co sinusoidal carrier of a fixed amplitude
and frequency is taken. Phase shift keying is obtained using an OP-AMP circuitry and a switch. If
incoming bit is 0, the output is same as the carrier; if it is zero, the output is 900 phase shifted version of
the carrier signal. For demodulation a coherent detector is used. It has 3 parts, a multiplier, and integrator
and decision device. The operation can be analyzed from the circuit.

Any digital modulation scheme uses a finite number of distinct signals to represent digital data.
PSK uses a finite number of phases, each assigned a unique pattern of binary digits. Usually, each phase
encodes an equal number of bits. Each pattern of bits forms the symbol that is represented by the particular
phase. The demodulator, which is designed specifically for the symbol-set used by the modulator,
determines the phase of the received signal and maps it back to the symbol it represents, thus recovering
the original data. This requires the receiver to be able to compare the phase of the received signal to a
reference signal — such a system is termed coherent (and referred to as CPSK).

Alternatively, instead of using the bit patterns to set the phase of the wave, it can instead be used to
change it by a specified amount. The demodulator then determines the changes in the phase of the received
signal rather than the phase itself. Since this scheme depends on the difference between successive phases,
it is termed differential phase-shift keying (DPSK). DPSK can be significantly simpler to implement than
ordinary PSK since there is no need for the demodulator to have a copy of the reference signal to determine
the exact phase of the received signal (it is a non-coherent scheme). In exchange, it produces more
erroneous demodulations. The exact requirements of the particular scenario under consideration determine
which scheme is used.

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Design-Demodulator:-
LPF-1:
Let the cut-off frequency=2 kHz
1
= 2 kHz
2π RC

Let C1=0.01μf,
R1=8kΩ.

1 1
RC FILTER: << RC <<
fc fm
1
Let RC=
10f m
Let R=10KΩ
1
C=
10f m R
C=0.2 μf or greater

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Fig 5.1 Typical waveform of PSK Modulator

Procedure:-
1) Connections are made as shown in the circuit diagram
2) The modulating signal m(t) is of low frequency (say 300Hz-500Hz) pulse waveform with an
amplitude 5v (TTL Output)
3) The carrier c(t) is a sine wave with amplitude less than 10v and frequency around 2kHz at pin no.2
PSK output is verified.
4) PSK input is given to demodulator circuit
5) Adjust DC input to get m’(t), reconstructed input

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Circuit diagram:-
Modulator:-

Fig 5.2 Circuit Diagram of PSK Modulator

Demodulator:-

P
SK I/P

Fig 5.3 Circuit Diagram of FSK Demodulator

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Result:- All the waveforms are observed on CRO and it is perfectly matching with the theoretical
waveforms shown in figure 5.1.

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Experiment no.6

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QPSK Generation and Detection

Aim:- To study the wave forms at different stages of QPSK generation and Detection.

Theory:-
Like DPSK, QPSK is another modulation technique used in digital communication. Sometimes
known as quaternary or quadriphase PSK or 4-PSK, QPSK uses four points on the constellation diagram,
equispaced around a circle, with four phases, QPSK can encode two bits per symbol, shown in the diagram
with gray coding to minimize the BER- twice the rate of BPSK. Analysis shows that this may be used
either to double the data rate compared to a BPSK system while maintaining the bandwidth of the signal or
to maintain the data-rate of BPSK but have the bandwidth needed.
Although QPSK can be viewed as a quaternary modulation. It is easier to see it as two
independently modulated quadrature carriers. With this interpretation, the even (or odd) bits are used to
modulate the in-phase component of the carrier. BPSK is used on both carriers and they can be
independently demodulated.

Fig 6.5 Constellation Diagram of QPSK

As a result, the probability of bit-error for QPSK is the same as for BPSK: The binary data is split
into two streams: even bits and odd bits which independently modulate the in-phase and quadrature-phase
carrier components. In this implementation, the two signals are superimposed, and the resulting signal is
the QPSK signal.

Block Diagram:

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Figure 6.6 Block diagram QPSK Generation

Phase
of QPSK
Input Bits
(in
degrees)
1 0 90
0 0 0
0 1 270
1 1 180

Procedure:-
 Connect the power supply to the module.
 Check the power supply points (+12v,-12v, +5v) using an oscilloscope.
 Make the connections externally using patch chords wherever necessary.
 Select either 600bps or 1.2kbps signal for generating the data pattern.
 Use the DIP switch to select to select a data pattern of 8-bit length ON or off to select “0” or “1” to
make each bit.
 Verify the presence of sin, sin , cos, cos signals using oscilloscope at the appropriate points.
 Observe the waveforms at different stages like; master clock select clock (600bps or 1.2kbps) word
pulse, NRZ data (8-bit messages), splitted odd and even data, the corresponding BPSK waveforms
at the input of adder and the QPSK output and verify them with required waveforms.
 Note that pulse width of the word pulse will be 8333.3μs if the selected clock pulse is 1.2kbps and
1666.66 μs if the selected clock pulse is 600bps.
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 Repeat the experiment for different data streams.

Block Diagram- QPSK Detection:-

Figure 6.7 Block Diagram – QPSK detection.

Procedure:-
 Make the inter connections between QPSK transmitter and Receiver modules.
 Check the power supply points.
 Monitor the transmitter signals.
 Observe the waveforms at different stages of receiver, output of adder, Band pass filter, the two
multipliers, LPFs, Comparators, Bit combiner and Recovered Data.
 It may be observed that the even bit data at the Trans end and receiver end should match similarly
for the bit data. A two channel oscilloscope may be used for observe these data format
simultaneously.
 Adjust the individual potentiometer knobs at the comparator points (level converter) to recover the
odd and even data properly.
 Compare the recovered data with the originally transmitted NRZ (L) data.
 Repeat the experiment for different data streams at the transmitting stage.

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Demonstration of QPSK Waveforms

I/P Bit Stream

1
0.5
0
0 1000 2000 3000 4000 5000 6000 7000 8000
Time
1

Odd Bits
0
-1
0 1000 2000 3000 4000 5000 6000 7000 8000

1
Even Bits

0
-1
0 1000 2000 3000 4000 5000 6000 7000 8000

1
QPSK

0
-1
0 1000 2000 3000 4000 5000 6000 7000 8000

Figure 6.8: QPSK waveform

Result:
All the waveforms are observed on CRO and it is perfectly matching with the theoretical
waveforms shown in figure 6.8.

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Experiment no.7
Generation and Detection of DPSK
Aim:
To study the various steps involved in generating the differential binary signal and differential
phase shift keyed signal at the modulator and recovering the binary signal from the received DPSK signal.

Apparatus:
Cathode ray oscilloscope, Probes, Patch chords

Block Diagram--DPSK Generation:

Figure 6.1 Block diagram of DPSK generation.

Fig 6.2 Encoded Format of input data

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Block Diagram-DPSK Detection:-

Figure 6.3 Block diagram of DPSK detection

Theory:-
DPSK is one of the digital modulation schemes like PSK. Alternative to PSK, instead of using the
bit patterns to set the phase of the wave, it can instead be used to change it by a specified amount. The
demodulator then determines the changes in the phase of the received signal rather than the phase itself.
Since this scheme depends on the difference between successive phases, it is termed as differential phase-
shift keying (DPSK).
For a signal that has been differentially encoded, there is an obvious alternative method of
demodulation. Instead of demodulating as usual and ignoring carrier-phase ambiguity, the phase between
two successive received symbols is compared and used to determine what the data must have been. When
differential encoding is used in this manner, the scheme is known as differential phase-shift keying
(DPSK). Note that this is subtly different to just differentially- encoded PSK since, upon reception, the
received symbols are not decoded one-by-one to constellation points but are instead compared directly to
one another.

Applications:
Owing to PSK’s simplicity, particularly when compared to Quadrature Amplitude Modulation, it is
widely used in existing technologies. The wireless LAN standard, IEEE 802.1 lb-1999, uses a variety of
different PSK’s depending on the data-rate required. At the basic-rate of 1 Mbit/s, it uses DBPSK
(differential BPSK). Bluetooth 2 will use p / 4-DQPSK( at its lower rate (2 Mbit/s) and 8-DPSK at its
higher rate (3 Mbit/s) when the link between the two devices is sufficiently robust. Bluetooth-l modulates
with Gaussian minimum-shift keying, a binary scheme, so either modulation choice in version 2 will yield
a higher data-rate. A similar technology, IEEE 802.15.4 (the wireless standard used by Zig Bee) also relies
on PSK.

Implementation:

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Block diagram shown in Figure 6.1, explains the basic principles behind the implementation of
DPSK. A function generator IC like XR 2206 may be used to produce a sine wave that will act as the
carrier. as well as Master clock-. Since we need two carrier signals that arc 1800 out of phase,
The sine wave produced is passed through an inverter to produce a sine wave form. Both these two
signals will be fed to a 2:1 multiplexer.

The clock divider circuits derive all the system clocks from the master clock. A DIP switch may be
used to generate message data in parallel form that is produced from either a 300 bps or 600 bps signal. By
keeping in ON or OFF position, either a digital ‘l’or a digital ‘0’, a data pattern can be selected. The
parallel data from the DIP switch will be converted into serial data in the data generator block, which will
be in NRZ form. The length of single data bit can be observed at the word pulse point. The NRZ data then
will be fed to an EX-OR gate to encode and produce DPSK data, which will be eventually fed to the
multiplexer as the control signal (act as select signal). Depending up on select data bit, either sine or sine
signal will be transmitted. The DPSK output may be observed at the output of multiplexer.

The information bearing data is X-ORed with the preceding bit, prior to enter the DPSK modulator.
For the first data bit, there is no preceding bit with which to compare it. Therefore an initial bit may be
assumed. The initial bit maybe either ‘0’ or ‘1’. Figure 6.2 shows the encoded data bits for an input data of
10111000 with an assumed initial bit of ‘0’ and the output phases.

Figure 6.3 illustrates the DPSK receiver circuit. It consists of a band pass filter, a multiplier, a low
pass filter, a comparator and a decoder circuit. The incoming DPSK signal is multiplied with the sine wave
carrier signal (received through the transmitter). The resulting signal is passed through the low pass filter
whose output is fed to the comparator. The output of the comparator will be the recovered data which can
be matched to the DPSK data. The recovered DPSK data is applied to a decoder circuit to recover the
original data. A multi turn pot may be used to make easier tuning with the comparator circuit to produce
the required demodulated output.

Figure 6.4 shows the DPSK modulator wave form with respect to a typical data stream and also the
wave forms at different stages of detection. It should be noted that there will actually be some time delay in
the detected data compared to transmitted data which is not shown in the figure.

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Fig 6.4 typical waveforms of modulator and demodulator

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Procedure: - (Generation)
 Connect the power supply to the module.
 Check the power supply points (+12v,-12v, +5v) using an oscilloscope.
 Make the connection externally using patch chords wherever necessary
 Select either 600bps or 300bps for generating the data Pattern
 Use the dip switch to select a data pattern of 8-bit length ON or OFF to select 0 or 1 to make each
bit.
 Verify the presence of sine and sine signal using oscilloscope at the appropriate points
 Observe the waveforms at different stage like master data Clock, select clock (600bps or 300bps),
word pulse, NRZ (8-bit message) and the DPSK output and verify them with required waveforms.
 Note that the pulse width of the word pulse will be 3333.33μs if the selected clock pulse is 300bps
and1666.66 μs if the selected clock pulse is 600bps
 Repeat the experiment for different data streams.

Procedure: - (Detection)
 Make the interconnection between DPSK transmitters and receiver modules.
 Check the power supply points
 Monitor the transmitted signals
 Observe the wave forms at different stages of receiver, output of adder, band pass filter, multiplier,
LPF, comparator, recovered data
 Adjust the potentiometer knobs to recover the data properly.

Result:
All the waveforms are observed on CRO and it is perfectly matching with the theoretical
waveforms shown in figure 6.4.

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Department of Electronics & Communication Engineering, RIT, Bangalore