Ramaiah Institute of Technology

Department of ECE

COURSE DESIGN, DELIVERY AND ASSESSMENT

Semester: VI
Course Code: ECE642
Course Name: COMPUTER ARCHITECTURE

Course Faculty:
Course Coordinator Signature Date
Dr. V. Anandi

Program Coordinator Signature Date

Dr. B.Sujatha

Head of Department (Sign & Date)

 COURSE DESIGN, DELIVERY, AND ASSESSMENT
Course Code and Title: COMPUTER ARCHITECTURE Course Credits:3:0:0
CIE:50 Marks SEE : 100 Marks
Total No of Theory / Tutorial / Lab Hours: 42
Prepared by: Dr. V. Anandi Date: 24/02/2025
Reviewed by: Dr. Raghuram S Date: 24/02/2025

Course Contents:

UNIT – I
Introduction: Combinational and Sequential Logic Circuits, Computer Systems, Technologies
for Building Processors and Memory, Uniprocessors & Multiprocessors
Instruction Sets: Computer Hardware, Representing Instructions in the Computer, Instructions
for Making Decisions, and Sample Instruction Sets.

UNIT – II
Computer Arithmetic: Addition and Subtraction, Multiplication, Division, Floating Point
Parallelism, and Computer Arithmetic
The Processor: Introduction, Logic Design Conventions, Building a Datapath, Overview of
Pipelining, Pipelined Datapath, Hazards, Exceptions

UNIT – III
Memory Hierarchy: Introduction, Memory Technologies, Basics of Caches Measuring and
Improving Cache Performance, Memory Hierarchy, Virtual Machines Virtual Memory, The
ARM Cortex-A53 and Intel Core i7, Memory Hierarchies

UNIT – IV

Parallel Processors from Client to Cloud: Introduction, Parallel Processing Programs, SISD,
MIMD, SIMD, SPMD, Vector, Hardware Multithreading, Multicore and Other Shared Memory
Multiprocessors, Multiprocessor Benchmarks and Performance Models
UNIT – V

Graphics and Computing GPUs: Introduction, GPU System Architectures, Programming

GPUs, Multithreaded Multiprocessor Architecture, Parallel Memory System, Floating-Point
Arithmetic, NVIDIA GeForce 8800 B-46, Mapping Applications to GPUs
Text Books:
1.​ David A Patterson, John L Hennessey, “Computer Organization and Design: The Hardware
Software Interface, The Morgan Kaufmann [RISC-V Edition] 2017.
Reference Books:
 1.​ Kai Hwang and Zu, “Scalable Parallel Computers Architecture” Tata McGraw Hill, 1st
Edition, 2003
2.​ D.A. Patterson, J.L. Hennessy, “Computer Architecture: A quantitative approach” 5th
Edition, Morgan Kaufmann, 2012.
Concept Map:

​
Course contents and Lecture schedule

Lesson No. Topics Duration

UNIT- I
1.​ Introduction: Combinational and Sequential Logic Circuits, Computer Systems 1 Hour
2.​ Technologies for Building Processors and Memory 1 Hour
3.​ Uniprocessors & Multiprocessors 1 Hour
4.​ Instruction Sets: Computer Hardware 1 Hour
5.​ Representing Instructions in the Computer 1 Hour
6.​ Representing Instructions in the Computer (contd) 1 Hour
7.​ Instructions for Making Decisions 1 Hour
8.​ Instructions for Making Decisions (contd) 1 Hour
9.​ Sample Instruction Sets 1 Hour
UNIT- II
10.​ Computer Arithmetic: Addition and Subtraction 1 Hour
11.​ Multiplication, 1 Hour
12.​ Multiplication, Division 1 Hour
13.​ Floating Point Parallelism 1 Hour
14.​ Computer Arithmetic 1 Hour
15.​ The Processor: Introduction, Logic Design Conventions 1 Hour
16.​ Building a Datapath 1 Hour
17.​ Overview of Pipelining, Pipelined Datapath 1 Hour
18.​ Hazards, Exceptions 1 Hour
UNIT- III
19.​ Memory Hierarchy: Introduction, Memory Technologies 1 Hour
20.​ Basics of Caches Measuring 1 Hour
21.​ Basics of Caches Measuring (contd) 1 Hour
22.​ Improving Cache Performance 1 Hour
23.​ Memory Hierarchy 1 Hour
24.​ Virtual Machines 1 Hour
25.​ Virtual Memory 1 Hour
26.​ Virtual Memory(contd) 1 Hour
27.​ The ARM Cortex-A53 and Intel Core i7, Memory Hierarchies 1 Hour
UNIT- IV
28 1 Hour
Parallel Processors from Client to Cloud: Introduction, Parallel Processing Programs

29. SISD, MIMD 1 Hour

30. SIMD, SPMD 1 Hour
31. Vector Processor 1 Hour
32. Hardware Multithreading 1 Hour
33. Multicore and Other Shared Memory Multiprocessors 1 Hour
34. Multiprocessor Benchmarks 1 Hour
35. Performance Models 1 Hour
UNIT –V
36. Graphics and Computing GPUs: Introduction, GPU System Architectures 1 Hour
37. Programming GPUs 1 Hour
38. Multithreaded Multiprocessor Architecture 1 Hour
39. Parallel Memory System 1 Hour
40. Floating-Point Arithmetic 1 Hour
41. NVIDIA GeForce 8800 B-46 1 Hour
42. Mapping Applications to GPUs 1 Hour
CourseOutcomes(COs):
1.​ Discuss contemporary computer architecture issues and techniques. (POs – 1,2,6 PSO - 2)
 2.​ Design basic and intermediate RISC pipelines, including the instruction set, data paths, and
ways of dealing with pipeline hazards. (POs - 2,3,4,12 PSO - 2)
3.​ Understand memory hierarchy design virtual memory, caches, and virtual machines. (POs -
1,2,3,5 PSO - 2)
4.​ Compare properties of shared memory and distributed multiprocessor systems and cache
coherency protocols. (POs - 2,3,6 PSO - 2)
5.​ Explain multithreading architectures, the methods for designing speculative multithreading
processors, and GPU. (POs - 2,3,6 PSO - 2)

Mapping of Course Outcomes with Program Outcomes:

Course Program Outcomes Program Specific

Outcomes Outcomes

1 1 2 3
1 2 3 4 5 6 7 8 9 11 12
0
1 3 2 2 3

2 2 2 2 3

3 2 2 2 3 3

4 3 2 2 3

5 3 2 2 3

Justification of Course Outcomes with Program Outcomes:

1.​ CO-PO Mapping Justification: All COs are mapped to PO2 and PO3, as the
course involves the comparative analysis and understanding of Processor
Architectures.
2.​ CO1 and CO3 are mapped to PO1 as fundamental concepts are discussed.
3.​ CO2 is mapped to PO4 as complex problems can be analyzed for arithmetic
circuits.
When/Where Contributing
Max Evidence
What To whom (Frequency to Course
Assessment Marks Collected
in the course) Outcomes
Internal Twice(Averag
Assessment e of two will 30 1, 2, 3, 4
Blue books
tests be computed)
C
Seminar/Assig
Direct I Once 10 PPTs 4,5
nment
Assessment E Students
QUIZ Once 10 Blue books 1,2,3
Methods
End of course
S
Semester End (Answering Answer
E 1,2,3,4,5
Examination five out of ten 100 scripts
E
questions)
Indirect
End of Course End of the Questionnair
Assessment Students ----- 1,2,3,4,5
Survey course e
Methods
CIE and SEE Evaluation:
Course Assessment and Evaluation:

Bloom’s Seminar Quiz

Sl. No Test 1 (%) Test 2(%) SEE (%)
Category (%) (%)

1 Remember 30 30 20 20 40

2 Understand 30 30 50 30 40

3 Apply 20 20 30 30 10

4 Analyze 20 20 0 20 10

5 Evaluate 0 0 0 0 0

6 Create 0 0 0 0 0

CO1,CO2,
Course Outcomes CO1,CO2,
CO1, CO2 CO3, CO4 CO4,CO5 CO3, CO4,
Mapped CO3,
CO5

TEST-I CO-1,2
TEST-II CO-3,4
Quiz & Seminar CO-1,2,3,4,5

Course Faculty Name Signature with Date

Prepared By Dr. V. Anandi

Reviewed By Dr.Raghuram S