Simulation of Modus Verilog Patterns

Using Cadence Xcelium Simulator

Product Version: Modus Version 19.11, Xcelium Version 19.10
November 2019
Copyright Statement

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 2
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Contents
Purpose ................................................................................................................................................... 4
Audience .................................................................................................................................................. 4
Overview .................................................................................................................................................. 4
Review Modus Pattern Output and “mainsim.v” ...................................................................................... 5
Compile and Simulate Modus Patterns ................................................................................................... 6
Modus Test Pattern Plus (+) Options .................................................................................................... 10
MISCOMPAREDEBUG ...................................................................................................................... 11
Zero-Delay Simulation ........................................................................................................................... 12
SDF Annotation and Simulation ............................................................................................................ 13
Items to Check before Running SDF Simulations .............................................................................. 14
How to Execute SDF Timing via Modus Test Bench ......................................................................... 17
Execute SDF Timing without Using the Modus Test Bench sdf_annotate ......................................... 18
Additional Xcelium Simulator Information .............................................................................................. 20
XMLS and XMHELP .......................................................................................................................... 22
What Will My Simulation Output Look Like? .......................................................................................... 23
Xcelium Profiling .................................................................................................................................... 25
Summary ............................................................................................................................................... 26
Support .................................................................................................................................................. 26
Feedback ............................................................................................................................................... 26

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 3
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Purpose
This application note illustrates how to compile and simulate Modus Verilog patterns using the
Cadence Xcelium simulator.

The application note is based on the “DELAY_SDF_TIMED” lab within the Advanced ATPG RAK
example. It is recommended that you download this Modus Advanced ATPG example and
practice running Xcelium simulation of the patterns.

Audience
All Modus users who want to first verify their test patterns before they are released to a
hardware tester.

Overview
Cadence Modus will produce LBIST (Logic BIST), MBIST (Memory BIST), and ATPG patterns
for both static and delay/transition faults. These patterns rely on test structures within the design
and possibly on the special event sequences defined by the user. Because of this dependence
and the possibility of incorrect event timing, all patterns created by Modus (or any test-
generation tool) should be verified via simulation.

This document defines how you simulate the Modus patterns. The process steps are fairly
simple:

• Compile your device under test (DUT) netlist.

• Compile all the technology libraries.

• Compile the Modus Verilog test bench.

• Elaborate the Modus test bench.

• Simulate the Modus test bench by explicitly referencing a test pattern file(s) via the
+TESTFILE plus argument.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 4
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Review Modus Pattern Output and “mainsim.v”

Modus write_vectors, by default, outputs the Verilog test patterns into the following
directory:

<WORKDIR>/testresults/verilog

The Advanced ATPG RAK run script “runmodus.atpg.sdf.timed.tcl” in the

DELAY_SDF_TIMED lab requests a unique directory for each test mode.
write_vectors \
-testmode COMPRESSION_DECOMP_OPCG \
-language verilog \
-scanformat parallel \
-exportdir
$WORKDIR/testresults/verilog/COMPRESSION_DECOMP_OPCG_PARALLEL

In the export directory, you see the ‘mainsim.v’ file, which is the top-level test bench, and two
pattern files (one for the scan shift confidence patterns and one for the ATPG logic patterns).
VER.COMPRESSION_DECOMP_OPCG.data.logic.ex1.ts2.verilog
VER.COMPRESSION_DECOMP_OPCG.data.scan.ex1.ts1.verilog
VER.COMPRESSION_DECOMP_OPCG.mainsim.v

For some designs, there can be many pattern files. The ‘mainsim.v’ test benches are unique
for the test mode and type of pattern output. NEVER mix and match the mainsim.v files and
the pattern files.

It is for this reason that separate directories are recommended for each unique test mode and
for Parallel and Serial patterns.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 5
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Compile and Simulate Modus Patterns

The mainsim.v file is the top-level module. This test bench will instantiate your DUT, read the
pattern files, and perform the simulation. You must compile and elaborate the following items:

• The mainsim.v file

• Your chip netlist

o Note that if Genus has produced the ATPG data, the netlist will be in your Modus
working directory.

• All of the technology library files, including Memory models

Hint: Look at the build_model command line to find the netlist and technology files. With very
few exceptions, the netlist and technology libraries here are also imported into Xcelium.

As an example, here is a list of files from the Advanced ATPG RAK referenced above.

• VER.COMPRESSION_DECOMP_OPCG.mainsim.v

• dtmf_chip.test_netlist.v

• ./LIBS/atpg/stdcell.v

• ./LIBS/atpg/pllclk_dft.v

• ./LIBS/atpg/pads.v

• ./LIBS/atpg/CDK_R512x16_dft.v

• ./LIBS/atpg/CDK_S128x16_dft.v

• ./LIBS/atpg/CDK_S256x16_dft.v

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 6
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

In the following example, you compile and simulate from within the write_vectors output
directory.

This is zero-delay. An SDF timing annotation example is shown below.

Genus write_atpg will output a single run script similar to this example.

Figure 1: xrun – zero-delay simulation

xrun \
+simvision \
-delay_mode zero -seq_udp_delay 50ps -nospecify \
-timescale 1ns/1ps -override_timescale \
VER.COMPRESSION_DECOMP_OPCG.mainsim.v \
…/../../dtmf_chip.test_netlist.v \
-v ../../../LIBS/verilog/include_libraries_sim.v -incdir ../../../ \
+HEARBEAT +FAILSET \
+TESTFILE1=VER.COMPRESSION_DECOMP_OPCG.data.scan.ex1.ts1.verilog \
+TESTFILE2=VER.COMPRESSION_DECOMP_OPCG.data.logic.ex1.ts2.verilog

A summary of the ‘xrun’ parameters:

a. +simvision is a $test$plusargs command that invokes the dump of waveform

data during simulation. You would only want this for diagnosing simulation
miscompares.

• This is NOT recommended for large designs. You will create too much data.

• Do NOT use this with third-party simulators. This is Cadence proprietary.

b. –delay_mode zero -seq_udp_delay 50ps -nospecify

• This defines zero-delay simulation and tells the simulator to insert a 50ps delay
before updating the output of UDP sequential devices. This delay MUST be greater
than ½ of the timescale accuracy. It avoids zero-delay event order problems.

• -nospecify says to NOT use any of the technology cell ‘specify’ block timing
information. This is assumed when you use -seq_udp_delay.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 7
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

c. -timescale 1ns/1ps -override_timescale

• Set the ‘timescale’ for any module definitions that do not have one. If a module
is missing a timescale, you will get an elaboration error.

• Set ‘override_timescale’ to ensure uniform timing delays throughout the entire

hierarchy. Any mix-and-match of different time units in the design can be toxic.

d. List the mainsim.v, chip Verilog, and technology library files to be compiled.

• -v allows you to reference an ‘include’ file for the libraries.

• The include file in this example references all of the technology files above Figure
1.

e. +HEARTBEAT requests runtime messages. Do this to show that the simulation has
not died. +FAILSET requests that every miscompare produces CPP failure data for
Cadence Diagnostics. This failure data is placed into a ‘FAILSET’ file.

f. Enter one ‘+TESTFILE<int>’ for each pattern file you want to simulate.

• If there is a simulation miscompare, you can rerun the simulation and ask for only
that pattern file.

• If the pattern files are huge, you can ask write_vectors to output a smaller range
of patterns:

write_vectors -testrange

If your simulation is successful, you will see 0 miscompares:

INFO (TVE-204): The total number of good comparing vectors is 3148834

INFO (TVE-203): The total number of miscomparing vectors is 0

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 8
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Figure 2: Three-step process: compile, elaborate, and simulate

xmvlog -log xmvlog.log \
VER.COMPRESSION_DECOMP_OPCG.mainsim.v \
../../../dtmf_chip.test_netlist.v \
-v ../../../LIBS/verilog/include_libraries_sim.v \
-incdir ../../../

xmelab DELAY_SDF_TIMED_COMPRESSION_DECOMP_OPCG -log xmelab.log \

-delay_mode zero \
-seq_udp_delay 50ps -NOSPECIFY \
-timescale 1ns/1ps -override_timescale

xmsim DELAY_SDF_TIMED_COMPRESSION_DECOMP_OPCG -log xsim.log \

+HEARBEAT +FAILSET \
+TESTFILE1=VER.COMPRESSION_DECOMP_OPCG.data.scan.ex1.ts1.verilog \
+TESTFILE2=VER.COMPRESSION_DECOMP_OPCG.data.logic.ex1.ts2.verilog

With this three-step process, you simulate that exact same pattern set as in Figure 1 but use the
individual Xcelium commands.

Notes:

• Always use the same Xcelium version for each command. Different versions are not
compatible.

• Be consistent with ‘-64bit’. You cannot mix and match this parameter.

• If you are running Incisive, and not Xcelium, do not invoke the ‘ncXXX’ commands from
within the Modus environment. The Modus installation has several of these functions
for netlist import. You will create a version mismatch.

• Run zero-delay simulation first to verify that the ATPG pattern event order is correct.
Then, run SDF annotated timing simulation. Do not run unit delay.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 9
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Modus Test Pattern Plus (+) Options

There are several Verilog “plusargs” available within Modus Verilog. All arguments are
case sensitive. The following table lists and explains each of the available
keywords/parameters that may be specified:

Specify this keyword to produce more detailed

+MODUS_DEBUG
runtime messages.
This will limit the number of TVE-660 miscompare
+miscompare_limit=<int>
messages. When the limit is hit, the simulation will stop.
+HEARTBEAT Specify this keyword to produce progress status messages.
Specify this keyword to produce the Chip-Pad-Pattern format
for each miscompare that gets reported during simulation.
+FAILSET The Chip-Pad-Pattern format is required for executing Modus
Diagnostics. Refer to the Diagnostics Reference Modus User
Guide.
Specify an odometer value to indicate the beginning of a
+START_RANGE
pattern range to be simulated.
Specify an odometer value to indicate the end of a pattern
+END_RANGE
range to be simulated.
- The Start-End Range parameters are useful when you
need to re-simulate and isolate on a failing pattern.
+simvision” is a simulation runtime directive to dump all
+simvision signals into an SHM waveform database.
− This is NOT recommended for large designs.
Specify an input data file to NC-Sim. Specify multiple files
+TESTFILEn=filename by incrementing the num string. For example, specify:
+TESTFILE1=<pattern file1> +TESTFILE2=<pattern file2>
This is a simulator directive to produce VCD output from
+vcd your simulation. VCD format is text based and much more
verbose than the proprietary SHM output produced by
+simvision.
This is a diagnostic debug file. This requires a compiler
directive:
+MISCOMPAREDEBUGFILE
xmvlog -define MISCOMPAREDEBUG
This invokes the “$processSimulationDebugFile”
script written by the Cadence Diagnostics team to assist in
analysis for miscompares.

Table: 1

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 10
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

There is an xmvlog compiler directive within the mainsim.v test bench. If you are using a
third-party Verilog simulator, set this to avoid referencing Cadence-only code.

xmvlog -define NOT_NC

MISCOMPAREDEBUG
“xmvlog -define MISCOMPAREDEBUG” turns on special debug code in the
mainsim.v test bench. “xmsim + MISCOMPAREDEBUGFILE <file name>”
executes the code that invokes the “$processSimulationDebugFile” script.

This system task is produced by Cadence and is available within the Modus installation. You
must set the library path to point to this custom script.

LD_LIBRARY_PATH=$Install_Dir/../plilib:$LD_LIBRARY_PATH

This is an enhanced process for debugging simulation miscompares and is beyond the
scope of this application note. For more information, refer to the “Modus Simulation
Miscompare Debugging Tools” documentation.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 11
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Zero-Delay Simulation
This section provides a background on zero-delay simulation.
By default, the timing within your library models comes from the “specify” block. The delay
timing within a specify block is usually set to 1 (essentially, this is unit-delay simulation), but
it can be any number. Thus, if you are not running with SDF timing do NOT have the simulator
use this specify block information (-nospecify). If you are not doing timing simulation, use
zero delay:

-delay_mode zero

There is a potential problem with zero-delay simulation. Many state device modules are
modeled with UDPs. By default, the Cadence simulator solves a UDP by using what is called
a “non-blocking” assignment. This means that in zero-delay mode, the output is updated
immediately without advancing time. This can cause an event order problem where a UDP
output is updated and then used in the same time frame. When this happens, you will get
simulation errors that look like two clock pulses were issued. What you will see is that on a
single clock edge, the data input to one FF will get transferred to its output, propagate to the
next FF, and get captured there too! You avoid this problem with -seq_udp_delay.

Note: The amount of delay you assign via “seq_udp_delay” should be greater than or equal
to 50% of the precision field of the Verilog timescale. For example, if you have “`timescale
1ns/100ps”, you should enter 50ps to 100ps on the “seq_udp_delay” parameter.

For behavior level FF and latch models, “Q = Data_In;” is a blocking assignment and “Q
<= Data_In; “ is a non-blocking assignment. Having a blocking assignment is good. If you
are interested in learning more about Verilog blocking and non-blocking assignments, refer to:

http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

Why not run unit delay?

One large drawback of unit delay is that logic paths can be very long, especially if clock tree
logic is inserted. As a result, an input stimulus can take many time units to propagate the
entire path. Modus, by default, separates input stimulus from clock events by 8 time units.
Paths that have a difference larger than 8 levels can result in events getting out of order such
as a clock edge arriving before the data, glitches, etc.

− Do not use unit-delay simulation.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 12
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

SDF Annotation and Simulation

SDF simulation should be performed on the vectors before the final tapeout to ensure that the
vectors meet timing. Generally, for Static-ATPG, JTAG, and other low-speed vectors,
simulation can be run by annotating just the best-case (BC) timing information. For at-speed
tests like True-Time ATPG and MBIST, simulations should be run with the worst-case (WC)
timing also.

BC SDF is generated based on the lowest temperature and highest voltage corner in the
library. For example, a BC SDF can contain timing data at -40C and 2.3V. Running
simulations with BC will ensure that the design will meet hold time. It is critical that the shift
path of the scan chain meets the hold requirement.

WC SDF ensures that even under the worst-case condition, the device will still meet its timing
requirements. This data is generally generated at high temperature and lowest voltage.

The following table illustrates the terminology used during physical design flow.

SDF/Check Library Temperature Voltage Speed MTM

BC SDF/Hold Fast Lowest (-40C) Highest Don’t care Minimum
WC SDF/Setup Slow Highest (125C) Lowest At-speed Maximum

Table: 2

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 13
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Items to Check before Running SDF Simulations

• Review your SDF file to see if it has best-case (BC), typical (Typ), and worst-case
(WC) timings. This timing data in SDF files come in triplets. There is a triplet for the
rising signal and a triplet for the falling signal. An example is given below:

(IOPATH (posedge CK) Q (BC:Typ:WC) (BC:Typ:WC))

(IOPATH (posedge CK) Q (166:168:171) (164:165:166))

NOTE THAT NOT ALL THREE TIMING VALUES MAY BE IN YOUR SDF.

If a timing value is missing, you cannot request the simulator to use those values. An
example of only WC timing values is as follows:

(IOPATH (posedge CK) Q (::171) (::166))

• Ensure that all the cells in the library have a “specify…endspecify” block. The
specify block is required by the simulator to annotate the timing information from the
SDF. In addition, the timing arcs and conditions specified in the SDF must exist within
the specify block. Two examples are given below:

• If the SDF contains a timing arc from SEL input to Y output of a MUX cell, that
definition must exist within the specify block of your Verilog library model.

• If the SDF timing says that data ‘in’ goes to Q output on posedge of a clock,
that posedge condition must be defined in the specify block.

• Check for “ifdef” statements in your technology library models that may
restrict/control access to code within the specify block. The example below contains
“`ifdef NTC”.

• This requires the user to enter “xrun -define NTC” (xmvlog -define
NTC) in order to invoke/access the Negative Timing Checks within the specify
block.

• Check the timescale entries within your Verilog, especially the library models. Make
sure that the precision portion on each timescale entry is small enough to
accommodate the timing that you will get from the SDF. For example, if your
timescale entry is 1ns/100ps, all timings in your SDF that are smaller than 100ps
will be simulated at 100ps. A 9ps delay becomes a 100ps delay!

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 14
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Figure 3: `ifdef NTC example

`timescale 1ns/1ps
`celldefine
module SDF4CQHVTD1 (SI, D, SE, CP, Q);
input SI, D,
SE, CP;
output Q;
reg notifier;

`ifdef NTC // Reserve for Negative

Timing Checks. wire SI_d, D_d,
SE_d, CP_d ;
pullup
(CDN);
pullup
(SDN);
tsmc_mux (D_i, D_d, SI_d, SE_d);
tsmc_dff (Q_buf, D_i, CP_d, CDN,
SDN, notifier); buf (Q, Q_buf);
not (SD, SE_d);
tsmc_xbuf(xSE,
SE_d, 1'b1);
tsmc_xbuf(xSD, SD,
1'b1);
`else // Reserve for
non NTC. pullup
(CDN);
pullup (SDN);
tsmc_mux (D_i, D, SI, SE);
tsmc_dff (Q_buf, D_i, CP, CDN,
SDN, notifier); buf (Q,
Q_buf);
not (SD, SE);
tsmc_xbuf(xSE,
SE, 1'b1);
tsmc_xbuf(xSD,
SD, 1'b1);
`endif

specify
(posedge CP => (Q +: D))=(0, 0);
$width(posedge CP, 0, 0, notifier);
$width(negedge CP, 0, 0, notifier);
`ifdef NTC // Reserve for NTC.
$setuphold(posedge CP &&& xSE, posedge SI, 0, 0, notifier, , ,CP_d, SI_d);
$setuphold(posedge CP &&& xSD, negedge D, 0, 0, notifier, , ,CP_d, D_d);
$setuphold(posedge CP, negedge SE, 0, 0, notifier, , ,CP_d, SE_d);
$setuphold(posedge CP &&& xSE, negedge SI, 0, 0, notifier, , ,CP_d, SI_d);
$setuphold(posedge CP &&& xSD, posedge D, 0, 0, notifier, , ,CP_d, D_d);
$setuphold(posedge CP, posedge SE, 0, 0, notifier, , ,CP_d, SE_d);
`else // Reserve for non NTC.
$setuphold(posedge CP &&& xSE, posedge SI, 0, 0, notifier);
$setuphold(posedge CP &&& xSD, negedge D, 0, 0, notifier);
$setuphold(posedge CP, negedge SE, 0, 0, notifier);
$setuphold(posedge CP &&& xSE, negedge SI, 0, 0, notifier);
$setuphold(posedge CP &&& xSD, posedge D, 0, 0, notifier);
$setuphold(posedge CP, posedge SE, 0, 0, notifier);
`endif

endspecify
endmodule

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 15
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

IMPORTANT NOTE ON NEGATIVE TIMING CHECKS: The SDF can contain negative
values to represent hold times of the sequential elements. In Figure 3 above, the
default behavior of this library model is to convert these negative hold values to 0. This
becomes more pessimistic checking and can cause the simulations to fail. The use of
“xrun -noneg_tchk” will only print the information about the timing checks. You
should enable Negative Timing Checks (as shown in this example), whenever possible.
For this example, enter the following compiler directive to access Negative Timing
Checks.

xrun -define NTC (xmvlog -define NTC)

• Ensure that the timescale used for the netlists, test benches, and libraries match the
value used in the SDF. Within the Verilog models, you will see a timescale directive.
The first term (1ns) refers to the time unit, and the second term (1ps) is the precision.

`timescale 1ns/1ps

Figure 4: TIMESCALE entry within an SDF

(TIMESCALE
1ns) (CELL
(CELLTYPE “INVHVTD1”)
(INSTANCE
top/core/hier1/hier2/n123)
(DELAY
(ABSOLUTE
(IOPATH I ZN (0.0871:0.0:0.0) (0.0585:0.0:0.0)
)
)
)

In Figure 4 above, the delay through the buffer on rising “I” input is 87.1ps. Because
of the timescale precision of 1ps, the simulator will round this delay to 87ps. On a
falling “I”, the delay will be rounded up to 59ps.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 16
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

How to Execute SDF Timing via Modus Test Bench

There are several ways to annotate SDF data into your simulation snapshot. The Modus
mainsim.v test bench has a placeholder for annotating your SDF timing data.

Figure 5: Modus test bench SDF annotate compiler directives

`timescale 1 ns / 1 ps
module <Modus test bench module name> ;
initial
begin
`ifdef sdf_annotate
`ifdef SDF_Minimum
$sdf_annotate ("default.sdf",dtmf_chip_inst,,"sdf_Min.log","MINIMUM");
`endif
`ifdef SDF_Maximum
$sdf_annotate ("default.sdf",dtmf_chip_inst,,"sdf_Max.log","MAXIMUM");
`endif
`ifdef SDF_Typical
$sdf_annotate ("default.sdf",dtmf_chip_inst,,"sdf_Typ.log","TYPICAL");
`endif
`endif

The expected SDF file name in the above example is “default.sdf”. There is no path as part
of the name. You may have to edit the test bench to provide the correct path and SDF file name.

To execute worst-case SDF annotation using the example above, you would run the following
(See Figure 6):

− Notice that you have removed these parameters:

-delay_mode -seq_udp_delay -nospecify

− Notice that you have requested:

-define sdf_annotate -define SDF_Maximum

o Note that the SDF annotation information will be placed into "sdf_Max.log".

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 17
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Figure 6: xrun with Modus SDF annotate directives

xrun \
+simvision \
-timescale 1ns/1ps -override_timescale \
VER.COMPRESSION_DECOMP_OPCG.mainsim.v \
…/../../dtmf_chip.test_netlist.v \
-v ../../../LIBS/verilog/include_libraries_sim.v -incdir ../../../ \
+HEARBEAT +FAILSET \
+TESTFILE1=VER.COMPRESSION_DECOMP_OPCG.data.scan.ex1.ts1.verilog \
+TESTFILE2=VER.COMPRESSION_DECOMP_OPCG.data.logic.ex1.ts2.verilog \
-define sdf_annotate -define SDF_Maximum

Again, note that the example in this application note is from the Modus Advanced ATPG RAK.
It is using the DELAY_SDF_TIMED lab within the RAK:

− DELAY_SDF_TIMED/testresults/verilog/COMPRESSION_DECOMP_OPCG_PARALLEL

Execute SDF Timing without Using the Modus Test Bench sdf_annotate
Via this method, you do NOT have to edit the test bench or the device netlist to invoke SDF
timing. The process is as follows:

1. Compile the SDF file. The output SDF file will have a “.X” postfix on the name.
xmsdfc –compile –output <compiled sdf file> <input sdf>

The RAK Example: xmsdfc -compile -output default.sdf.x default.sdf

2. Create an SDF command file. This file has an entry for each field on the
$sdf_annotate system task. You only need the first two entries below.

As with the $sdf_annotate task, the SCOPE entry points to the instance within the
hierarchy that matches the module for which the SDF file was created. This is usually
just the DUT instance name within the test bench but can actually be any block within
the hierarchy.

Figure 7: An SDF command file

COMPILED_SDF_FILE=”<compiled sdf file>.X”,

SCOPE=<testbench module name>.<dut instance>,
LOG_FILE=”<any file name>”;

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 18
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

The DELAY_SDF_TIMED lab within the Advanced ATPG RAK example:

Create a file named SDF_COMMAND_FILE.

COMPILED_SDF_FILE="default.sdf.x",
SCOPE=DELAY_SDF_TIMED_COMPRESSION_DECOMP_OPCG.dtmf_chip_inst,
LOG_FILE="My_sdf_annotate.log";

3. Simulate using the “SDF_CMD_FILE” parameter.

// Using the Advanced ATPG RAK example, this is the following command

xrun \
-timescale 1ns/1ps -override_timescale \
VER.COMPRESSION_DECOMP_OPCG.mainsim.v \
../../../dtmf_chip.test_netlist.v \
-v ../../../LIBS/verilog/include_libraries_sim.v \
-incdir ../../../ \
+HEARBEAT +FAILSET \
+TESTFILE1=VER.COMPRESSION_DECOMP_OPCG.data.scan.ex1.ts1.verilog \
+TESTFILE2=VER.COMPRESSION_DECOMP_OPCG.data.logic.ex1.ts2.verilog \
-sdf_cmd_file SDF_COMMAND_FILE -maxdelays

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 19
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Additional Xcelium Simulator Information

1. Use “–log <log file name>” to specify your own simulation log file name.

2. Following are some other useful Xcelium options. These options are given in terms
of “xrun”.

a. –access +rw - Enable access to internal signals for waveform dump. If this is not
included, internal signals are optimized out to improve simulation performance.
The equivalent to this is xmelab -access +r.

b. -compile - Only compile the provided Verilog files and libraries. Do not elaborate
or simulate. This is a good step to try on your initial script.

c. -gateloopwarn – If your simulation goes into infinite loop, rerun NC elaboration

with this option. Then, during simulation, this will break the loop, stop the
simulation, and bring you to the xmsim prompt where you can use the “drivers
–active” command to get the list of active drivers at the time of simulation.

• ncverilog +xmelabargs+gateloopwarn

d. -status – Print the status of xrun during the simulation.

e. –transport_int_delay – Model the logic to have near-infinite switching

speeds. So, all glitches at the inputs are propagated to the output.

f. -64bit – Run the 64-bit version of NC-Verilog. IMPORTANT: Once you invoke
64bit, you must continue to use this parameter on all subsequence NC commands.

g. –profile – Generate a runtime profile of the design.

h. –gui – Invoke the Graphical User Interface.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 20
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

i. -maxdelays | -mindelays | -typdelays - Specify max, min, or typical

delays for simulation. When you annotate SDF data, the SDF file usually contains
min, typical, and max delays. By default, NC will annotate the typical timing values
into your simulation snapshot.

j. –snapshot <snapshot name> - By default, the snapshot name is your test

bench module name. You can override this to provide any descriptive name you
like (such as defining the SDF file you use for minimum, typical, or maximum
timings). Use this to avoid overwriting a snapshot you want to save. The same
parameter for elaboration is xmelab -snapshot <snapshot name>.

k. –r <snapshot name> - Force simulation of the snapshot name provided. Do not

recompile or re-elaborate. The equivalent to this is xmsim <snapshot name> .

l. –seq_udp_delay 10ps - Use this for zero-delay simulation. This will tell NC to
insert a minimal delay onto the output of UPDs. This will help you avoid zero-time
(delta time) simulation event order problems. Use a DELAY VALUE that is
GREATER than ½ of the timescale accuracy.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 21
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

XMLS and XMHELP

Once you have compiled the Modus mainsim.v file, your DUT, and your Verilog libraries,
you can use “xmls” and “xmhelp” to view your results and analyze any problems.

xmls -snap = Ask xmls to list all simulation snapshots that you have created.

If you are not sure which version of a module you are using for simulation, list the source file
for all compiled modules or for a specific module. You can use this information to compare the
model versions imported into Modus.

xmls -source = List the Verilog source for all modules

xmls -source <module name> = Report the source Verilog for a specific module.

If you are getting error or warning messages that are confusing, “xmhelp” may be able to
provide more information. For example, if you want to learn more about an xmelab message,
you can use the following command:

xmhelp <xm command> <xm message label>

Two examples:

xmhelp xmelab SDFNEP

xmhelp xmvlog RECOMP

The resulting additional information about these messages may be helpful.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 22
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

What Will My Simulation Output Look Like?

The Modus test bench includes a number of features to assist the user. Figure 8 below is a
snippet of the output simulation log file. Features shown in Figure 8 are:

• TVE-200 reports the pattern file that is being processed.

• TVE-201 reports that simulation of the pattern file is complete.

• TVE-205 and TVE-206 provide the number of comparisons and the number of
miscompares for EACH input vector test file.

• TVE-203 and TVE-204 provide the total number of comparisons and miscompares
for the entire set of test files.

• TVE-202 messages are from the +HEARTBEAT keyword. For long simulation runs,
having regular heartbeat messages can assure you that your job is still active.

• TVE-650 and TVE-660 are miscompare messages. Bad news! You will need to
debug. Debug the first miscompare message.

The keyword “ write_vectors -includenetnames yes” results in the internal observe

net being output as part of any SO simulation failure message.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 23
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Figure 8: Simulation log file snippet

Following are the simulation results for the DELAY_SDF_TIMED lab within the Advanced ATPG
RAK. An error was manually created in the dtmf_chip netlist. The write_vector output and
the simulation working directory is:

− DELAY_SDF_TIMED/testresults/verilog/COMPRESSION_DECOMP_OPCG_PARALLEL

xrun: 19.03-s004: (c) Copyright 1995-2019 Cadence Design Systems, Inc.

INFO (TVE-200): Reading vector file:

VER.COMPRESSION_DECOMP_OPCG.data.scan.ex1.ts1.verilog

INFO (TVE-201): Simulation complete on vector file:

VER.COMPRESSION_DECOMP_OPCG.data.scan.ex1.ts1.verilog

INFO (TVE-206): The number of good comparing vectors for the file just completed is
21190

INFO (TVE-205): The number of miscomparing vectors for the file just completed is 0

INFO (TVE-200): Reading vector file:

VER.COMPRESSION_DECOMP_OPCG.data.logic.ex1.ts2.verilog

WARNING (TVE-660): SO miscompare at pattern: 1.2.1.37.15.9 at Time: 705820000.00 ps

Expected: 0 Simulated: 1 During Scan Cycle #: 24 Internal Unload =
COMPACTOR.compressor.g_9.g43.__iNsT0.01; Observe Register (OR) = 51;
.....

INFO (TVE-201): Simulation complete on vector file:

VER.COMPRESSION_DECOMP_OPCG.data.logic.ex1.ts2.verilog

INFO (TVE-206): The number of good comparing vectors for the file just completed is
3127638

INFO (TVE-205): The number of miscomparing vectors for the file just completed is 6

INFO (TVE-204): The total number of good comparing vectors is 3148828

INFO (TVE-203): The total number of miscomparing vectors is 6

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 24
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Xcelium Profiling
For large designs, there may be times when you want to profile your Xcelium simulation to
debug infinite loops or see how much memory is being consumed. Below is a brief list of
Xcelium commands that dump various pieces of information and improve performance.

If you are seeing infinite loops (stuck in delta simulation time), try putting a delay on the “@”
wait Verilog entries.

xmvlog –delay_trigger

If you are running Linux, enable multi-core code generation. Set the max number of core to
use.

xmelab -mccodegen -mcmaxcores 4

This is a performance-improvement switch during simulation. This tells NC simulation to do

SHM dumping on a separate process.

xmsim -mcdump

Print out runtime statistics while simulating xmsim -status.

For more information on the available performance and profiling features, see “Frequently
Asked Questions on performance and usage of Xcelium / Incisive profiler” within the
Cadence Support website https://support.cadence.com.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 25
 Simulation of Modus Verilog Patterns Using Cadence Xcelium Simulator

Summary
Throughout this application note, you have used the DELAY_SDF_TIMED lab within the Modus
Advanced ATPG RAK. This RAK was released for Modus version 18.10, but you ran Modus
19.11.

You are invited to download the RAK and use it to learn about Modus ATPG and how to
simulate the test patterns. Search for the following within the Cadence Support pages:

Modus DFT Software Solution – Advanced ATPG Rapid Adoption Kit (RAK) Overview

This RAK is designed as a quick reference to advanced ATPG techniques. The goal is to
provide visibility at advanced ATPG techniques, and provide quick examples and flows for each
topic.

Support
Cadence Support Portal provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to interact
with Cadence Customer Support. Visit https://support.cadence.com.

Feedback
Email comments, questions, and suggestions to [email protected].

Learn more at Cadence Support Portal - https://support.cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 26