IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO.

5, OCTOBER 2003 1381

An Efficient BIST Method for Non-Traditional

Faults of Embedded Memory Arrays
Wen-Ben Jone, Senior Member, IEEE, Der-Chen Huang, and Sunil R. Das, Fellow, IEEE

Abstract—In this work, a built-in self-testing (BIST) method is controller to each small memory array is not economical be-
proposed to detect nontraditional faults of embedded memory ar- cause of the small size of the array. Thus, BIST with a single
rays for a system-on-chip (SoC) design. The nontraditional faults controller is the design goal, and the number of routing signals
include single-cell read-sensitive faults and read coupling faults.
The BIST method can efficiently deal with embedded memory ar- from the BIST controller to all small arrays must be well con-
rays spatially distributed on the entire SoC chip. The concept of trolled to avoid any routing problem. In order to reduce the test
redundant read-write operations is applied to detect all embedded time, all small arrays must be tested simultaneously if power
memory arrays with different sizes simultaneously. The redundant dissipation is tolerable. Consequently, we are looking for a test
operations do not affect the fault coverage of all nontraditional architecture that supports parallel BIST with a limited number
faults discussed in this paper. The method has the advantages of
low hardware overhead, short test time, and high fault coverage of control and data signals. Many parallel memory test methods
for nontraditional memory defects. deal with single large memory array testing by virtually or phys-
ically partitioning a large array into several blocks that are then
Index Terms—Built-in self-testing (BIST), embedded memory
array test, read-sensitive faults, serial interface technique, tested simultaneously [3]–[6]. Several research works concen-
system-on-chip (SoC) testing. trate on concurrently testing several memory arrays that are sep-
arate [7], [2]. In some applications, the array widths are very
large. If word-based test patterns are concurrently routed from
I. INTRODUCTION the BIST controller to each array, the routing area might not
be tolerable. The worst case situation will happen when many
A SYSTEM-ON-A-CHIP (SoC) integrated circuit generally
contains processors, memories, and peripheral interface
devices on a single chip. For example, totally, 32 millions of
arrays are concurrently tested and most arrays are very wide.
The serial interfacing technique was proposed to test several
transistors are fabricated on the PNX8525 chip that includes two embedded memories using a BIST technique, where only two
programmable processor cores and 237 embedded memory ar- serial scan data signals are required for each memory module
rays, some are large while some are small [1]. While SoC de- to access the memory contents [7]. Thus, considerable routing
signs have the advantages of higher performance, lower power area can be saved. This technique is very useful for our appli-
consumption, and smaller area when compared with system-on- cation where many arrays are spatially distributed on the entire
board designs, test development is now identified as a major SoC chip.
bottleneck. This work concentrates on the testing of embedded The cost of testing memories increases rapidly with every
memory arrays, especially for arrays with smaller sizes. Dif- new generation of memory chips [9]. Precise fault modeling
ficulties of testing small embedded memory arrays are 1) the and efficient test design to keep test cost within economically
small size (relatively, when compared with cache) of arrays does acceptable limits are very essential. Recently, inductive fault
not justify the addition of a BIST controller to each array, 2) analysis has been used to experimentally analyze spot defects
these arrays are spatially distributed on the entire chip, and 3) in SRAMs [10]. Based on the memory cell layout, Spice sim-
most arrays are deeply embedded inside the chip and are thus ulation was performed to analyze the behavior of the memory
hard to test using external testers. In this work, we will develop cell by verifying each defect with resistance of zero ohm to
an efficient test method which is able to alleviate these diffi- infinite ohms. The observed fault behaviors were transformed
culties. In [1], each smaller memory array (smaller than 1 k) to functional fault models. The existence of traditional faults
receives a test wrapper, and uses a march algorithm applied have been verified, except that no inversion coupling faults and
through the scan chain. no idempotent coupling faults have been found. Additionally,
It appears that BIST is the only cost-effective solution to solve single-cell read-sensitive faults and read-sensitive coupling
the small-array testing problem. Unfortunately, adding a BIST faults have been observed. Most previous research assumes
that read operation will not cause any fault effect for SRAM,
and the work in [10] has established a new direction for testing
SRAMs.
Manuscript received December 15, 2002; revised April 17, 2003. In [11], [12], an efficient BIST method that is able to con-
W.-B. Jone is with the Department of Electrical and Computer Engineering
and Computer Science, University of Cincinnati, Cincinnati, OH 45221 USA. currently test many embedded memory arrays with different
D.-C. Huang is with the Department of Electronic Engineering, National sizes has been proposed. The new march testing method, called
Chinyi Institute of Technology, Taiping, Taichung, Taiwan, R.O.C. RSMarch, enables all embedded memory arrays to share the
S. R. Das is with the School of Information Technology and Engineering,
University of Ottawa, Ottawa, ON K1N 6N5, Canada. same BIST controller. The basic idea of RSMarch is to tolerate
Digital Object Identifier 10.1109/TIM.2003.818546 some redundant (and thus useless) march operations such that
0018-9456/03$17.00 © 2003 IEEE
1382 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 5, OCTOBER 2003

all memory arrays can share the same data and control signals
from the BIST controller, although these arrays have different
sizes. The beauty of RSMarch is that the redundant operations
do not affect the fault coverage achieved by the nonredundant
operations. Thus, the BIST design for multiple arrays testing
meets the desired test requirements: 1) low hardware overhead
because a scan test architecture and a single BIST controller are
employed, 2) small test time due to the application of parallel
testing, and 3) high fault coverage because the redundant opera-
tions do not mask fault detections. In this research, by adding
very limited number of read operations, we demonstrate that
RSMarch can be extended to detect the nontraditional faults dis-
covered in [10].
Section II provides the related background for the serial in-
terfacing technique, and the traditional and nontraditional fault
models used in this work. The concept of redundant read-write
operations, the proposed test architecture, and the new march
algorithm (RSMarch) are presented in Section III for detecting
the nontraditional faults. In Section IV, the fault coverage of Fig. 1. Shift behavior of serial interfacing.
RSMarch (especially for the nontraditional faults) is analyzed
based on the fault models used. Finally, Section V gives our con-
clusions.

II. BACKGROUND
Many test algorithms have been proposed for SRAMs and
choosing the best solution highly depends on the application.
Fig. 2. SMarch algorithm.
In this work, we must develop a good methodology which is
able to efficiently test many not-too-large memory arrays widely
spread on the entire chip. Particularly, the word width and the read 1 from and write 0 to as shown in Fig. 1. This imme-
word number of each array may differ from the others. Further, diately fills the addressed word with 0. Then, the next c opera-
it is not cost-effective to add a BIST controller for every memory tions read 0 from and write 0 to .
array because of the small array size. In the SoC chip PNX8525, The major difference between SMarch and March C is the
small arrays are tested using a scan-based test method that may way they change the memory contents. SMarch changes the
consume a lot of test time [1]. Since test patterns for memory contents of memory one bit at a time by a pair of read and write
arrays are very regular, as long as we can solve the test pattern operations, while March C changes one word at a time. Another
routing problem for the SoC design, BIST should be the best difference is that SMarch observes one bit at a time but March
way of testing small memory arrays as in the case of testing huge C observes one word for each read/write operation. It is not dif-
memory arrays. These special requirements lead us to consider ficult to verify that the test patterns supported by SMarch are
the serial interfacing technique as a natural solution [7]. With able to detect stuck-at, transition, coupling, and sequential faults
the serial-access technique, only very few data and control lines which occur in the memory array [7]. Since the addressing faults
are required during the entire BIST process. have been successfully mapped to memory cell array faults, they
The basic idea of the serial interfacing technique is to syn- are also detected by the same test patterns [8].
thesize the I/O port of each array as a scan chain, from which In order to support the SMarch algorithm, additional multi-
the test patterns can be provided and memory contents can be plexers are inserted to the I/O port of the memory cell array for
read as shown in Fig. 1. By fixing the addressing lines, succes- the purpose of serial scan as shown in Fig. 3. Therefore, the
sive read/write operations (on a given address) serially scan in added multiplexers and the memory I/O port form a serial scan
the test patterns and scan out the contents of the word as shown chain which allows the BIST circuit to provide one bit of scan-in
in Fig. 1. Based on this test architecture, the SMarch algorithm data , and to observe one bit of scan-out data for each
is used to generate test patterns for the memory cell array [7]. memory read/write operation during testing. More details of the
In fact, SMarch is a march-like test similar to algorithm C pro- serial interfacing technique can be found in [7]. The beauty of
posed by [13], and has six march elements as shown in Fig. 2. the serial interfacing technique lies in its small hardware over-
Here, c denotes the number of bits for each word, and head, specially, only two lines are required in test data appli-
represents test marching from low-order (high-order) words to cation and observation (instead of 2c lines where c is the word
high-order (low-order) words. For example, march element M3 width) for each memory array. Further, the input data line can be
of Fig. 2 contains two groups of input-output patterns, shared by all arrays. Therefore, the number of interconnections
and , for each memory address. By fixing to 0 during between the BIST controller and each memory cell array is com-
the entire march element M3, the first c operations continuously pletely independent of the array size. As will be shown later, this
JONE et al.: EFFICIENT BIST METHOD FOR NON-TRADITIONAL FAULTS 1383

Recently, it has been reported that read operations can also

cause malfunction to memory arrays and this nontraditional
fault model can be divided into the following two cases [10].
1) Single cell read-sensitive faults.
• RDF: a read operation performed to cell changes
the content of , and returns the inverted logic value.
This fault is called a read destructive fault.
• DRDF: a read operation performed to cell changes
the data of , but the operation returns the correct
logic value. This fault is called a deceptive read de-
structive fault.
• IRF: a read operation performed to cell returns the
inverted logic value, while the state of the cell is not
changed. This fault is called an incorrect read fault.
• RRF: a read operation performed to cell returns a
random logic value, while the state of the cell is not
changed. This fault is called a random read fault.
Fig. 3. Serial interface for an embedded array. 2) Read-sensitive coupling faults.
• CFir: a read operation applied to the victim cell
(v-cell) returns an incorrect value, if the aggressor
special feature of the serial interfacing technique results in the cell (a-cell) is in a certain state. The fault is called
greatest benefit for a circuit containing many arrays (especially an incorrect read coupling fault.
when they are widely spread on the chip) with different sizes. • CFrd: a read operation applied to the v-cell causes
Although the test time also increases due to the (serial) shift op- a transition in the v-cell and returns an incorrect
eration, this does not cause any trouble for our application since value, when the a-cell is in a given state. The fault
most memory cell arrays do not contain a tremendous number is called a read destructive coupling fault.
of bits. • CFds: a read or write operation applied to the a-cell
The major component of a small embedded memory array is causes the v-cell to undergo a transition. This fault
the memory cell array which is generally implemented using is called a disturb coupling fault.
SRAM. Thus, an appropriate memory cell array fault model • CFrr: a read operation applied to the v-cell reurns a
must be used to deal with SRAM faults [8]. In conventional random logic value, if the a-cell is in a certain state.
memory test methods, most faults occurring in the read/write The fault is called a random read coupling fault.
logic or address decoder can be mapped to the memory cell
We will show in Section IV that the single-cell read-sensitive
array. In other words, the faults occurring in the read/write
faults and read-sensitive coupling faults discussed above can be
logic or address decoder can be detected by the test algorithms
detected by RSMarch, with very limited number of read oper-
for memory cell array. After fault mapping is done, tests for
ations added. Note that Idempotent coupling fault (CFid) and
read/write logic and address decoder are no longer needed.
Inversion coupling fault (CFin) will not be considered in this re-
Thus, the faults considered by most traditional fault models can
search, since they are not existent according to the experimental
be detailed as follows.
result in [10].
1) Stuck-at fault (SAF): The logic value of a memory cell is
always stuck-at 1 (SA1) or 0 (SA0).
2) Transition fault (TF): A cell fails to undergo a III. PARALLEL EMBEDDED MEMORY ARRAY TESTING
transition (TF ) and/or a transition (TF
). In [11], [12], based on traditional memory fault models, we
3) Coupling fault (CF): In this case, a write operation in one have proposed a BIST scheme to concurrently test embedded
cell can influence the value of another cell , and cell memory arrays of different sizes, i.e., of various word widths
is called the coupling cell whereas cell is called the and word numbers. In a SoC design, the small embedded
coupled cell. As in [8], three types of coupling faults are memory arrays are spatially distributed on the entire chip and
considered below. the number of arrays can be as many as several hundreds. If the
• State coupling fault (CFst): A coupled cell is forced number of BIST control and data lines is not well controlled,
to a certain value if the coupling cell is in a given the hardware overhead might not be acceptable. To accomplish
state . this objective, a new memory BIST scheme has been developed
• Idempotent coupling fault (CFid): A and/or to deal with this problem [11], [12]. The BIST controller
transition in the coupling cell forces a certain designed must be shared by all arrays without losing fault
value in the coupled cell. coverage. Further, the BIST controller design must be entirely
• Inversion coupling fault (CFin): A and/or independent of the number and the size of all arrays embedded
transition in the coupling cell inverts the on the chip. Many factors influence the BIST circuit design for
content of the coupled cell. multiple arrays, and some of which are:
1384 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 5, OCTOBER 2003

(a)

Fig. 4. Proposed BIST architecture for multiple RAMs.

• number of wires allowed to connect the BIST circuit to

arrays;
• similarity of all arrays which share the BIST controller;
• amount of additional logic that is required;
• test time required to finish the testing of all arrays.
We believe that the serial interfacing technique is the best
solution to reduce the number of interconnections between the (b)
Fig. 5. Multiple arrays testing with different word widths. (a) BUF : with
BIST controller and all of the arrays. Otherwise, the number of
test data lines alone will be enormous if the word widths are horizontal redundancy. (b) BUF : without horizontal redundancy.
large. Since most arrays have similar circuit structure except
the memory array sizes, the similarity is high if the array size
problem can be well handled. The single BIST controller de- data (i.e., ) signals from the BIST controller, while the output
sign is rendered the only solution for the purpose of reducing responses (e.g., ) of each array feed to a global MISR. The
hardware overhead. Finally, the parallel testing method must be most significant benefit of this test architecture is that the BIST
used to decrease the test time. Consequently, we are pursuing a controller design is entirely independent of the number of ar-
BIST design that satisfies the above four requirements for mul- rays.
tiple arrays testing. Suppose the maximum word width of all arrays is , and the
From the above discussions, it can be noticed that all arrays word width of a certain array (say ) is only where is
can be concurrently tested if the array size problem can be re- larger than . Each word of will not be wide enough to
solved. Therefore, we proposed a new multiple arrays BIST follow the normal SMarch operations in each march element.
methodology (Fig. 4) which is able to test all arrays simultane- For example, in march element M2 of Fig. 2, after performing
ously without sacrificing fault coverage and hardware overhead times of r0 and w1 operations, each bit of the word under
[11], [12]. The basic idea is to use the maximum word width test in has been exercised and the test outputs/inputs are
(number) of all arrays as the word width (number) for the BIST then changed to r1 and w1 as shown in Fig. 5(a). However,
controller design. Thus, the large-size arrays dominate the en- the memory array with maximum word width still
tire test process, and all arrays receive the same number of input performs times of operations [Fig. 5(b)]. In fact, only
test patterns as well as generate the same number of output re- the output response for has been changed to 1, instead
sponses. That is, all arrays receive the same control and data of 0. However, this is allowable since the global MISR is
signals from the BIST controller. able to correctly compress the test responses, as long as the
Based on this concept, the small-size arrays might receive signature simulation tool takes this output response change
extra test patterns and generate redundant output responses. For into account. Thus, march element M2 for is changed
example, if the first (second) array has word width and word to . The only side-effect of this
number equal 5 and 3 (4 and 6), then the BIST controller will output response change is that redundantly erroneous output
determine the word width as 5 and the word number as 6. Thus, responses might occur. For example, if the last bit of the word
the second array will have one bit test that is not really useful under test has a stuck-at-0 fault, then the error will appear
for each word testing (horizontal redundancy), while all words times, instead of times. Fortunately, this can be
of the first array will be tested twice for each march element handled by MISR, and the problem of inconsistent word width
(vertical redundancy). If these two types of over-testing do not can thus be easily resolved.
result in any side-effect, then the hardware overhead can be min- On the other hand, if has word number that is smaller
imized, the fault coverage can be maintained, and the goal of than the maximum word number of all arrays, then some
parallel testing can be successfully accomplished. The BIST ar- words of will be exercised more than once in each march
chitecture that concurrently tests three arrays is shown in Fig. element. Fig. 6(a) illustrates the case where has been
4. All arrays receive the same control (i.e., read and write) and completely exercised by one marching element, while
JONE et al.: EFFICIENT BIST METHOD FOR NON-TRADITIONAL FAULTS 1385

(a)

(b)
Fig. 6. Multiple arrays testing with different word numbers. (a) BUF : with
first-run scan. (b) BUF : with vertical redundancy.

is still marching midway. Fig. 6(b) shows the case where the
first two words of are exercised twice, when stops
marching. Thus, the redundant operations occurring in
will result in test responses that are not expected by SMarch.
For example, when the first two words of [Fig. 6(b)] are
Fig. 7. RSMarch algorithm.
exercised the second time by march element M2 (Fig. 2), the
test responses are all 1s since the entire has been filled
with 1. However, SMarch expects 0 for the first read opera- the memory array, when the march element finally terminates.
tions. Therefore, SMarch must be modified to accommodate the Following the same example (i.e., ), the first
new test architecture such that test responses of each smaller two words of will be scanned three times when the entire
array can be correctly handled. Let the maximum word width march element is finished. Again, this test session may or may
and word number of all arrays equal and , respectively, and not exist depending on the relationship between and . Later,
assume that there exists a smaller array with word width and we will analyze the march structure of RSMarch and ensure that
word number individually equal and where and the fault coverage of SMarch is still maintained.
. Then the array will be exercised by RSMarch (redundant
SMarch) as shown in Fig. 7. Note that RSMarch for array IV. FAULT COVERAGE ANALYSIS
degenerates to SMarch in the case where has and As described in [7], SMarch can detect the faults most likely
. to occur such as stuck-at fault, transition fault, coupling fault,
The structure of RSMarch is slightly different from SMarch and sequential fault. The redundant test patterns resulting from
in that redundant operations induced by smaller arrays are ex- the march structure of RSMarch might damage the fault cov-
istent. As shown in Fig. 7, the first row of each march element erage that is achieved by SMarch. Next, we will show that RS-
gives the marching operations for the first-run scan of the entire March is able to accomplish the same fault coverage as SMarch.
memory array. It can be found that horizontally redundant oper- After this, we prove that RSMarch can detect all nontraditional
ations might exist, if array width is smaller than . faults described before by adding a very limited number of read
The second row of each march element gives the marching op- operations.
erations by which the entire memory array will be excessively To simplify the following discussions, let march operations
scanned. For example, if has word number equal 4 of the first row (Fig. 7) in march element represented
and there exists an array with the maximum word number equal by , and those of the second and the third rows denoted
10 (i.e., ), then the entire array of will be su- by . Thus, march element contains and , and
perfluously scanned one more time. Note that this test session march operations contained in are all redundant. We
might or might not be existent depending on the relationship emphasize that also has some redundant march operations.
between and . Finally, the third row of each march element For example, the march operations of is
gives the marching operations which excessively scan part of where the first
1386 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 5, OCTOBER 2003

Fig. 8. Horizontal redundancy and fault detection.

and the second are both redundant. The redundant Fig. 9. Vertical redundancy and fault detection.
operations in are denoted by .
Theorem 4.1: RSMarch can detect all faults detected by dant operations do not affect the fault detection capability of the
Smarch. nonredundant operations.
Proof: The basic idea of proving this theorem is to en- • Case 1: causes errors left in the memory array when it
sure that the redundant operations do not affect the fault de- terminates.
tection capability of the nonredundant operations. The discus- If the erroneous cell(s) can be scanned out by then the
sion can be divided into two major categories: the horizontally error(s) will be detected by . However, if the erroneous
redundant operation analysis and the vertically redundant op- cell(s) cannot be exercised by then it (they) will not
eration analysis. To simplify the proof, we concentrate on be masked by either, because there is no bit change
for the horizontal analysis, while the general case (for the hor- during the application of . Thus, the error(s) will be
izontal analysis) can be easily extended. As shown in Fig. 7, detected by other s as the test behavior of SMarch.
contains two separate redundant operations that both equal For example, in the end of operation, each cell of the
. The first (second) redundant operation of is de- memory array is expected to contain 0. However, if there
noted . The following two cases discuss the influ- exists a cell containing 1, then this error will be detected
ence of and to the test behavior. by provided that this cell can be scanned out by
• Case a: terminates with errors left in the word (Fig. 9). Otherwise, the error will be detected by fol-
under test. lowed.
When the nonredundant operations terminate, • Case 2: does not cause errors left in the memory array
the entire word is expected to contain all 1s. Now, if errors when it terminates.
occur, then there exists at least one logic 0 stored some- Since applies the same test patterns used by the last
where in the word (e.g., c1 in Fig. 8). This logic 0 will operations of (i.e., there is no bit change), will not
be read and detected by the following oper- leave errors when it terminates. Thus, follows the
ations. Note that the errors might be detected more than memory contents left by . Again, the redundant oper-
once depending on the relationship between and . Thus, ations do not change the test behavior of Smarch in this
and will not mask the error left by . case.
• Case b: terminates without errors left in the Consequently, it can be ensured that and in-
word under test. duced by RSMarch will not affect the detection capability
When the nonredundant operations terminate, of SMarch.
the entire word contains all 1s (e.g., word in Fig. 8). The
following operation will have the same effect Theorem 4.1 guarantees that the fault coverage achieved by
as since there is no bit change. That is, the re- RSMarch can be maintained as high as that by SMarch. Without
dundant operations do not change the behavior of SMarch this theoretical support, additional counters and control circuits
in this case. Note that might terminate with er- will be required to terminate the march operations for smaller
rors left in other memory words because of coupling faults arrays when test patterns of large arrays are still marching. This
(e.g., and in Fig. 8). However, redundant opera- would significantly increase the design efforts and the difficul-
tions will not mask them since there is no bit ties of the BIST controller.
change (after the coupling faults have been triggered) in The following discussion concentrates on detecting read-sen-
the word under test (when is applied). Thus, sitive faults that occur to each embedded memory array, without
the coupling errors will be detected by or or by redundant operations in each march element. We will show that
other s. RSMarch can detect all CFds, CFir, and CFrd faults without
adding any extra test patterns. It should be noted that detection
The following discussions deal with vertically redundant op- of CFst by RSMarch has been proved by Theorem 4.1. How-
erations, and the basic idea is to prove that the vertically redun- ever, a very limited number of test patterns must be added to
JONE et al.: EFFICIENT BIST METHOD FOR NON-TRADITIONAL FAULTS 1387

RSMarch to detect single-cell read-sensitive faults. To simplify these extra read operations does not affect the fault coverage of
the following discussion, we use the fault primitive (FP) nota- all other faults mentioned above.
tion presented in [10]. For a single-cell read-sensitive fault, it Theorem 4.7: RSMarch can detect all deceptive read de-
can be represented by where S describes the sensi- structive (DRDF) faults (by repeating each read operation in
tizing operation or state, F the value of the faulty cell, and R the M2) if there exist no redundant operations.
logic value that appears at the output. For a read-couping fault, Proof: DRDF faults can be divided into two cases:
we use to describe the fault behavior where Sa and . Under the assumption of no redundant
(Sv) describes the sensitizing operation or state of the aggressor operation, M2 can be written as . Assume
(victim) cell. cell c1 has a DRDF fault . The first r0 operation will
Theorem 4.2: RSMarch can detect all incorrect read cou- sensitize the fault, and the second (immediately following) r0
pling (CFir) faults if there exist no redundant operations. operation will observe the fault. Without the addition of another
Proof: Let c1 (c2) be the a-cell (v-cell) of a CFir fault and r0 operation, the w1 operation which immediately follows
c1 has a smaller address than c2. M2 can detect the r0 operation will destroy the fault effect. Similarly, if c1
by the test patterns of , and by those of contains a DRDF fault , then the first r1 operation will
. Similarly, M3 can detect by the test pat- sensitize the fault while the second r1 operation will observe
terns of , and by those of . Again, the fault effect.
let c1 (c2) be the a-cell (v-cell) of a CFir fault but c1 has a larger The following discussions deal with the relationship between
address than c2. M4 can detect by the test patterns redundant operations and read-sensitive faults.
of , and by those of . Similarly, Theorem 4.8: Redundant operations of RSMarch will not af-
M5 can detect by the test patterns of , and fect the detection of single-cell read-sensitive faults.
by those of . Proof: First, we prove that horizontally redundant
Theorem 4.3: RSMarch can detect all read destructive cou- read/write operations do not affect the detection of single-cell
pling (CFrd) faults if there exist no redundant operations. read-sensitive faults by RSMarch. As in Theorem 4.1, the
Proof: The proof is similar to that of Theorem 4.2, and is discussion can be further divided into two cases.
thus omitted here.
• Case 1: The cell under consideration does not contain a
Theorem 4.4: RSMarch can detect all disturb coupling
faulty value before the horizontally redundant operations
(CFds) faults if there exist no redundant operations.
are applied. In the case of RDF occurring at cell
Proof: Let c1 (c2) be the a-cell (v-cell) of a CFds
c1, the first set of redundant operations in M1
fault and c1 has a smaller address than c2. M2 can detect
will only cause the early detection of the RDF fault at c1,
- - , and - CFds faults, while
while the second set of redundant operations in
M3 can detect - - , and - CFds
M1 will just cause more errors observed by the MISR.
faults. Fault - will be sensitized by M4 and observed
by M5, Similarly, Fault - will be sensitized by M5 Further, the state (which might be faulty) of the word
and observed by M6. Then, let c1 (c2) be the a-cell (v-cell) of containing cell c1 will not be affected by the horizon-
a CFds fault but c1 has a larger address than c2. M4 can detect tally redundant operations. Thus, the horizontally redun-
- - , and - CFds faults, while dant operations will not cause any side effect for the next
M5 can detect - - , and - CFds march element (M2). The horizontally redundant behavior
faults. Fault - will be sensitized by M2 and observed of other march elements to RDF can be investi-
by M3. Similarly, Fault - will be sensitized by M1 gated in the same manner. Further, similar discussion can
and observed by M2. be applied to RDF and IRF. In the case of DRDF
Theorem 4.5: RSMarch can detect all read destructive (RDF) fault at c1, no horizontally redundant operations
faults if there exist no redundant operations. exist since c1 has been written logic 1 due to the w1 op-
Proof: Basically, RDF faults can be divided into two eration of in M2. However, DRDF
cases: and . It can be easily verified that will receive horizontally redundant operations due to the
can be detected by M1, while can be excessive operations of . Again,
detected by M2. this will just cause more erroneous outputs observed by
Theorem 4.6: RSMarch can detect all incorrect read (IRF) the MISR.
faults if there exist no redundant operations. • Case 2: The cell under consideration contains a faulty
Proof: IRF can be divided into two cases: and value before the horizontally redundant operations are ap-
where the former case can be detected by M1, while plied. In the case of RDF occurring at cell c1, the
the latter can be detected by M2. fault will not be sensitized by the horizontally redundant
In order to detect a DRDF, M2 must be enhanced operations , since c1 contains the erroneous
by repeating each read operation one more time: value (1). But, the faulty value already stored in c1 will
. The be sensitized by the horizontally redundant operations and
second and third march sub-elements of M2 are changed observed by the MISR. Then, cell c1 is written logic 0 and
accordingly. Thus, the first r0 (r1) operation will sensitize the the discussion for RDF in Case 1 follows. Thus,
DRDF fault, while the second r0 (r1) will more erroneous outputs will be detected by M1, but the
observe the fault effect. We emphasize that the addition of state of the word containing cell c1 will not be affected by
1388 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 5, OCTOBER 2003

the horizontally redundant operations. The same discus- • Case 2: Vertically redundant operations. Again, in M2, the
sion can be applied to other fault types. vertically redundant operations will not change the state
of the memory array, though CFir fault will
Next, we prove that vertically redundant operations do not
be excessively sensitized and observed.
affect the detection of single-cell read-sensitive faults by RS-
Theorem 4.10: Redundant operations of RSMarch will not
March. Again, the discussion can be further divided into two
affect the detection of read destructive coupling faults (CFrd).
cases.
Proof: This theorem can be proved as that in Theorem 4.9
• Case 3: The cell under consideration does not contain a and is thus omitted.
faulty value before the vertically redundant operations are Theorem 4.11: Redundant operations of RSMarch will not
applied. Assume we have cell c1 with RDF . The affect the detection of disturb read-coupling faults (CFds).
fault will be repeatedly (depending on the number of times Proof: Again, march element M2 is used to illustrate the
that vertically redundant operations are applied to c1) sen- proof. Assume there exists a CFds fault, the aggressor (victim)
sitized by vertically redundant operations of M1 and de- cell is c1 (c2), and the address of c1 is smaller than that of c2.
tected by the MISR. The vertically redundant behavior of • Case 1: Horizontally redundant operations. M2 is used
other march elements to RDF can be investigated to detect CFds - - , and - .
in the same manner. Further, the word state will not be af- Since the horizontally redundant operations at c1 contain
fected by the vertically redundant operations. The same only (r1w1), it is impossible to sensitize CFds -
discussion can be applied to RDF and IRF faults. excessively. Further, CFds - has been sensitize
For DRDF , no vertically redundant operations by the first set of (nonredundant) operations at
exist, since the entire memory array has been set to logic 1 c1 (if the fault really exists), so it will not be sensitized
(before the redundant operations of M2 are applied). How- again by the redundant operations . However,
ever, more errors caused by DRDF will be fed CFds - will be sensitized earlier by the redun-
into the MISR by the vertically redundant operations of dant operations at c1. Once it has been sen-
M2. sitized, the following operations at c1 will not
• Case 4: The cell under consideration contains a faulty excessively sensitize this fault, and the word state is not
value before the vertically redundant operations are ap- changed in the existence of the redundant operations ei-
plied. Assume we have cell c1 with RDF , but ther. Other CFds faults under different march elements can
cell c1 contains logic 1 that was left by previous opera- be discussed similarly
tions. Obviously, the fault effect at c1 will be sensitized • Case 2: Vertically redundant operations. The vertically
and detected by the vertically redundant operations of M1. redundant operations contain only opera-
Then, logic 0 will be written into c1 and the discussion in tions. Since the entire array contains logic 1 before
Case 3 follows. Note that cell c1 might be exercised by the vertically redundant operations are applied, CFds
more than one round of vertically redundant operations, - - , and - will never be
and the discussion can be extended similarly. Other fault sensitized again. Further, the array state is not changed.
types can be discussed in the same way.
Theorem 4.9: Redundant operations of RSMarch will not af- V. CONCLUSION
fect the detection of incorrect read-coupling faults (CFir). In this paper, we have presented an efficient BIST method
Proof: March element M2 is used to illustrate the proof that is able to concurrently test multiple arrays with different
and other march elements can be discussed similarly. Assume sizes for nontraditional fault models. By tolerating some redun-
there exists a CFir fault, the aggressor (victim) cell is c1 (c2), dant march operations existent, the concept of RSMarch has
and the address of c1 is smaller than that of c2. Here, we just been proposed to deal with the difficulty of testing a set of small
concentrate on CFir fault , while other faults can be arrays. The new method has the advantages of low hardware
discussed similarly. overhead, short test application time, and high fault coverage.
• Case 1: Horizontally redundant operations. In M2, the hor- The benefit of low hardware overhead comes from 1) only one
izontally redundant operations at the aggressor line is required for sending test bit patterns to all arrays, 2) the
cell c1 will not change the state of c1. Thus, the horizon- single BIST controller can be shared by all arrays, 3) each array
tally redundant operations at c1 do not result in any ef- only requires one more MISR bit for test response analysis,
fect for the CFir fault. Further, the state of the word (wd1) and 4) no comparison circuits are required for different array
containing cell c1 is not changed either. When the victim sizes due to the concept of allowing redundant operations. The
cell c2 is exercised by the horizontally redundant opera- advantage of short test application time is due to the strategy of
tion , CFir fault will be sensitized sev- testing all arrays in parallel, without sacrificing the fault cov-
eral more times and compressed into the MISR. But, the erage. Another important property of the proposed method is its
word state of wd2 (which contains c2 and might be faulty) power in dealing with nontraditional faults, such as single-cell
will not be changed. Thus, though the aggressor and victim read-sensitive faults and read-sensitive coupling faults. This
cells are excessively exercised by the horizontally redun- can be easily achieved by adding only repeated read operations
dant operations, the detection of CFir fault at cell c2 is not in M2, and the extra test time and test hardware are both very
affected at all. limited. The proposed method can be efficiently applied to any
JONE et al.: EFFICIENT BIST METHOD FOR NON-TRADITIONAL FAULTS 1389

SoC chip that contains a large number of spatially distributed [12] , “An efficient BIST method for distributed small buffers,” IEEE
embedded arrays. Trans. VLSI Syst., vol. 10, no. 4, pp. 512–515, Aug. 2002.
[13] M. Marinescu, “Simple and efficient algorithms for functional RAM
Embedded memories have been widely used in ASICs, SoCs, testing,” in Proc. Int. Test Conf., 1982, pp. 236–239.
and custom ICs, especially, smaller memories can help proces- [14] International Technology Roadmap for Semiconductors (2000). [On-
sors gain performance. It has been predicted by 2000 ITRS De- line]. Available: http://www.public.itrs.net

sign Roadmap Update that embedded memories might occupy

71% (90%) of SoC chip area in 2005 (2011) [14]. We believe
that BIST based on the serial interfacing technique should be
a natural way of solution, due to the minimization of test data
and address routing. Assume we have a SoC with memory ar-
rays, and the average word width of the arrays is bits. Without
using the scan-based BIST method, the number of routing lines
is since (on an average) each array requires lines for
Wen-Ben Jone (S’85–M’88–SM’01) was born in
routing test data and test responses. However, only lines Taipei, Taiwan, R.O.C. He received the B.S. degree
are required for the proposed method, since test data can be in computer science and the M.S. degree in computer
engineering from National Chiao-Tung University,
broadcast by one line while each array requires one more line for Hsinchu, Taiwan, in 1979 and 1981, respectively,
routing the test responses to the MISR. For example, if and and the Ph.D. degree in computer engineering and
equal 100 and 50, respectively, the number of routing lines will science from Case Western Reserve University,
Cleveland, OH, in 1987.
be 10 000 for a BIST method without using a scan-based tech- In 1987, he joined the Department of Computer
nology. However, our method just requires 101 routing lines. Science at the New Mexico Institute of Mining and
This is a great saving of routing hardware overhead. In fact, our Technology, Socorro, NM, where he was promoted
as an Associate Professor in 1992. From 1993 to 2000, he was with the De-
method uses only of the routing space which is required partment of Computer Engineering and Information Science, National Chung-
by a nonscan-based BIST method. Cheng University, Chiayi, Taiwan. He was a Visiting Research Fellow with the
Department of Computer Science and Engineering, the Chinese University of
Hong-Kong, in 1997. Since 2001, he has been with the Department of Elec-
trical and Computer Engineering and Computer Science, University of Cincin-
nati, OH. He was a Visiting Scholar with the Institute of Information Science,
Academia Sinica, Taiwan, in 2002. His research interests include VLSI de-
sign for testability, built-in self-testing, memory testing, high-performance cir-
cuit testing, MEMS testing and repairing, and low-power circuit design. He
has served as a reviewer in these research areas in various technical journals
and conferences. He has published more than 100 papers and holds one U.S.
patent. He has served on the program committee of VLSI Design/CAD Sympo-
sium (1993–1997, Taiwan), the program committee of the 1995, 1996, and 2000
Asian Test Conference, the 1995–1998 Asia and South Pacific Design Automa-
REFERENCES tion Conference, the 1998 International Conference on Chip Technology, the
2000 International Symposium on Defect and Fault Tolerance in VLSI Systems,
the 2002 and 2003 Great Lake Symposium on VLSI, and he was the General
Chair of the 1998 VLSI Design/CAD Symposium.
[1] B. Vermeulen, S. Oostdijk, and F. Bouwman, “Test and debug strategy Dr. Jone is listed in the Marquis Who’s Who in the World (15th Edition, 1998,
of the PNX8525 nexperia digital video platform system chip,” in Proc. 2001). He received the Best Thesis Award from The Chinese Institute of Elec-
Int. Test Conf., 2001, pp. 121–130. trical Engineering (Republic of China), in 1981. He is a corecipient of the 2003
[2] L. Ternullo, R. D. Adams, J. Connor, and G. S. Koch, “Deterministic IEEE Donald G. Fink Prize Paper Award. He is a member of the IEEE Com-
self-test of a high-speed embedded memory and logic processor sub- puter Society Test Technology Technical Committee.
system,” in Proc. Int. Test Conf., 1995, pp. 33–44.
[3] P. Mazumder and J. K. Patel, “Parallel testing for pattern-sensitive faults
in semiconductor random-access memories,” IEEE Trans. Comput., vol.
C-38, no. 3, pp. 394–407, Mar. 1989.
[4] T. Shridhar, “A new parallel test approach for large memories,” IEEE
Design Test Comput., vol. 3, pp. 15–22, Aug. 1986.
[5] Y. Morooka, S. Mori, M. Miyamoto, and M. Yamada, “An address mask-
able parallel testing for ultra high density drams,” in Proc. Int. Test Conf.,
1991, pp. 556–563.
[6] J. C. Lee, Y. S. Kang, and S. Kang, “A parallel test algorithm for pattern
sensitive faults in semiconductor random access memories,” in Proc. Int.
Symp. Circuits and Systems, 1997, pp. 2721–2724.
[7] B. N. Dostie, A. Silburt, and V. K. Agarawal, “Serial interfacing tech- Der-Chen Huang was born in Miaoli, Taiwan, R.O.C., in 1960. He received
nique for embedded memory testing,” IEEE Design Test Comput., pp. the B.S. degree in electrical engineering from Feng-Chia University, Taiwan,
52–63, Apr. 1990. in 1983, the M.S. degree in computer engineering from the Florida Institute of
[8] A. J. van de Goor, Testing Semiconductor Memories: Theory and Prac- Technology in 1991, and the Ph.D. degree in computer engineering from the
tice. New York: Wiley, 1991. Department of Computer Science and Information Engineering, Chung-Cheng
[9] M. Inoue et al., “A new test evaluation chip for lower cost memory tests,” University, Chiayi, Taiwan, in 2000.
IEEE Design Test Comput., pp. 15–19, Mar. 1993. From 1983 to 1989, he was a Design Engineer with the Computer Communi-
[10] S. Hamdioui and A. J. van de Goor, “An experimental analysis of spot cation Laboratory (CCL) and Chung-Shan Institute and Science of Technology
defects in SRAMs: Realistic fault models and tests,” in Proc. Asian Test (CSIST) when he was assigned to a partnership project at General Dynamics,
Symp., 2000, pp. 131–138. Fort Worth, TX. Currently, he is an Associate Professor in the Electronic En-
[11] W. B. Jone, D. C. Huang, S. C. Wu, and K. J. Lee, “An efficient BIST gineering Department, Chinyi Institute of Technology, Taichung, Taiwan. His
method for small buffers,” Proc. IEEE VLSI Test Symp., pp. 246–251, research interests include VLSI design for testability and diagnosis, memory
1999. test, built-in self-test, and system-on-chip design and test.
1390 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 5, OCTOBER 2003

Sunil R. Das (M’70–SM’90–F’94) received the Dr. Das is a Member of the Association for Computing Machinery (ACM). He
B.Sc. (Honors) degree in physics and the M.Sc. was elected one of the delegates of the prestigious Good People, Good Deeds of
(Tech.) and Ph.D. degrees in radiophysics and the Republic of China in 1981 in recognition for his outstanding contributions
electronics from the University of Calcutta, Calcutta, in the field of research and education. He is listed in the Marquis Who’s Who
West Bengal, India. Biographical Directory of the Computer Graphics Industry, Chicago, IL (First
He is a Professor of Electrical and Computer En- Edition, 1984). He is the 1996 recipient of the IEEE Computer Society’s highly
gineering at the School of Information Technology esteemed Technical Achievement Award for his pioneering contributions in the
and Engineering, University of Ottawa, Ottawa, fields of switching theory and modern digital design, digital circuits testing,
ON, Canada. He previously held academic and microarchitecture and microprogram optimization, and combinatorics and
research positions with the Department of Electrical graph theory. He is also the 1997 recipient of the IEEE Computer Society’s
Engineering and Computer Sciences, Computer Meritorious Service Award for excellent service contributions to the IEEE
Science Division, University of California, Berkeley, the Center for Reliable TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS AND
Computing (CRC), Computer Systems Laboratory, Department of Electrical THE SOCIETY, and was elected a Fellow of the Society for Design and Process
Engineering, Stanford University, Stanford, CA (on sabbatical leave), the Science in 1998 for his accomplishments in integration of disciplines, theories
Institute of Computer Engineering, National Chiao Tung University, Hsinchu, and methodologies, development of scientific principles and methods for
Taiwan, R.O.C., and the Center of Advanced Study (CAS), Institute of Radio- design and process science as applied to traditional disciplines of engineering,
physics and Electronics, University of Calcutta. He has published extensibly industrial leadership and innovation, and educational leadership and creativity.
in the areas of switching and automata theory, digital logic design, threshold He became a Golden Core Member of the IEEE Computer Society in 1998
logic, fault-tolerant computing, microprogramming and microarchitecture, in recognition for being one of the distinguished core of dedicated volunteers
microcode optimization, applied theory of graphs, and combinatorics. He and staff whose leadership and services made the IEEE Computer Society the
has edited, jointly with P. K. Srimani, a book entitled Distributed Mutual world’s preeminent association of computing professionals. He is the recipient
Exclusion Algorithms (Los Alamitos, CA: IEEE Computer Society Press, of the IEEE Circuit and Systems Society’s Certificates of Appreciation for
1992). He is coauthor, with C. L. Sheng, of a text on digital logic design, services rendered as Associate Editor, IEEE TRANSACTIONS ON VERY LARGE
being published by Ablex Publishing Corporation. He is an Associate Editor of SCALE INTEGRATION (VLSI) SYSTEMS, during 1995–1996 and 1997–1998,
the International Journal of Parallel and Distributed Systems and Networks and of the IEEE Computer Society’s Certificates of Appreciation for services
published by Acta Press, Calgary, AB, Canada, and a member of the Editorial rendered to the Society as Member of the Society’s Fellow Evaluation
Board and a Regional Editor for Canada of VLSI Design: An International Committee, once in 1998 and again in 1999. He served as a Member of the
Journal of Custom-Chip Design, Simulation and Testing published by Gordon IEEE Computer Society’s Fellow Evaluation Committee for 2001, as well. He
and Breach Science Publishers, Inc., NY. He is a former Associate Editor of was elected a Fellow of the Canadian Academy of Engineering in 2002 for
the SIGDA Newsletter, the publication of the ACM Special Interest Group on pioneering contributions to computer engineering research—specifically in
Design Automation, and a former Associate Editor of the International Journal the fields of switching theory and computer design, fault-tolerant computing,
of Computer Aided VLSI Design published by Ablex Publishing Corporation, microarchitecture and microprtogram optimization, and to some problem
Norwood, NJ. He was also Guest Editor of the International Journal of areas in applied theory of graphs and combinatorics. He is the recipient of the
Computer Aided VLSI Design (September 1991) as well as VLSI Design: An prestigious Rudolph Christian Karl Diesel Best Paper Award of the Society
International Journal of Custom-Chip Design, Simulation and Testing for the for Design and Process Science in recognition of the excellence of their paper
March 1993, September 1996, and December 2001 Special Issues on VLSI presented at the Fifth Biennial World Conference on Integrated Design and
Testing. Process Technology held in Dallas, TX, June 4–8, 2000. He is also the co-re-
Dr. Das has served as the Managing Editor of the IEEE VLSI Technical Bul- cipient of the IEEE’s esteemed Donald G. Fink Prize Paper Award for 2003 for
letin, a publication of the IEEE Computer Society Technical Committee (TC) a paper published in the December 2001 issue of the IEEE TRANSACTIONS ON
on VLSI, and also as an Executive Committee Member of the IEEE Computer INSTRUMENTATION AND MEASUREMENT. He was elected a Fellow of the IEEE
Society Technical Committee (TC) on VLSI. He is currently an Associate Editor in 1994 for contributions to switching theory and computer design.
of the IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS (now of Part
A, Part B, and Part C) and the IEEE TRANSACTIONS ON INSTRUMENTATION AND
MEASUREMENT. He is a former Administrative Committee (ADCOM) Member
of the IEEE Systems, Man, and Cybernetics Society and a former Associate Ed-
itor of the IEEE TRANSACTIONS ON VLSI SYSTEMS (for two consecutive terms).
He has served on the Technical Program Committees and Organizing Commit-
tees of many IEEE and non-IEEE International Conferences, Symposia, and
Workshops, and also acted as Session Organizer, Session Chair, and Panelist.
He also served as the Co-Chair of the IEEE Computer Society Students Ac-
tivities Committee from Region 7 (Canada). He was the Associate Guest Ed-
itor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issues on Micro-
electronic Systems (Third and Fourth Special Issues) and Guest Editor, jointly
with Rochit Rajsuman, for a Special Section of the IEEE TRANSACTIONS ON
INSTRUMENTATION AND MEASUREMENT on Innovations in VLSI Automatic Test
Equipment, October 2003.