EUROCON 2007 The International Conference on “Computer as a Tool” Warsaw, September 9-12

Improved Accuracy Function Generator

Circuit for Analog Signal Processing
Cosmin Popa
Faculty of Electronics, Telecommunications and Information Technology
University Politehnica of Bucharest, Bucharest, Romania, e-mail: [email protected]

Abstract— A new current-mode function generator each desired function derived from them, using a n − th
circuit will be presented, having a much smaller order limited polynomial series expansion. Considering a
complexity per function with respect to the previous
continuous function f (x ) , its Taylor series expansion
reported similar works. The circuit allows to compute an
important number of mathematical functions using their around x = 0 , for x << 1 could be expressed as:
n − th order limited polynomial series expansion. The
approximation error could be strongly decreased by
f (1) f ( 2)
increasing the number of terms considered in the previous x =0 x =0
expansion. The selection of the active function is digitally f ( x) = f (0 ) + x+ x 2 + ... =
1! 2!
made, the main part of the function generator being
common for all the computed functions. The circuit core, f (1) f (2 )
the current squarer circuit, will be analyzed in six possible x =0 x =0
= f (0 ) + g 1 ( x) + g 2 ( x ) + ... . (1)
implementations, using exclusively MOS transistors 1! 2!
working in the saturation region for improving the circuit
frequency response. In order to reduce the circuit The error resulted by using this approximation will be
complexity, classical MOS active devices will be replaced proportional with the number of terms neglected in the
by a FGMOS (Floating Gate MOS) transistor. A very
previous expansion.
important advantage of the proposed function generator
circuit is the independence of the computed function on The implementation in CMOS technology of the
the technological parameters. The circuit is implemented elementary function generators g k (x) is based on a
in 0.35 µm CMOS technology, the SPICE simulations
confirming the theoretical estimated results.
single original block, a CMOS current squarer.
In order to improve the circuit frequency response, only
Keywords—function generator, computing error, strong-inverted MOS devices must be used (the weak
complexity, Taylor expansion
inversion operation of the MOS transistor is not a proper
choice for high-speed CMOS circuits because of the very
I. INTRODUCTION small currents available for charging and discharging the
device capacitances). An alternative choice is to replace
A very important goal in analog designs is the VLSI
the classical MOS transistors by FGMOS (Floating Gate
implementation in CMOS technology of the
MOS) active devices, allowing an important reducing of
mathematical functions, having the most important
the circuit complexity.
advantage of speeding-up the designed circuits and
finding many applications in analog signal processing. The errors introduced by the technological parameters
For example, the exponential circuits are used in drifts and mismatches will be practically removed
telecommunication, medical equipment or disk drives [1] because the output current expression is designed to be
– [6], while the squaring and Euclidean distance circuits not dependent on technology.
find applications in instrumentation circuits,
communication, neural network, display systems or A. The CMOS Implementation of the Current Squarer
vector quantization [7], [8]. The core of the circuit is represented by the CMOS
current-mode current squarer. Deriving from this circuit,
The original circuit presented in the following it is possible to implement all the desired continuous
paragraph represents a digitally programmable current- functions by using the limited Taylor series expansion.
mode function generator, designed for implementing There will be presented six possible realizations of the
mathematical functions for VLSI applications. same function (the current squaring), using exclusively
II. THEORETICAL ANALYSIS MOS transistors or FGMOS transistors biased in
saturation region for improving the frequency response.
The original idea for obtaining an important number of
basic or complex mathematical functions is the utilization 1) The first CMOS current squarer: the original
of n elementary generators for implementing implementation of a CMOS current squarer using a
FGMOS transistor is presented in Fig. 1.
g k ( x ) = x k , k = 1,..., n functions and the computing of

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 VCC

1 1 2 1 1
IO IIN

IOUT
IO IO1 ID
4
IIN
1/4
1/2 1 1 1
T1 T2

Fig. 1. CMOS squarer using a FGMOS transistor

The FGMOS transistor is a MOS transistor whose gate Because of the PMOS multiple current mirrors, it is
is floating, being capacitive coupled to the multiple input possible to write that:
gates. The drain current of a FGMOS transistor with n-
input gates working in the saturation region is given by I D = 2 I O + I O1 + I IN , (6)
the following equation:
resulting:
2
K 
n
( I O + I IN ) 2 I O I IN I IN
2
ID =
2  ∑
 k i (Vi − V S ) − VT 

(1) I O1 =
4I O
=
4
+
2
+
4I O
. (7)
 i =1
where K = µ n Cox (W / L) is the transconductance Thus, the output current expression is:
parameter of the transistor, µ n is the electron mobility,
C ox is the gate oxide capacitance, W / L is the transistor 2
I IN
I OUT = . (8)
aspect ratio, ki , i = 1,..., n are the capacitive coupling 4I O
ratios, Vi is the i -th input voltage, VS is the source
The most important advantage of the original
voltage and VT is the threshold voltage of the transistor. implementation of the current squarer proposed in Fig. 1
Considering that all MOS transistors from Fig. 1 are is the absolutely (in a first-order analysis) independence
working in saturation and k1 = k 2 = 1 / 2 , the expression of the circuit output current on technological parameters
of the drain current of the FGMOS transistor could be ( K , VT ).
written as:
2) The second CMOS current squarer: another original
2 idea for implementation the current-mode squarer is to
4K  1 1  use two groups of cascaded MOS transistors, the devices
ID =  VGS1 + VGS2 − VT  , (2)
2 2 2  from the first group being biased at the same drain
current, while each MOS transistor from the second
where VGS1 and VGS2 represents the gate-source group works at different drain currents (Fig. 2).
voltages of T1 and T2 transistors, respectively, having
the following expressions: IO IOUT

2I O
VGS1 = VT + , (3) IIN
K
IOUT + IIN
2 I O1
VGS2 = VT + . (4)
K
From the previous three relations it results the
following dependence of the FGMOS transistor drain Fig. 2. The current-mode CMOS squarer
current on I O and I O1 currents:
Considering a strong inversion (saturation) operation of
all MOS transistors from Fig. 2, it is possible to write:
I D = I O + I O1 + 2 I O I O1 . (5)

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   respectively), the I 2 current expression could be written
2VT +
2 IO  = 2VT + 2 IOUT + 2( IOUT + I IN ) ,
 K  K K as:
 
(9) 4K
I2 = (VCC − V − VT )2 , (13)
equivalent to: 2

2
2 I O = I OUT + I OUT + I IN (10)  V + V1 
. I 2 = 2 K VCC − O − VT  , (14)
 2 
After some algebraic computations, it results the
expression of the output current I OUT : resulting:

(4 I O − I IN ) 2 I 2 = IO + I1 + 2 I O I1 . (15)
I OUT = . (11)
16 I O Using this square-root function, the desired square
So: function can be easily obtained by subtracting I IN and
2 I O currents from I 2 current expression.
I IN I2 The full implementation in CMOS technology of the
I OUT = I O − + IN . (12)
2 16 I O square function is presented in Fig. 4.
Using NMOS current mirrors, I 2 current is forced to be
Subtracting I O current and adding I IN / 2 current to
equal to:
the previous relation of I OUT , it is possible to obtain an
output current proportional to the square of the input I 2 = I 1 + I IN + 2 I O . (16)
current.
From the two previous relations it results:
3) The third CMOS current squarer: the third proposed
circuit (Fig. 3) for implementing the square function is ( I O + I IN ) 2 I O I IN I2
based on an original principle of the average potential. I1 = = + + IN . (17)
4I O 4 2 4IO

VCC Considering that the output current has the following

linear dependence on the circuit currents (that could be
1 4 1 implemented using simple current mirrors):
I2
I 0 I IN
I OUT = I 1 − − . (18)
V
4 2
V0 V1
it results an output current proportional to the square of
IO I I I I1 the input current:
Fig. 3. The CMOS squarer based on 2
I IN
a new principle of the average potential I OUT = . (19)
4I0
Because the V potential represents the arithmetic mean
of VO and I potentials (fixed by I O and I currents,

VCC

1 1
I1
I
4
VO V1 I2
IO IO V I1 I1 2IO
I I
IIN

Fig. 4. The CMOS squarer based on a new principle of the average potential

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 4) The fourth CMOS current squarer: the circuit of the
current squarer is presented in Fig. 5. Considering that all 5) The fifth CMOS current squarer: the next circuit
transistors from Fig. 5 are working in saturation, it is proposed for implementing the squaring function is
possible to write: presented in Fig. 6. Considering that all transistors are
working in saturation, it results that:
2 I IN 2IO 2 I OUT
2VT + 2 = 2VT + + (20)
K K K K I I2
I OUT = (V − VT )2 = I O + IN + IN . (24)
resulting that: 2 2 16 I O

So, subtracting I O and I IN / 2 from expression (24), it

2 I IN = I O + I OUT (21)
. is possible to obtain a quadratic dependence of the output
current I OUT on the input current I IN .
Because of the PMOS current mirror having a current
ratio equal to 3 it results:
VCC
I O + I OUT = 3 I IN . (22)
IO
Thus, the output current of the circuit presented in
Fig. 5 will be proportional to the square of the input
IIN
current I IN :
V IOUT
2
I IN
I OUT = . (23)
4IO
VCC
Fig. 6. The circuit for implementation the squaring function

1 3

IIN

IO IOUT

IO

Fig. 5. The circuit for implementation squaring function

VCC

4IO

T1
IOUT

TO
T2
IO
IIN IIN I I 4I

TO ’

Fig. 7. The CMOS current-squarer

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 The quantitative evaluation of the error introduced by
6) The sixth CMOS current squarer: the operation of
the second-order effects in the current squarer operation
the CMOS current squarer presented in Fig. 7 will be first
analyzed considering the simplest well-known quadratic could be expressed using the error ε 1 , which will modify
characteristic of the saturated MOS device. For the circuit the expression (27) of I OUT current:
core represented by TO , TO ' , T1 and T2 transistors it is
possible to write that: I2
I OUT = IN + ε 1 , (32)
IO
2VGSO = VGS1 + VGS2 , (25)
where:
equivalent to:
2IO
2 I O = I + I IN + I − I IN , (26) ε 1 = 2θ G I O . (33)
K
resulting that: The error of computing I OUT current is proportional to
the constant θ G that models the mobility degradation
I2
I OUT = 4(I − I O ) = IN . (27) effect and it will also affect the entire function generator
IO circuit accuracy.
The symbolic representation of each current squarer B. The Function Generator
presented above is shown in Fig. 8.
The goal is to design a circuit that could be digitally
controlled in order to compute a relatively large number
of continuous functions. The core of this circuit is
represented by the previous presented current squarer, all
IO IIN the desired functions being approximated by their limited
polynomial series expansion. A digital word will choose
IOUT IOUT IOUT from a preset list the active computed function.
Considering the expansion variable x equal to the ratio
of input and reference currents:

I
Fig. 8. The symbolic representation of the current squarer x = IN << 1 , (34)
IO
The operation of the circuit presented above are affected it results that the approximate expression of function
by the second-order effects that degrade the quadratic law f ( x) could be written as a limited Taylor expansion
of the MOS transistor. These undesired effects are
modeled by the following relations (channel length series:
modulation (28) and mobility degradation (29)).
∞ f ( k ) ( x) k
I IN
K
I D = (VGS − VT )2 (1 + λV DS ) ; (28)
I O f ( x ) = I O f (0) + ∑ k!
x =0
I Ok −1
, (35)
2 k =1

K0 where f ( k ) ( x) represents the value of the k − th

K= . (29) x =0
[1 + θ G (VGS − VT )](1 + θ DV DS ) order derivate of f ( x) in x = 0 . For simplicity, the
following notations will be used:
Considering that the design condition λ = θ D is
fulfilled, the gate-source voltage of a MOS transistor
f ( k ) ( x)
working in saturation at a drain current I D will have the ak = x =0
(36)
following expression: k!

VGS = VT +
2I D I
+θG D . (30) I k +1
K K I OUT (k ) = IN . (37)
I Ok
Taking into account the second-order effects, the
relation (26) becomes: So, the function f ( x) and I OUT current could be
written as a linear expression of I OUT ( k ) currents:
θG
2 IO + (I O − 2 I ) = I + I IN + I − I IN . (31)
2K

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 ∞ (1) 1
I OUT = I O f ( x ) = I O f (0) + ∑ a k I OUT (k −1) . (38) ak =
k!
(40)
k =1
for f 1 ( x) function and:
The block diagram of the function generator circuit is
presented in Fig. 9, consisting in n identical current
( 2) (2 ) (−1) k
squarers for a n − th order polynomial series expansion a 2 k = 0; a 2 k + 1 = (41)
of f ( x) function and in a block that computes a k (2k + 1)!
coefficients for k = 0,1,..., n + 1 . The current squarers for f 2 ( x) function.
implementations and interconnections remain the same III. CONCLUSIONS
for all the computed functions, representing the
The proposed circuit allows the computing of an
expansion basis, while the configuration of a k block
important number of mathematical functions using their
could be digitally changed using bk , k = 1,..., m bits for n − th order limited polynomial series expansion. The
each selected function. The advantage of this selection of the active function is digitally made, the main
implementation is that the part of the circuit that has the part of the function generator being common for all the
more important area (the current squarers) is the same for computed functions. The core of the circuit is represented
all the computed function. So, a very good precision of by an original current-mode squarer, using exclusively
the circuit could be achieved by increasing the value of n MOS transistors working in strong inversion (saturation)
(the medium complexity for each function is, for improving the circuit frequency response. Classical
approximately, given by the area of the squarers, divided MOS transistors have been replaced by a FGMOS
by the number of the functions). transistor for reducing the circuit complexity. The circuit
was implemented in 0.35 µm CMOS technology, SPICE
IO IOUT (0) = IIN
IO simulations confirming the theoretical estimated results.
a0
IO IIN IOUT (0) REFERENCES
a1
IOUT IOUT IOUT [1] R. Harjani, “A Low-Power CMOS VGA for 50 Mb/s Disk Drive
IOUT (1) Read Channels”, IEEE Transactions on Circuits and Systems II,
a2
Analog Digital Signal Processing, pp. 370-376, 1995.
IOUT (1)
IIN IOUT (1) [2] A. Motamed, C. Hwang, and M. Ismail, “A Low-Voltage Low-
IO IIN Power Wide-Range CMOS Variable Gain Amplifier”, IEEE
Transactions on Circuits and Systems, Analog Digital Signal
IOUT IOUT IOUT
Processing, pp. 800-811, 1998.
IOUT (2)
a3 [3] P.C. Huang, L.Y. Chiou, and C.K. Wang, “A 3.3V CMOS
IOUT (2) Wideband Exponential Control Variable gain Amplifier”,
IOUT (2)
ak Proceedings 1998 of IEEE International Symposium on Circuits
IO IIN
block and Systems, pp. 285-288, 1998.
IOUT
IOUT IOUT IOUT [4] S. Vlassis, and S. Siskos, “Current-Mode Non-Linear Building
IOUT (3) Blocks Based on Floating-Gate Transistors”, IEEE International
a4 Symposium on Circuits and Systems, pp. II-521 – II-524, 2000.
IOUT (3) [5] S. Vlassis, “CMOS Current-Mode Pseudo-Exponential Function
IOUT (3)
IO IIN Circuit”, Electronics Letters, pp. 471-472, 2001.
IOUT IOUT IOUT [6] C.C. Chang, “Current-Mode Pseudo-Exponential Circuit with
IOUT (4) IOUT (4) Tunable Input Range”, Electronics Letters, pp. 1335-1336, 2000.
a5 [7] E. Seevinck,R.F. Wassenaar, and C.K. Wong, “A Wide-Band
IOUT (4)
Technique for Vector Summation and Rms-Dc Conversion”, IEEE
Journal of Solid-State Circuits, vol. SC-19, pp. 311-318, 1984.
IOUT (n-2) IOUT (n-1)
[8] S. Collins, D.R. Brown, and G.F. Marshall, “An Analogue Vector
IO IIN b0
digital Matching Architecture”, Analog Integrated Circuits and Signal
IOUT IOUT IOUT bm selection Processing, pp. 247-257, 1995.
IOUT (n)
an+1

Fig. 9. The block diagram of the function generator circuit

C. Example of Computed Functions

For example, the polynomial series expansions for
f 1 ( x) = exp( x) and f 2 ( x) = sin( x) are, respectively:

x x2 x3
f 1,2 ( x) = 1 + ± + ± ... , (39)
1! 2! 3!
so a k coefficient are, for each function:

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