Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology

ISSN No- 2584-2706

Digital Sign Calculator Verification and

Implementation of Verilog HDL via FPGA
Simulation
Dr. Sarabjeet Kaur
Aditya Soraut
Amit Verma
Abhishek Kumar

Abstract:-
It is a possible to set up a digital sign calculator
Scientific calculators included a number of
in the course of daily living. In this exploration
extended operations, such as logarithmic,
composition, the pattern of a sign calculator is
exponential, trigonometric, and hyperbolic
brought forward by using a format of Verilog
Functions, that can break through complex
HDL. Much synthetic Verilog code was created
mathematical functions. Binary format is also
and obtained in Artix-7. The design of a 9-bit
used for the calculators' input data.
digital sign calculator can break fine
Additionally, the connected circuit will translate
mathematical operations similar to adder,
the decimal numbers into the base-two binary
subtract, multiplier, and divider. This digital
number system. Double data strings are used in
sign calculator consists of nine-digit figures.
integrated circuits to regulate transistors so that
The simulation procedure will be carried out in
mathematical calculations may be performed.
this article using devices from the Xilinx
Mathematical tasks are completed, and the
family. A shaft-style simulation of the
binary data is returned to the basic ten systems.
calculator design is one of the outputs
The conclusion will show on the display screen.
displayed in the waveform and RTL view.
A complicated circuit is created by combining
Calculator facts have been used favorably using
many logical gates to build adders. Numerous
Verilog HDL in relation to the behavior of the
mathematical operations, including addition,
sign calculator functions.
subtraction, multiplication, division, and more,
may be carried out by different combinations of
Keywords-
logical gates inside the chips.
Digital Sign Calculator, Circuit design,
Verilog, Mathematical function The creation of quicker, physically smaller
designs with a greater number of gates and
I. Introduction smaller sizes presents substantial problems for
The digital sign calculator consists of computer digital designers. To operate the device at the
programs and hardware that can do basic worst possible temperature, FPGA designers
must produce designs that satisfy crucial
arithmetic operations, such as adder, subtractor,
requirements that other designers can
multiplier, and dividor. In the scientific comprehend. Furthermore, it is evident that the
calculator there are numerous high-potential process variable circumstances may match the
tasks, such as logarithmic, exponential, specifications and do not surpass the power
trigonometric, and hyperbolic functions, which consumption objectives. They are also reliable
might simplify challenging mathematical and verifiable. As a result, the designer writes
tasks.The development of calculators reduced and synthesizes hardware description language
the amount of time needed to explain (HDL) code, which is then executed in the
complicated numbers and the mistakes that hardware chips. Verilog is crucial for business
occur when calculating integers by hand. testing and replication of the outputs since it

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 Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology
ISSN No- 2584-2706

prevents mistakes. Free experiments are Figure 1. Flow and Data Type
available in the Verilog simulation, and The digital sign calculator's block depiction is
software tools for evaluating FPGA logic seen in Figure 2. The investigation and
devices are also free. Hardware An overview advancement are performed utilizing Verilog
Systems based on the chips with schematics HDL with the Xilinx ISE 14.0 computer
have been developed using languages like program. In the Verilog HDL programming
Verilog HDL and VHDL. Signal logic is carried language, the calculator plan is divided into
out by RTL, the design abstraction that controls many significant corridors, each of which is
the modeling of digital signals between programmed in a distinct module and activated
hardware payrolls and synchronous digital using the RTL view and waveform lines. The
circuits. Numerous studies on calculator design "sign calculator" module is the best work
have been conducted, including RISC (64-bit) module for the digital sign calculator in this
calculator design using Verilog HDL and FPGA business strategy.
Board; translation of splitting algorithms into
Verilog programming language; FPGA All computing handling and capacities run in
prototype and a basic 9-bit calculator design bit this module. As appeared in Figure 2,In the
slicing technique; updated non-restoring square process of converting the input data from
root calculators with reduced VHDL code; and decimal to binary format, inputs from the
a novel approach for creating FPGA-integrated "push" section were received in the blocks
square root calculators. based on the block illustration. The
"DECIMAL" function performs the information
computation. This function stacks the twice
II. The Flow Design and Data Type supplied data to register A. Sign up The amount
The data types' block illustrations and the of memory consumed is returned by a function.
For processing reasons, Register B stored the
computational design processes are shown in
input number memory on the seven-segment
Figure 1.Initially, the design was provided the
input values; For data processing reasons, the LED screen. Implemented, reset (Rst), sign
control(S), mode of operation (M), add,
structure is found in a decimal shape and
transformed into a binary format. The digital subtract, multiply, and divide are among the
operators.
sign calculator may be used for multiplication,
division, addition, and subtraction, among other
binary operations. The push-button portion of
the synchronous unit has transformed the data
from the asynchronous unit.A binary-to-decimal
format is created for the unit operating at the 7-
segment unit using the computed output data in
binary format. The first result of the
mathematical operations is created by indicating
the number by illuminating different positions
of the seven-segmented LEDs. These are nine
sets of output LEDs with seven segments each.
Eight of them display the number derived from
the computation's outcome. The other, on the
far left, displays the number indicator. Figure-2. Sign Calculator block diagram

III. Bit Width Register

To ensure that the calculator's design can
execute eight-digit computations, it is essential
to evaluate the bit width range of the
registers.The number of digits in a register is its
bit width. Enroll A's inputs fall between 0 and
9999, meaning that in its two-fold version, they

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 Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology
ISSN No- 2584-2706

fall between 0 and counter where only one bit changes value
101111101011110000011111111. -199999998 between two consecutive counts. The offbeat
(-99999999-99999999) to 199999998 flag "reset," which starts the count, is shared by
(99999999+99999999) is the range of values in all of the flip-flops.
the decimal frame. When converted to its two-
D flip-flops make up the n-bit circuit; each flip-
fold structure using the values of 199999998, it
flop stores data on its own. These flip-flops can
has 28 bits and is
store and perform multi-digit computations
1011111010111100000111111110. The
efficiently since they are linked in parallel and
formula for the sum of all bit ranges is 2 . share a reset and signal clock.
Then let n be the representative of the number
of bits, and 2� = 228 = 268435456.2� = 228 =
VI. Result And Discussion
268435456. The binary representation of the The Modulus-designed RTL viewer is shown in
decimal 268435456 is Figure 4 at the higher value of the code in the
10000000000000000000000000000. To appendix. "Sign calculator" is the name of the
arrange, the memory address has to be in the top-level module. There are fifteen outcome
two-fold format. pins and fourteen input pins in the blueprint.
IV. Overflow The syncro blocks operate based on the function
When the number estimate exceeds the selected by the user, directing the data into the
maximum bit area allowed in the registers, an ‘sign calculator’ module. In the meantime
overflow occurs. In order to prevent overflow, syncro10 will work based on the number
the articles require that entries be limited to a entered by the user. Ultimately, all of the data
range between -999999999 and 999999999. enters the "sign calculator" module, which
The design overflow is calculated based on the carries out the primary arithmetic operations,
decimal mode behavior. With the signed binary including addition, subtraction, multiplication,
form of and division. This module also manages the bit
0000_0101_1111_0101_1110_0000_1111_111 width of registers and overflow detection.
1, the input values must be greater than - The waveform summary in the Report Timing
999999999. Converting to its 2's complement part of the circuit's timing performance is
yields the following value: displayed in Figure 4. The Nexys A7 FPGA
1111_1010_0000_1010_0001_1111_0000_000 was used to implement the sign calculator
1. blueprint. It enables effective data management
Therefore, when its 2's complement double and contains the most registers overall. The
value is translated back into decimal form, it quantity of data the system can process at any
becomes 4194967297. However, as this is the given time depends on the size of these
maximum value for a nine-digit calculator, the registers.
input values must not be greater than
999999999. A time request for a cycle of 20.0 ns is provided
by this circuit. With a positive setup slack value
V. The Synchronous Circuit of 12.711 ns, the design satisfies the time
Flip-Flop is made up of an edge detector circuit requirements. The time required to extend the
and a latch with an activation input. A signal clock signal from the device pins to the
clock serves as the edge locator's input. A target/source flip-flop's clock signal is known as
square shaft with a fixed frequency is called a the tactful delay, and it is 4.985 ns.
signal clock. The edge circuit for producing There is a 5.758 ns data delay. This
impulses during ascent is a positive edge-trigger illustrates how long it takes for a signal to get
flip-flop. from its source to the intended flip-flop. The
In the nine-digit calculator, flip-flops share a waveform illustration guarantees that the time
common reset and a signal clock, and an n-bit restriction is fulfilled and that the data reaches
shift register is linked in series. This ensures the target before the required amount of time.
accurate numerical operations by producing a

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 Volume-3, Issue-4, April 2025 International Journal of Modern Science and Research Technology
ISSN No- 2584-2706

Register A may receive the alternative input An example of a waveform simulation with
values. Register B is where the final values are increment is shown in Figure 6. 20 ns per period
entered. The calculated data is sent to register was the timer's initial setting. The "equal"
B. In order to process the result, Register B has waveform was consistently raised to the highest
stored the input number in memory. As with the possible level. The "reset" waveform was
expansion, let's say the customer selects the inserted into a d flip-flop type to manage the
operation. In this instance, a high or active state calculator design flux, depending on the proper
is indicated by the multiplexer changing from 0 circumstances. Pressing the double format value
to 1. Division, multiplication, and subtraction into a decimal waveform fits the desired values
are further operations. within the calculator's architecture. By placing
their waveform in an advanced position, the
desired chosen processes may be given names.
To enlist A, double input data is stacked into this
function. The number of customers in the
memory is returned by the Enlist A function.
The first input number is taken by Enrol A.
Subsequently, the input number that is
substituted begins at 0. once the customer
choose what they want. Figure 5 shows that 14
and 7 are the two inputs from the "decimal"
signal that are stacked to enroll A. "Add," which
stands for the addition operation, is the
administrator selection. The calculated result
yields at the "out" waveform and is stored in
registers B and 21. This suggests that 21 is the
consequence of adding the numbers 14 and 7.
The system used for the final interpretation is
the same for all other steps.

Figure-5. The Waveform of the ‘add’ function

Figure-3. Top-level module RTL view simulation.
‘sign calculator’
The waveform reconstruction of the unique
functions of the calculator design using Verilog
HDL in this study, such as independent
division, multiplication, and deduction, is
shown in Figures 6, 7, and 8.

Figure-4. The Report Timing section of the

circuit’s waveform

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ISSN No- 2584-2706

Figure-6. The Waveform of the ‘sub’ function VIII. Confirmation

simulation I would want to express my gratitude to Noida
Institute of Engineering and Technology for
giving me the space and chance to create this
module.

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