What is computer organization?

Computer organization refers to the operational units and their interconnections that realize
the architectural specifications of a computer. It involves the structural relations and the
manner in which the components of the computer system are connected and work together.
What is computer architecture?
Computer architecture is the conceptual design and fundamental operational structure of a
computer system. It encompasses the layout of the hardware, the design of the instruction set,
and the techniques for data handling and processing. The objective is to outline a blueprint
that ensures optimal performance and efficiency.
What is the difference between computer organization and architecture?
While computer architecture is concerned with the conceptual design and functional
specification of a computer system, computer organization deals with the detailed operational
implementation of the system. Essentially, architecture provides the macro-level blueprint,
while organization focuses on the micro-level realization.
Why is understanding computer organization and architecture important?
Understanding computer organization and architecture is crucial for designing efficient
computer systems, improving existing ones, and making informed decisions about hardware
resources. It also helps in optimizing software to make full use of the underlying hardware and
enhance overall system performance.
What are the key components of computer organization?
The key components of computer organization include the central processing unit (CPU),
memory hierarchy (registers, cache, RAM, and secondary storage), input/output devices, and
the interconnection system (buses and communication channels) that allows these
components to interact effectively.

Unit-2

Register Transfer and Micro Operations

Register Transfer Language

A digital computer system exhibits an interconnection of digital modules such as registers, decoders, arithmetic
elements, and Control logic.
These digital modules are interconnected with some common data and control paths to form a complete digital
system.
Moreover, digital modules are best defined by the registers and the operations that are performed on the data stored
in them.
The operations performed on the data stored in registers are called Micro-operations.
The internal hardware organization of a digital system is best defined by specifying:
o The set of registers and the flow of data between them.
o The sequence of micro-operations performed on the data which are stored in the registers.
o The control paths that initiates the sequence of micro-operation
The Register Transfer Language is the symbolic representation of notations used to specify the sequence of micro-
operations.
In a computer system, data transfer takes place between processor registers and memory and between processor
registers and input-output systems. These data transfer can be represented by standard notations given below:
o Notations R0, R1, R2..., and so on represent processor registers.
o The addresses of memory locations are represented by names such as LOC, PLACE, MEM, etc.
 o Input-output registers are represented by names such as DATA IN, DATA OUT and so on.
o The content of register or memory location is denoted by placing square brackets around the name of
the register or memory location.

Register Transfer
The term Register Transfer refers to the availability of hardware logic circuits that can perform a given micro-
operation and transfer the result of the operation to the same or another register.
Most of the standard notations used for specifying operations on various registers are stated below.
o The memory address register is designated by MAR.
o Program Counter PC holds the next instruction's address.
o Instruction Register IR holds the instruction being executed.
o R1 (Processor Register).
o We can also indicate individual bits by placing them in parenthesis. For instance, PC (8-15), R2 (5),
etc.
o Data Transfer from one register to another register is represented in symbolic form by means of
replacement operator. For instance, the following statement denotes a transfer of the data of register
R1 into register R2.
1. R2 ← R1
o Typically, most of the users want the transfer to occur only in a predetermined control condition. This
can be shown by following if-then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.
o It is more convenient to specify a control function (P) by separating the control variables from the
register transfer operation. For instance, the following statement defines the data transfer operation
under a specific control function (P).
1. P: R2 ← R1
The following image shows the block diagram that depicts the transfer of data from R1 to R2.

Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the register R1 are connected to the
'n' inputs of register R2.
A load input is activated by the control variable 'P' which is transferred to the register R2.

Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer information from one register to
another. The number of wires connecting all of the registers will be excessive if separate lines are used between
each register and all other registers in the system.
A bus structure, on the other hand, is more efficient for transferring information between registers in a multi-register
configuration system.
A bus consists of a set of common lines, one for each bit of register, through which binary information is transferred
one at a time. Control signals determine which register is selected by the bus during a particular register transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the help of four 4 * 1
Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1 and S2).
We have used labels to make it more convenient for you to understand the input-output configuration of a Bus system
for four registers. For instance, output 1 of register A is connected to input 0 of MUX1.

The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers. The selection lines
choose the four bits of one register and transfer them into the four-line common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four multiplexers are selected
and applied to the outputs that forms the bus. This, in turn, causes the bus lines to receive the content of register A
since the outputs of this register are connected to the 0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content provided by register B.
The following function table shows the register that is selected by the bus for each of the four possible binary values
of the Selection lines.
Note: The number of multiplexers needed to construct the bus is equal to the number of
bits in each register. The size of each multiplexer must be 'k * 1' since it multiplexes 'k'
data lines. For instance, a common bus for eight registers of 16 bits each requires 16
multiplexers, one for each line in the bus. Each multiplexer must have eight data input
lines and three selection lines to multiplex one significant bit in the eight registers.
A bus system can also be constructed using three-state gates instead of multiplexers.
The three state gates can be considered as a digital circuit that has three gates, two of which are signals equivalent
to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a high-impedance state.
The most commonly used three state gates in case of the bus system is a buffer gate.
The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.
 o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputs will communicate with the
bus line.
o A 2 * 4 decoder ensures that no more than one control input is active at any given point of time.

Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated below.
o The transfer of information from a memory unit to the user end is called a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:
1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data register (DR) from the memory
word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:
1. Write: M [AR] ← R1
 o The Write statement causes a transfer of information from register R1 into the memory word (M)
selected by address register (AR).

Arithmetic Micro-operations
In general, the Arithmetic Micro-operations deals with the operations performed on numeric data stored in the
registers.
The basic Arithmetic Micro-operations are classified in the following categories:
1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift
Some additional Arithmetic Micro-operations are classified as:
1. Add with carry
2. Subtract with borrow
3. Transfer/Load, etc.
The following table shows the symbolic representation of various Arithmetic Micro-operations.
Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to

R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to

R3.

R2 ← R2' Complement the contents of R2 (1's

complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Note: The increment and decrement micro-operations are symbolized by '+ 1' and '? 1'
respectively. Arithmetic operations like multiply and divide are not included in the basic
set of micro-operations.

Logic Micro Operations

 What are Logic Micro-Operations
in Computer Architecture?
Logic operations are binary micro-operations implemented on the bits saved in the registers. These
operations treated each bit independently and create them as binary variables.
For example, the exclusive-OR micro-operation with the contents of two registers R1 and R2 is denoted

P: R1←R1⊕⊕R2
by the statement

It determines a logic micro-operation to be implemented on the single bits of the registers supported
that the control variable P = 1. Consider that each register has four bits. Let the content of R1 be 1010
and the content of R2 be 1100.
The exclusive-OR micro-operation stated above represent the following logic computation −
1010 Content of R1
1100 Content of R2
0110 Content of R1 after P = 1
The content of R1, after the implementation of the micro-operation, is similar to the bit-by-bit
exclusive-OR operation on pairs of bits in R2 and previous values of R1.

Special Symbols
Special symbols will be approved for the logic micro-operations OR, AND, and complement, to
categorize them from the matching symbols that can define Boolean functions. The symbol V can
indicate an OR micro-operation and the symbol can indicate an AND micro-operation.
The complement micro-operation is similar to the 1's complement and supports a bar on the highest of
the symbol that indicates the registered name. There are various symbols, and it will be applicable to
differentiate between a logic micro-operation and a control (or Boolean) function.
There is another sense for supporting two sets of symbols can that recognize the symbol +, when can
symbolize arithmetic plus, from a logic OR operation. Although the + symbol has two meanings, it will
be available to determine between them by observing where the symbol appears.
When the symbol + appears in a micro-operation, it will indicate an arithmetic plus. When it appears in
a control (or Boolean) function, it will indicate an OR operation. We cannot use it to symbolize an OR
micro-operation.
For example, in the statement
P+Q: R1←R2+R3,R 4←R5V R6
The + between P and Q is an OR operation between two binary variables of a control function. The +
between R2 and R3 determines an add micro-operation. The OR micro-operation is named by the
symbol V between registers R5 and R6.
 What are Shift Micro-operations
in Computer Architectures?
Shift micro-operations are used for the serial transfer of data and also support in conjunction with
arithmetic, logic, and several data-processing operations. The contents of a register can be shifted to
the left or the right.
Simultaneously, that the bits are shifted, the first flip-flop holds its binary data from the serial input. In
shift-left operation, the serial input transfers a bit into the rightmost position. In shift-right operation,
the serial input transfers a bit into the leftmost position. The data transferred by the serial input
decides the type of shift.

Types of Shift Micro-operations

There are three types of shift micro-operations are as follows −

Logical Shift
It transfers 0 by the serial input. The symbol "shl" can be used for logical shift left and "shr" can be
used for logical shift right.
R1 ←R1 shl R1
R2 ←R1 shr R2
The register symbol should be the equivalent on both sides of the arrows.

Circular Shift
This circulates or pivots the bits of register around the two ends without any trouble of data or
contents. In circular shift, the serial output of the shift register is linked to its serial
input. "cil" and "cir" is used for circular shift left and right respectively. The symbolic documentation
for the shift micro-operations is demonstrated in the table.
Shift Micro-operations
Symbolic Designation Description
R ←R1 shl R Shift-left register R
R ←R1 shr R Shift-right register R
R ←R1 cil R Circular shift-left register R
R ←R1 cir R Circular shift-right register R
R ←R1 ashl R Arithmetic shift-left R
R ←R1 ashr R Arithmetic shift-right R

Arithmetic Shift
This shifts a signed binary number to left or right. An arithmetic shift left multiplies a signed binary
number by 2 and shift left divides the number by 2. Arithmetic shift micro-operation leaves the sign bit
constant due to the signed number remains equal when it is multiplied or divided by 2.
Rn-1 Rn-2 R→ R1 R0
Sign bit
Arithmetic Shift Right
The leftmost bit in a register influences the sign bit, and the remaining bits influence the number. The
sign bit is 0 for positive and 1 for negative. Negative numbers are in 2's complement form. The figure
displays a symbolic register of n bits.
Bit Rn-1 in the leftmost position holds the sign bit.
Rn-2 is the most significant bit of the number and
R0 is the least significant bit. The arithmetic shift-right leaves the sign bit constant and shifts the
number (involving the sign bit) to the right. Therefore
Rn-1 remains the equal,
Rn-2 receives the bit from
Rn-1 and so on for the other bits in the register. The bit in
R0 is lost.

What is Arithmetic Logic Shift

Unit in Computer Architecture?
A computer systems create use of several storage registers that are linked to a typical operational unit
is known as the arithmetic and logic unit (ALU). ALU is the central and one of the most essential units
internal the CPU of the computer.
All the logical and numerical operations of a computer are implemented here. The contents of a
particular register are arranged in the input of ALU. ALU implements the given operation and then
transfers it to the target register.
The one stage of an arithmetic logic shift unit is demonstrated in the figure. The subscript i nominate a
frequent stage. There are two inputs are used for both the arithmetic and logic units.
A specific micro-operation is choosing with inputs S 1 and S0 A 4 x 1 multiplexer at the output select
between an arithmetic output inand a logic output in . The data in the multiplexer are chosen with
inputs S3 and S2.
There are two data inputs to the multiplexer receive inputs A i-1 for the shift-right operation and A i+1 for
the shift-left operation. The circuit should be continued n times for an n-bit ALU.
The output carry Ci+1 of a given arithmetic stage should be linked to the input carry C i of the next stage
in the series. The input carries to the first stage is the input carry C in It can support a selection variable
for the arithmetic operations.
The circuit whose one stage is determined in the diagram. It provides eight arithmetic operations, four
logic operations, and two-shift operations. Each operation is selected with the five variables
S3,S2,S1,S0The input carries Ci∧Cin can be used for selecting an arithmetic operation only.
Functional Table for Arithmetic Logic Shift Unit
S3 S2 S1 S0 Cin Operation Function
0 0 0 0 0 F = A Transfer A
0 0 0 0 1 F = A +1 Increment A
0 0 0 1 0 F = A +B Addition
0 0 0 1 1 F = A +B+1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’ + 1 Subtraction
0 0 1 1 0 F = A –1 Decrement A
0 0 1 1 1 F = A Transfer A
 ∧∧ B
F = A ∨∨ B
0 1 0 0 X F=A AND

F = A⊕⊕B
0 1 0 1 X OR
0 1 1 0 X XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift Left A into F
This table shows the 14 operations of the ALU. The first eight are arithmetic operations and are
selected with S3S2 = 00. The next four are logic operations and are selected with S 3S2 = 01. The final
two operations are shift operations and are selected with S 3S2 = 10 and 11. The other three selection
inputs do no influence the shift.

BASIC COMPUTER ORGANIZATION AND DESIGN: