A

Report on

VHDL PROGRAM TO IMPLEMENT MUX

Submi ed by:

Prinsi Khaire
Vishakha Danav
Samiksha Gedam

Guided by:
Mrs. Mrunali Nagarkar

BAJAJ CHANDRAPUR POLYTECHNIC CHANDRAPUR

ELECTRONIC AND TELECOMMUNICATION ENGINEERING
(EJ 6I)
SESSION 2025-26
  INDEX

1. Introduc on

2. Diagram

3. Explana on

4. Advantages

5. Disadvantages

6. Applica on

7. References
  INTRODUCTION

A multiplexer (MUX) is a fundamental digital circuit used to select one of several input signals
and forward it to a single output line. It operates using select lines, which determine which
input is connected to the output at any given time. This functionality makes multiplexers
extremely valuable in digital systems where efficient data routing and resource sharing are
critical. A 4:1 multiplexer has four data input lines, two select lines, and one output. Depending
on the binary combination of the select lines, one of the four inputs is transmitted to the output.

In digital design, the use of hardware description languages (HDLs) like VHDL (VHSIC
Hardware Description Language) allows for modeling, simulation, and synthesis of digital
circuits before actual implementation. VHDL is widely used in academia and industry due to
its versatility and ability to describe complex systems at various levels of abstraction.

This project involves implementing a 4:1 multiplexer using VHDL. The design utilizes
behavioral modeling, where a process block and a case statement are used to assign the correct
input to the output based on the select line values. This approach not only simplifies the design
process but also makes the logic more understandable and easier to test. By simulating the
VHDL code, the correct operation of the multiplexer can be verified, demonstrating the
practical application of digital logic and the power of HDL-based design workflows.
  BLOCK DIAGRAM

Block Diagram Of MUX

  EXPLANATION

🔍 What is a Mul plexer?

A multiplexer (MUX) is a combinational circuit that selects binary information from one of
many input lines and directs it to a single output line. The selection of input is controlled by
select lines.

 A 2:1 MUX has 2 inputs, 1 select line, and 1 output.

 A 4:1 MUX has 4 inputs, 2 select lines, and 1 output.

🧩 Idea Behind Building 4:1 MUX from 2:1 MUX

To design a 4:1 MUX using only 2:1 MUXes, we use three 2:1 MUXes:

 Two for the first level (choosing between two inputs each).
 One for the second level (choosing between the outputs of the first level).

🔷 Inputs and Select Lines

 Inputs: I0, I1, I2, I3

 Select lines: S1 (higher-order bit), S0 (lower-order bit)
 Output: Y

🧠 Selec on Logic
Here’s how it works:

S1 S0 Selected Input
0 0 I0
0 1 I1
1 0 !2
1 1 I3
So, we first use S0 to choose between:

 I0 or I1 → Output = Out1
 I2 or I3 → Output = Out2

Then use S1 to choose between:

 Out1 or Out2 → Final Output = Y

🛠 VHDL Implementa on
Now, let’s translate the above logic into VHDL code.

✅ En ty Declara on

We declare the four inputs, two select lines, and the output:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4to1_using_2to1 is
Port (
I0, I1, I2, I3 : in STD_LOGIC;
S0, S1 : in STD_LOGIC;
Y : out STD_LOGIC
);
end mux4to1_using_2to1;

✅ Architecture - Behavioral Modeling

We use signal variables to hold intermediate outputs (Out1 and Out2) from the first two 2:1
MUXes.

architecture Behavioral of mux4to1_using_2to1 is

signal Out1, Out2 : STD_LOGIC;
begin
-- First level 2:1 MUXes
Out1 <= I0 when S0 = '0' else I1; -- Select between I0 and I1
Out2 <= I2 when S0 = '0' else I3; -- Select between I2 and I3

-- Second level 2:1 MUX

Y <= Out1 when S1 = '0' else Out2; -- Select between Out1 and Out2
end Behavioral;
🧪 How It Works
Let’s test a few scenarios:

1. If S1 = 0, S0 = 0:
o Out1 = I0, Out2 = I2, so Y = Out1 = I0
2. If S1 = 0, S0 = 1:
o Out1 = I1, Out2 = I3, so Y = Out1 = I1
3. If S1 = 1, S0 = 0:
o Out1 = I0, Out2 = I2, so Y = Out2 = I2
4. If S1 = 1, S0 = 1:
o Out1 = I1, Out2 = I3, so Y = Out2 = I3

This confirms correct operation of the 4:1 MUX using three 2:1 MUXes.
 ADVANTAGES

1. Modular design – Easier to build complex circuits from simpler blocks.

2. Reusability – 2:1 MUX modules can be reused in other designs.

3. Scalability – Can be extended to 8:1, 16:1 MUX easily.

4. Simplified testing – Smaller units are easier to debug.

5. Logical clarity – Shows how larger circuits are derived from basics.

6. Better learning – Helps understand hierarchical design principles.

7. Consistent structure – Uniform logic gates across design.

8. Less code repetition – Reusable VHDL components.

9. Supports synthesis tools – Tools can optimize modular design.

10. Easier simulation – Small blocks make testbenches simple.

 DISADVANTAGES

1. Increased delay – Signal passes through more stages.

2. More hardware – Requires more logic gates or ICs.

3. Higher power – Extra components consume more energy.

4. Complex routing – More interconnections needed.

5. Larger area – Consumes more chip or board space.

6. Extra signals – Intermediate outputs needed.

7. Slightly complex VHDL – Needs extra signals and logic.

8. Harder timing control – Timing becomes trickier in deeper levels.

9. More prone to glitches – If not designed carefully.

10. Longer simulation time – Due to added components.

 APPLICATION

1. Data routing – Directs one of several data inputs to a single output.

2. Control unit design – Used in CPUs for instruction selection.

3. Arithmetic Logic Unit (ALU) – Helps select specific operations.

4. Communication systems – Combines multiple signals into one line.

5. Signal selection – Chooses between multiple analog or digital signals.

6. Memory address decoding – Helps in selecting memory banks.

7. Function generators – Used to switch between waveform outputs.

8. Embedded systems – For selecting sensor or input data.

9. Industrial automation – Selects control inputs in PLCs and robots.

10. Testing equipment – Used to test multiple signals on a single output channel.
 REFERENCE

1. https://www.elprocus.com/mux-working-types-and-its-applications/

2. https://www.circuitdiagram.co/circuit-diagram-of-4:1-mux/

3. https://allaboutfpga.com/vhdl-4-to-1-mux-

multiplexer/?srsltid=AfmBOoo469pSL19tiCsL4SiBJupksXu-

wxeljSYMeZt6xA7qvqxuhCCQ

4. https://surf-vhdl.com/how-to-implement-digital-mux-in-vhdl/

5. https://stackoverflow.com/questions/56068623/vhdl-for-2to1-

multiplexerhttps://stackoverflow.com/questions/56068623/vhdl-for-2to1-multiplexer

6. https://startingelectronics.org/software/VHDL-CPLD-course/tut4-multiplexers/