Microwave Wideband Synthesizer

with Integrated VCO

Data Sheet ADF4372
FEATURES GENERAL DESCRIPTION
RF output frequency range: 62.5 MHz to 16,000 MHz The ADF4372 allows implementation of fractional-N or integer-N
Fractional-N synthesizer and integer-N synthesizer phase-locked loop (PLL) frequency synthesizers when used with
High resolution 39-bit fractional modulus an external loop filter and an external reference frequency. The
Typical spurious fPFD: −90 dBc wideband microwave voltage controlled oscillator (VCO) design
Integrated rms jitter: 38 fs (1 kHz to 100 MHz) allows frequencies from 62.5 MHz to 16 GHz to be generated.
Normalized phase noise floor: −234 dBc/Hz
The ADF4372 has an integrated VCO with a fundamental output
fPFD operation to 250 MHz
frequency ranging from 4000 MHz to 8000 MHz. In addition, the
Reference input frequency operation to 600 MHz
VCO frequency is connected to a divide by 1, 2, 4, 8, 16, 32, or 64
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
circuit that allows the user to generate radio frequency (RF)
62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x
output frequencies as low as 62.5 MHz at RF8x. A frequency
8,000 MHz to 16,000 MHz output at RF16x
multiplier at RF16x generates from 8 GHz to 16 GHz. RFAUX8x
Lock time approximately 3 ms with automatic calibration
duplicates the frequency range of RF8x or permits direct access to
Lock time <30 μs with autocalibration bypassed, typical
the VCO output. To suppress the unwanted products of frequency
Analog and digital power supplies: 3.3 V typical
multiplication, a harmonic filter exists between the multiplier and
VCO supply voltage: 3.3 V and 5 V
the output stage of RF16x.
RF output mute function
7 mm × 7 mm, 48-terminal LGA package Control of all on-chip registers is through a 3-wire interface.
The ADF4372 operates with analog and digital power supplies
APPLICATIONS ranging from 3.15 V to 3.45 V, and 5 V for the VCO power
Wireless infrastructure (multicarrier global system for supply. The ADF4372 also contains hardware and software
mobile communication (MC-GSM), 5G) power-down modes.
Test equipment and instrumentation
Clock generation
Aerospace and defense
FUNCTIONAL BLOCK DIAGRAM
VCC_CAL VCC_VCO VCC_LDO VCC_X1 VCC_X2 VCC_MUX VCC_3V VDD_NDIV VDD_LS VCC_LDO_3V VCC_REF VDD_PFD VDD_VP

MUX MUXOUT
5-BIT R ÷2
REFP ×2 COUNTER DIVIDER
DOUBLER RS_SW
REFN LOCK
DETECT VCC_REG_OUT
ADF4372
SCLK
CHARGE
SDIO DATA REGISTER FUNCTION PUMP CPOUT
CS LATCH
VTUNE
PHASE
COMPARATOR
TRACKING 8GHz
FILTER TO 16GHz
VCO OUTPUT RF16P
LOW CORE ×2
NOISE STAGE RF16N
LDO INTEGER FRACTION MODULUS
REGISTER REGISTER REGISTER 62.5MHz TO 8000MHz
1, 2, 4, 8, OUTPUT RF8P
16, 32, 64 STAGE RF8N
THIRD-ORDER
FRACTIONAL
INTERPOLATOR MUX
62.5MHz TO 8000MHz
N COUNTER RFAUX8P
MUX OUTPUT
STAGE RFAUX8N
16984-001

GND
Figure 1.

Rev. A Document Feedback

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ADF4372 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 PFD and Charge Pump.............................................................. 19
Applications ....................................................................................... 1 MUXOUT and Lock Detect...................................................... 19
General Description ......................................................................... 1 Double Buffers ............................................................................ 19
Functional Block Diagram .............................................................. 1 VCO ............................................................................................. 20
Revision History ............................................................................... 2 VCO ALC Threshold ................................................................. 20
Specifications..................................................................................... 3 Output Stage................................................................................ 20
Timing Specifications .................................................................. 7 Doubler ........................................................................................ 21
Absolute Maximum Ratings............................................................ 8 Phase Adjust and Spur Optimization by Using
Thermal Resistance ...................................................................... 8 PHASE_WORD .......................................................................... 21

Electrostatic Discharge (ESD) Ratings ...................................... 8 SPI................................................................................................. 21

ESD Caution .................................................................................. 8 Device Setup .................................................................................... 23

Pin Configuration and Function Descriptions ............................. 9 Step 1: Set Up the SPI Interface ................................................ 23

Typical Performance Characteristics ........................................... 11 Step 2: Initialization Sequence .................................................. 23

Theory of Operation ...................................................................... 15 Step 3: Frequency Update Sequence ........................................ 23

RF Synthesizer, a Worked Example.......................................... 15 Applications Information .............................................................. 24

Reference Input Sensitivity........................................................ 15 Power Supplies ............................................................................ 24

Reference Doubler and Reference Divider ............................. 16 PCB Design Guidelines for an LGA Package ......................... 24

Spurious Optimization and Fast Lock ..................................... 16 Output Matching ........................................................................ 24

Optimizing Jitter ......................................................................... 16 Register Summary .......................................................................... 25

Spur Mechanisms ....................................................................... 16 Register Details ............................................................................... 27

Lock Time .................................................................................... 16 Outline Dimensions ....................................................................... 48

Circuit Description ......................................................................... 18 Ordering Guide .......................................................................... 48

Reference Input ........................................................................... 18

RF N Divider ............................................................................... 18
REVISION HISTORY
9/2021—Rev. 0 to Rev. A Changes to Address: 0x23, Default: 0x00, Name: REG0023
Changes to Table 1 ............................................................................ 3 Section and Table 33 ...................................................................... 34
Changes to Table 3 and Table 4 ....................................................... 8 Changes to Address: 0x25, Default: 0x07, Name: REG0025
Added Electrostatic Discharge (ESD) Ratings Section and Section and Table 35 ...................................................................... 35
Table 5; Renumbered Sequentially ................................................. 8 Changes to Address: 0x2A, Default: 0x00, Name: REG002A
Changes to Table 6 ............................................................................ 9 Section and Table 39 ...................................................................... 37
Changes to Figure 29 and INT, FRAC, MOD, and R Counter Changes to Table 40 ....................................................................... 38
Relationship Section ....................................................................... 18 Changed Address: 0x2E, Default: 0x12, Name: REG002E
Added Phase Adjust and Spur Optimization by Using Section to Address: 0x2E, Default: 0x10, Name: REG002E
PHASE_WORD Section ................................................................ 21 Section.............................................................................................. 39
Deleted Output Stage Mute Section ............................................. 22 Changes to Table 42, Address: 0x2E, Default: 0x10, Name:
Added VCO ALC Threshold Section........................................... 20 REG002E Section, and Table 43 ................................................... 39
Changes to Output Stage Section ................................................. 20 Changed Address: 0x2F, Default: 0x94, Name: REG002F Section
Changes to Step 3: Frequency Update Sequence Section .......... 22 to Address: 0x2F, Default: 0x92, Name: REG002F Section ....... 40
Changes to Table 9 .......................................................................... 25 Changes to Table 44 ....................................................................... 40
Changes to Table 26, Table 27, and Table 28 ............................... 31 Changes to Table 50 ....................................................................... 42
Changes to Table 29 ........................................................................ 32 Changes to Table 54 ....................................................................... 43
Changes to Table 30 and Table 31 ................................................ 33
8/2019—Revision 0: Initial Version

Rev. A | Page 2 of 48
Data Sheet ADF4372

SPECIFICATIONS
4.75 V ≤ VCC_VCO ≤ 5.25 V, all other supply pins (AVDD) = 3.3 V ± 5%, GND = 0 V, dBm referred to 50 Ω, TA = whole operating
temperature range, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
REFP AND REFN CHARACTERISTICS
Input Frequency
Single-Ended Mode 10 500 MHz Doubler disabled
Differential Mode 10 600 MHz Doubler disabled
Single-Ended or Differential Mode 10 125 MHz Doubler enabled
Input Sensitivity
Single-Ended Mode 0.4 AVDD V p-p REFP biased at AVDD/2, ac coupling
ensures AVDD/2 bias
Differential Mode 0.4 1.8 V p-p Low voltage differential signal (LVDS) and
low voltage positive emitter coupled
logic (LVPECL) compatible, REFP and REFN
biased at 2.1 V, ac coupling ensures 2.1 V
bias
Input Capacitance
Single-Ended Mode 6.9 pF
Differential Mode 1.4 pF
Input Current ±150 µA Single-ended reference programmed
300 µA Differential reference programmed
Phase Frequency Detector Frequency 160 MHz Fractional mode
(fPFD)
250 MHz Integer mode
CHARGE PUMP
Charge Pump Current, Sink and Source ICP
High Value 5.6 mA
Low Value 0.35 mA
Current Matching 3 % 0.5 V ≤ voltage at the CPOUT pin (VCP) ≤
VDD_VP − 0.5 V
ICP vs. VCP 3 % 0.5 V ≤ VCP ≤ VDD_VP − 0.5 V
ICP vs. Temperature 1.5 % VCP = 2.5 V
LOGIC INPUTS CS, SDIO, SCLK, and CE are 3 V logic
Input High Voltage VINH 1.17 V
Input Low Voltage VINL 0.63 V
Input Current IINH/IINL ±1 µA
Input Capacitance CIN 3.0 pF
LOGIC OUTPUTS
Output High Voltage VOH AVDD V 3.3 V output selected
− 0.4
1.5 1.875 V 1.8 V output selected
Output High Current IOH 500 µA
Output Low Voltage VOL 0.4 V Output low current (IOL) = 500 µA
SYNTHESIZER DIVIDER RANGE
Reference Divider R 1 32 Count
VCO Divider N 16 32,767 Count Integer mode prescaler = 4/5
64 65,535 Count Integer mode prescaler = 8/9
23 32,767 Count Fractional mode prescaler = 4/5
75 65,535 Count Fractional mode prescaler = 8/9

Rev. A | Page 3 of 48
ADF4372 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLIES
Supply Voltage (Except VCO) AVDD 3.15 3.45 V VCC_CAL, VCC_X1, VDD_X1, VCC_X2,
VCC_MUX, VCC_3V, VDD_NDIV, VDD_LS,
VCC_LDO_3V, VCC_REF, VDD_PFD,
VDD_VP are grouped as AVDD and are at
the same voltage
Supply Current (Except VCO) 1 AIDD 190 260 mA All outputs are disabled.

Output Dividers
Divider = 2 14 20 mA Each divide by 2 consumes additional
typical 7 mA current
Divider = 64 50 65 mA
VCO Supply Voltage VCC_VCO
3.15 3.3 3.45 V 3.3 V condition
4.75 5 5.25 V 5 V condition
VCO Supply Current IVCO 80 120 mA 3.3 V condition
135 200 mA 5 V condition
RF8x Supply Current RF8P and RF8N output stage is
programmable, extra current is drawn in
VCC_X1
25 mA −4 dBm setting
39 mA −1 dBm setting
52 mA 2 dBm setting
65 mA 5 dBm setting
RFAUX8x Supply Current 42 mA −4 dBm setting
56 mA −1 dBm setting
70 mA 2 dBm setting
84 mA 5 dBm setting
RF16x Supply Current 90 120 mA
Low Power Sleep Mode 5.1 6.2 mA Hardware power-down 3.3 V VCO case
8 9.5 mA Hardware power-down 5 V VCO case
21.5 25 mA Software power-down 3.3 V VCO case
23.7 28 mA Software power-down 5 V VCO case
RF OUTPUT CHARACTERISTICS
VCO Frequency Range 4000 8000 MHz Fundamental VCO range
RF8P and RF8N Output Frequency 62.5 8000 MHz
RFAUX8P and RFAUX8N Output 62.5 8000 MHz
Frequency
RF16P and RF16N Output Frequency 8000 16000 MHz 2 × VCO output
VCO Sensitivity KV
For 5 V 80 MHz/V VCO frequency = 6 GHz, see Figure 33 for
KV plot
For 3.3 V 60 MHz/V VCO frequency = 6 GHz, see Figure 34 for
KV plot
Frequency Pushing (Open-Loop) 8 MHz/V
Frequency Pulling (Open-Loop) 0.5 MHz Voltage standing wave ratio (VSWR) = 2:1
RF8P and RF8N
30 MHz VSWR = 2:1 RF16x
Maintain Lock Temperature Range 2 125 °C Maintains lock without reprogramming
device

Rev. A | Page 4 of 48
Data Sheet ADF4372
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Harmonic Content
Second Harmonic RF8P and RF8N −25 dBc Fundamental VCO output (RF8x)
−25 dBc Divided VCO output (RF8x)
Third Harmonic RF8P and RF8N −12 dBc Fundamental VCO output RF8x)
−15 dBc Divided VCO output (RF8x)
Second Harmonic RF16P and RF16N −30 dBc Measured at 20 GHz
Third Harmonic RF16P and RF16N −30 dBc Measured at 30 GHz
Fundamental VCO Feedthrough −62 dBc RF16x = 10 GHz, VCO frequency = 5 GHz
−30 dBc RF8P and RF8N = 1 GHz,
VCO frequency = 4 GHz
RF Output Power Maximum Setting 3 7 dBm RF8P = 4 GHz, 7.5 nH inductor to VCC_X1
5 dBm RF8P = 8 GHz, 7.5 nH inductor to VCC_X1
0 dBm RF16x = 8 GHz
4 dBm RF16x = 16 GHz
RF Output Power Variation ±1 dB RF8P and RF8N = 5 GHz
±1 dB RF16x = 10 GHz
RF Output Power Variation (Over ±2 dB RF8x and RFAUX8x = 4 GHz to 8 GHz
Frequency)
±2.5 dB RF16x = 8 GHz to 16 GHz
Level of Signal with RF Output Disabled −50 dBm RF8P and RF8N = 1 GHz
−44 dBm RF8P and RF8N = 8 GHz
−41 dBm RF8P and RF8N = 8 GHz, 5 V VCO case
−75 dBm RF16P = 8 GHz
−55 dBm RF16P = 16 GHz
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise VCO noise in open-loop conditions,
Performance where VCC VCO = 5 V VCC_VCO = 5 V
−117 dBc/Hz 100 kHz offset from 4.0 GHz carrier
−139 dBc/Hz 1 MHz offset from 4.0 GHz carrier
−156 dBc/Hz 10 MHz offset from 4.0 GHz carrier
−112 dBc/Hz 100 kHz offset from 5.7 GHz carrier
−136 dBc/Hz 1 MHz offset from 5.7 GHz carrier
−153 dBc/Hz 10 MHz offset from 5.7 GHz carrier
−109 dBc/Hz 100 kHz offset from 8.0 GHz carrier
−133 dBc/Hz 1 MHz offset from 8.0 GHz carrier
−152 dBc/Hz 10 MHz offset from 8.0 GHz carrier
RF16x Output Phase Noise Performance VCC_VCO = 5 V
where VCC_VCO = 5 V
−106 dBc/Hz 100 kHz offset from 11.4 GHz carrier
−130 dBc/Hz 1 MHz offset from 11.4 GHz carrier
−146 dBc/Hz 10 MHz offset from 11.4 GHz carrier
−103 dBc/Hz 100 kHz offset from 16 GHz carrier
−127 dBc/Hz 1 MHz offset from 16 GHz carrier
−145 dBc/Hz 10 MHz offset from 16 GHz carrier

Rev. A | Page 5 of 48
ADF4372 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Fundamental VCO Phase Noise VCO noise in open-loop conditions,
Performance where VCC_VCO = 3.3 V VCC_VCO = 3.3 V
−116 dBc/Hz 100 kHz offset from 4.0 GHz carrier
−137 dBc/Hz 1 MHz offset from 4.0 GHz carrier
−156 dBc/Hz 10 MHz offset from 4.0 GHz carrier
−111 dBc/Hz 100 kHz offset from 5.7 GHz carrier
−133 dBc/Hz 1 MHz offset from 5.7 GHz carrier
−153 dBc/Hz 10 MHz offset from 5.7 GHz carrier
−109 dBc/Hz 100 kHz offset from 8.0 GHz carrier
−132 dBc/Hz 1 MHz offset from 8.0 GHz carrier
−153 dBc/Hz 10 MHz offset from 8.0 GHz carrier
Normalized Inband Phase Noise Floor
Fractional Channel 4 −233 dBc/Hz
Integer Channel 5 −234 dBc/Hz
Normalized 1/f Noise 6 PN1_f −127 dBc/Hz 10 kHz offset, normalized to 1 GHz
Integrated RMS Jitter 38 fs Wenzel oven controlled crystal oscillators
(OCXO) as the reference frequency input
(REFIN), integer-N mode, fPFD = 245.76 MHz,
300 kHz loop filter bandwidth, 1 kHz to
100 MHz
Integer Boundary Spurs (Filtered) −90 dBc 960 kHz offset from integer channel
Inband Integer Boundary Spur −55 dBc Measured at 5 kHz offset from integer
(Unfiltered) channel
Spurious Signals Due to fPFD −90 dBc
FREQUENCY LOCK TIME 7
Lock Time with Automatic Calibration 3 ms
Lock Time with Automatic Calibration 30 µs
Bypassed
1
TA = 25°C, AVDD = 3.3 V, VCC_VCO = 5.0 V, prescaler = 4/5, reference frequency (fREFP) = 50 MHz, fPFD = 50 MHz, and RF frequency (fRF) = 5001 MHz. RF8x enabled. All RF
outputs are disabled.
2
Guaranteed by design and characterization.
3
RF output power using the EV-ADF4372SD2Z differential outputs combined using a Marki BAL-0036 balun, and measured by a spectrum analyzer with the evaluation
board and cable losses de-embedded. Highest power output selected for RF8P, RF8N, RFAUX8P, and RFAUX8N.
4
Use this value to calculate the phase noise for any application. To calculate inband phase noise performance as seen at the VCO output, use the following formula: −233 +
10log(fPFD) + 20logN. The result is the lowest noise mode for the fractional channel.
5
Use this value to calculate the phase noise for any application. To calculate inband phase noise performance as seen at the VCO output, use the following formula: −234 +
10log(fPFD) + 20logN. The result is the lowest noise mode for the integer channel.
6
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at a radio frequency
(fRF) and at a frequency offset (fOFFSET) is given by PN1_f + 10log(10 kHz/fOFFSET) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
the ADIsimPLL design tool.
7
Lock time is measured for 100 MHz jump with standard evaluation board configuration.

Rev. A | Page 6 of 48
Data Sheet ADF4372
TIMING SPECIFICATIONS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Serial Port Interface (SPI) Timing See Figure 2, Figure 3, and Figure 4
SCLK Frequency fSCLK 50 MHz
SCLK Period tSCLK 20 ns
SCLK Pulse Width High tHIGH 10 ns
SCLK Pulse Width Low tLOW 10 ns
SDIO Setup Time tDS 2 ns
SDIO Hold Time tDH 2 ns
SCLK Falling Edge to SDIO Valid Propagation Delay tACCESS 10 ns
CS Rising Edge to SDIO High-Z tZ 10 ns
CS Fall to SCLK Rise Setup Time tS 2 ns
SCLK Rise to CS Rise Hold Time tH 2 ns
Timing Diagrams
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CS

SCLK

SDIO R/W A14 A13 A1 A0 D7 D61 D1 D0N

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK

SDIO A0 A1 A2 A14 R/W D0N D1 D61 D7

16984-002

Figure 2. SPI Timing, MSB First (Upper) and LSB First (Lower)

tS tSCLK tH
CS
tHIGH tLOW
SCLK

tDS tDH
16984-003

SDIO R/W A14 A13 A0 D7 D6 D1 D0

Figure 3. SPI Write Operation Timing

tS tSCLK
CS
tHIGH tLOW
SCLK

tDS tACCESS
tDH tZ
16984-004

SDIO R/W A14 A2 A1 A0 D7 D6 D1 D0

Figure 4. SPI Read Operation Timing

CS

SCLK DON’T DON’T

CARE CARE

DON’T DON’T
SDIO R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16984-005

CARE CARE

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – ...) DATA

Figure 5. 3-Wire, MSB First, Descending Data, Streaming

Rev. A | Page 7 of 48
ADF4372 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. THERMAL RESISTANCE
Table 3. Thermal performance is directly linked to printed circuit board
Parameter Rating (PCB) design and operating environment. Close attention to
PCB thermal design is required.
AVDD Rails to GND1 −0.3 V to +3.6 V
AVDD Rails to Each Other −0.3 V to +0.3 V θJA is the natural convection, junction to ambient thermal resistance
VCC_VCO to GND1 −0.3 V to +5.5 V measured in a one cubic foot sealed enclosure. θJC is the junction to
VCC_VCO to AVDD −0.3 V to AVDD + 2.8 V case thermal resistance.
CPOUT to GND1 −0.3 V to AVDD + 0.3 V
Table 4. Thermal Resistance
VTUNE to GND −0.3 V to AVDD + 0.3 V
Package Type θJA θJC, TOP θJC, BOTTOM Unit
Digital Input and Output Voltage to GND1 −0.3 V to AVDD + 0.3 V
Analog Input and Output Voltage to GND1 −0.3 V to AVDD + 0.3 V CC-48-41 25 14.4 3.7 °C/W
REFP and REFN to GND1 −0.3 V to AVDD + 0.3 V 1
Test Condition 1: thermal impedance simulated values are based on JESD51
REFP to REFN ±2.1 V standard.
Temperature ELECTROSTATIC DISCHARGE (ESD) RATINGS
Operating Range −40°C to +105°C
The following ESD information is provided for handling of
Storage Range −65°C to +125°C
ESD-sensitive devices in an ESD protected area only.
Maximum Junction 125 °C
Reflow Soldering Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Peak 260°C Charged devices model per ANSI/ESDA/JEDEC JS-002.
Time at Peak 30 sec
ESD Ratings for ADF4372
Transistor Count
Table 5. ADF4372, 48-Terminal LGA
Complementary Metal-Oxide 131,439
Semiconductor (CMOS) ESD Model Withstand Threshold Class
Bipolar 4063 HBM, All Pins 4.0 kV 3A
CDM, All Pins 750 V C2B
1
GND = 0 V.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress rating ESD CAUTION
only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.

Rev. A | Page 8 of 48
Data Sheet ADF4372

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC_LDO_3V
VDD_PFD
VCC_REF

MUXOUT
VDD_VP

REFN
REFP

TEST
GND

GND

GND
CE
48 47 46 45 44 43 42 41 40 39 38 37

GND 1 36 GND
CPOUT 2 35 SCLK
RS_SW 3 34 SDIO
VCC_CAL 4 33 CS
VTUNE 5 32 VDD_LS
VCC_REG_OUT 6 ADF4372 31 VDD_NDIV
VCC_VCO 7 TOP VIEW 30 VCC_3V
VCC_LDO 8 (Not to Scale) 29 VCC_MUX
GND 9 28 GND
NC 10 27 RF16N
NC 11 26 RF16P
GND 12 25 GND

13 14 15 16 17 18 19 20 21 22 23 24

GND

GND

GND
RF8P
RF8N
VCC_X1
VDD_X1
VCC_X1
VDD_X1

VCC_X2
RFAUX8P
RFAUX8N
NOTES

16984-006
1. THE LAND GRID ARRAY (LGA) HAS AN EXPOSED PAD
THAT MUST BE SOLDERED TO A METAL PLATE ON
THE PCB FOR MECHANICAL REASONS AND TO GND.

Figure 6. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
1, 9, 12, 13, 20, GND Ground Return.
24, 25, 28, 36,
37, 42, 48
2 CPOUT Charge Pump (CP) Output. When enabled, this output provides ±ICP to the external loop filter. The
output of the loop filter is connected to VTUNE to drive the internal VCO.
3 RS_SW Factory Test Pin. Leave floating.
4 VCC_CAL Power Supply for Internal Calibration Monitor Circuit. The voltage on this pin ranges from 3.15 V to
3.45 V. VCC_CAL must have the same value as AVDD, nominally 3.3 V.
5 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering
the CPOUT output voltage.
6 VCC_REG_OUT VCO Supply Regulator Out. The output supply voltage of the VCO regulator is available at this pin, and
must be decoupled to GND with a 10 μF capacitor and shorted to the VCC_VCO pin. Leave this pin
open if an external LDO regulator is connected to VCC_VCO.
7 VCC_VCO Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling
capacitors to the analog ground plane as close to this pin as possible. For optimal performance, this
supply must be clean and have low noise.
8 VCC_LDO Supply Pin to the VCO Regulator. If the internal regulator is used, connect the voltage supply to
VCC_LDO. The voltage on this pin ranges from 4.75 V to 5.25 V. If the external regulator is used, short
this pin to VCC_VCO.
10, 11 NC No Connect.
14, 16 VCC_X1 Power Supply for the Main RF Output. The voltage on this pin must have the same value as AVDD.
15, 17 VDD_X1 Digital Supply for the Main RF Circuit. The voltage on this pin must have the same value as AVDD.
18 RF8P Main RF Output. AC couple to the next stage. The output level is programmable. The VCO fundamental
output or a divided down version is available. This pin can be powered off when not in use. If unused,
this pin can be left open.
19 RF8N Complementary Main RF Output. AC couple this pin to the next stage. The output level is programmable.
The VCO fundamental output or a divided down version is available. This pin can be powered off when
not in use. If unused, this pin can be left open.
21 VCC_X2 Power Supply for the Doubled RF Output. The voltage on this pin must have the same value as AVDD.

Rev. A | Page 9 of 48
ADF4372 Data Sheet
Pin No. Mnemonic Description
22 RFAUX8P Auxiliary RF Output. AC couple to the next stage. This pin can be powered off when not in use. If unused,
this pin can be left open.
23 RFAUX8N Complementary Auxiliary RF Output. AC couple this pin to the next stage. This pin can be powered off
when not in use. If unused, this pin can be left open.
26 RF16P Doubled VCO Output. AC or dc couple this pin to the next stage. This pin can be powered off when not
in use. If unused, this pin can be left open.
27 RF16N Complementary Doubled VCO Output. AC or dc couple this pin to the next stage. This pin can be
powered off when not in use. If unused, this pin can be left open.
29 VCC_MUX Power Supply for the VCO Mux. The voltage on this pin must have the same value as AVDD.
30 VCC_3V Analog Power Supply. The voltage on this pin must have the same value as AVDD.
31 VDD_NDIV N Divider Power Supply. The voltage on this pin must have the same value as AVDD.
32 VDD_LS Level Shifter Power Supply. The voltage on this pin must have the same value as AVDD.
33 CS Chip Select, CMOS Input. When CS goes high, the data stored in the shift register is loaded into the
register that is selected by the address bits.
34 SDIO Serial Data Input Output. This input is a high impedance CMOS input.
35 SCLK Serial Clock Input. Data is clocked into the 24-bit shift register on the clock rising (or falling) edge. This
input is a high impedance CMOS input.
38 VCC_LDO_3V Regulator Input for 1.8 V Digital Logic. The voltage on this pin must have the same value as AVDD.
39 CE Chip Enable. Connect to 3.3 V or AVDD.
40 TEST Factory Test Pin. Connect this pin to ground.
41 MUXOUT Mux Output. The mux output allows the digital lock detect, the analog lock detect, scaled RF, or the
scaled reference frequency to be externally accessible. This pin can be programmed to output the
register settings in 4-wire SPI mode.
43 REFP Reference Input. If driving the device with a single-ended reference, ac couple the signal to the REFP
pin.
44 REFN Complementary Reference Input. If unused, ac couple this pin to GND. REFP and REFN must be ac-
coupled if driven differentially. If driven single-ended, the reference signal must be connected to REFP,
and the REFN must be ac-coupled to GND. In differential configuration, the differential impedance is
100 Ω.
45 VCC_REF Power Supply to the Reference Buffer. The voltage on this pin must have the same value as AVDD.
46 VDD_PFD Power Supply to the Phase Frequency Detector (PFD). The voltage on this pin must have the same
value as AVDD.
47 VDD_VP Charge Pump Power Supply. The voltage on this pin must have the same value as AVDD. A 1 μF
decoupling capacitor to GND must be included to minimize spurious signals.
EP Exposed Pad. The land grid array (LGA) has an exposed pad that must be soldered to a metal plate on
the PCB for mechanical reasons and to the GND.

Rev. A | Page 10 of 48
Data Sheet ADF4372

TYPICAL PERFORMANCE CHARACTERISTICS

–20 –20
M1 1kHz –60.29dBc/Hz M1 1kHz –49.64dBc/Hz
–30 M2 10kHz –89.95dBc/Hz –30 M2 10kHz –79.83dBc/Hz
M3 100kHz –117.9dBc/Hz M3 100kHz –106.27dBc/Hz
–40 M4 1MHz –139.1dBc/Hz –40 M1 M4 1MHz –130.23dBc/Hz
M5 10MHz –156.3dBc/Hz M5 10MHz –147.45dBc/Hz
–50 M1 M6 30MHz –160.95dBc/Hz –50 M6 30MHz –151.39dBc/Hz
M7 95MHz –162.86dBc/Hz M7 95MHz –155.61dBc/Hz
–60 –60

PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

–70 –70 M2

–80 M2 –80
–90 –90
M3
–100 –100
–110 M3 –110
–120 –120 M4
–130 M4 –130
–140 –140 M5
M6
M7
–150 M5 –150
M6 M7
–160 –160
–170 –170

16984-010
16984-007
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 7. Open-Loop VCO Phase Noise, 4.0 GHz, VCC_VCO = 5 V Figure 10. Open-Loop VCO Phase Noise at RF16x Output, 11.4 GHz,
VCC_VCO = 5 V
–20 –20
M1 1kHz –55.29dBc/Hz M1 1kHz –48.74dBc/Hz
–30 M2 10kHz –85.75dBc/Hz –30 M2 10kHz –78.16dBc/Hz
M3 100kHz –112.32dBc/Hz M3 100kHz –103.95dBc/Hz
M4 1MHz –136.05dBc/Hz –40 M1 M4 1MHz –127.04dBc/Hz
–40
M1 M5 10MHz –155.3dBc/Hz M5 10MHz –146.07dBc/Hz
–50 M6 30MHz –161.75dBc/Hz –50 M6 30MHz –151.02dBc/Hz
M7 95MHz –161.11dBc/Hz M7 95MHz –154.34dBc/Hz
–60 –60
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)

M2
–70 –70
M2
–80 –80
–90 –90
M3
–100 M3 –100
–110 –110
–120 –120 M4
M4
–130 –130
M5
–140 –140 M6
M5 M7
–150 M6 M7 –150
–160 –160
–170 –170
16984-008

16984-011
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 8. Open-Loop VCO Phase Noise, 5.7 GHz, VCC_VCO = 5 V Figure 11. Open-Loop VCO Phase Noise at RF16x Output, 16.0 GHz,
VCC_VCO = 5 V
–20 –40
M1 1kHz –54.23dBc/Hz +105°C
–30 M2 10kHz –84.17dBc/Hz
M3 100kHz –110.13dBc/Hz +25°C
–40 M4 1MHz –133.29dBc/Hz –60 –40°C
M1 M5 10MHz –153.36dBc/Hz
–50 M6 30MHz –159.75dBc/Hz
M7 95MHz –163.7dBc/Hz
–60
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)

–80
–70
M2
–80
–100
–90
–100 M3
–120
–110
–120
M4
–130 –140

–140
M5
–150 M6 –160
M7
–160
–170 –180
16984-012
16984-009

100 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz) FREQUENCY OFFSET (Hz)

Figure 9. Open-Loop VCO Phase Noise, 8.0 GHz, VCC_VCO = 5 V Figure 12. Open-Loop VCO Phase Noise over Temperature, 8.0 GHz,
VCC_VCO = 5 V

Rev. A | Page 11 of 48
ADF4372 Data Sheet
20 –35
DE-EMBEDDED MEASUREMENT

INTEGER BOUNDARY SPURIOUS SWEEP (dBc)

RAW MEASUREMENT –45

15 –55
OUTPUT POWER (dBm)

–65

10 –75

–85

5 –95

–105

0 –115
153.6MHz
–125 122.88MHz
61.44MHz
–5 –135

16984-013

16984-016
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 3.5 4.5 5.5 6.5 7.5 8.5
FREQUENCY (GHz) CARRIER FREQUENCY (GHz)

Figure 13. RF8P and RF8N Output Power, De-Embedded Board and Cable Figure 16. Integer Boundary Spurious Sweep vs. Carrier Frequency,
Measurement, Combined Using Balun (7.4 nH Inductors, 10 pF AC Coupling fPFD = 61.44 MHz, 122.88 MHz, and 153.6 MHz,
Capacitors Limit Power at Low Frequencies) Loop Filter Bandwidth = 100 kHz
–70 6

–75 4

–80
PFD SPUR LEVEL (dBc)

OUTPUT POWER (dBm) 2

–85
0
–90
–2
–95

–4
–100

–105 PFD FREQUENCY = 153.6MHz –6

PFD FREQUENCY = 122.88MHz DE-EMBEDDED MEASUREMENT
PFD FREQUENCY = 61.44MHz RAW MEASUREMENT
–110 –8
16984-014

16984-017
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 7 8 9 10 11 12 13 14 15 16 17
CARRIER FREQUENCY (GHz) FREQUENCY (GHz)

Figure 14. PFD Spurious Sweep, fPFD = 61.44 MHz, Loop Filter Bandwidth = Figure 17. RF16P and RF16N Output Power, De-Embedded Board and Cable
100 kHz Measurement, Combined Using Balun
0 –35
SECOND HARMONIC +105°C, VCO SUPPLY = 5.30V
THIRD HARMONIC +105°C, VCO SUPPLY = 4.80V
+25°C, VCO SUPPLY = 5.05V
–10 FOURTH HARMONIC –40 –40°C, VCO SUPPLY = 5.30V
FIFTH HARMONIC –40°C, VCO SUPPLY = 4.80V
SIXTH HARMONIC
FEEDTHROUGH POWER (dBc)

–20 –45
HARMONIC LEVEL (dBc)

–30 –50

–40 –55

–50 –60

–60 –65

–70 –70

–80 –75
16984-015

16984-018

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 7 8 9 10 11 12 13 14 15 16 17
CARRIER FREQUENCY (GHz) CARRIER FREQUENCY (GHz)

Figure 15. RF8P and RF8N Output Harmonics, De-Embedded Board and Figure 18. RF16P and RF16N VCO Feedthrough, De-Embedded Board and
Cable Measurement, Combined Using Balun Cable Measurement, Combined Using Balun

Rev. A | Page 12 of 48
Data Sheet ADF4372
–35 0.075
+105°C, VCO SUPPLY = 5.30V 1kHz TO 20MHz
+105°C, VCO SUPPLY = 4.80V
+25°C, VCO SUPPLY = 5.05V 0.070 12kHz TO 20MHz
–40 –40°C, VCO SUPPLY = 5.30V
–40°C, VCO SUPPLY = 4.80V
0.065
FEEDTHROUGH POWER (dBc)

–45
0.060
–50

JITTER (ps)
0.055
–55
0.050
–60
0.045
–65
0.040
–70
0.035

–75 0.030

–80 0.025

16984-019

16984-027
7 8 9 10 11 12 13 14 15 16 17 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
CARRIER FREQUENCY (GHz) FREQUENCY (GHz)

Figure 19. RF16P and RF16N VCO × 3 Feedthrough, De-Embedded Board and Figure 22. RMS Jitter, Fractional-N, fPFD = 153.6 MHz, VCC_VCO = 5 V
Cable Measurement, Combined Using Balun
0 0.075
SECOND HARMONIC (4 × VCO)
THIRD HARMONIC (6 × VCO)
0.070
–10 5/2TH HARMONIC (5 × VCO)
0.065
–20
HARMONIC LEVEL (dBc)

0.060
–30
JITTER (ps)
0.055

–40 0.050

0.045
–50
0.040
–60
0.035
–70
0.030

–80 0.025
16984-020

16984-028
7 8 9 10 11 12 13 14 15 16 17 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
CARRIER FREQUENCY (GHz) FREQUENCY (GHz)

Figure 20. RF16P and RF16N Output Harmonics, De-Embedded Board and Figure 23. RMS Jitter Integrated from 1 kHz to 100 MHz, Fractional-N,
Cable Measurement, Combined Using Balun fPFD = 153.6 MHz, VCC_VCO = 3.3 V
0.075 –30
1kHz TO 100MHz DE-EMBEDDED MEASUREMENT
0.070 12kHz TO 20MHz –35 RAW MEASUREMENT

0.065 –40
OUTPUT POWER (dBm)

0.060 –45
JITTER (ps)

0.055 –50

0.050 –55

0.045 –60

0.040 –65

0.035 –70

0.030 –75

0.025 –80
16984-026

16984-050

4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 21. RMS Jitter, Integer-N, fPFD = 245.76 MHz, Loop Filter Bandwidth = Figure 24. RF8P and RF8N Output Power When Disabled, De-Embedded
220 kHz, VCC_VCO = 5 V Board and Cable Measurement, Combined Using Balun

Rev. A | Page 13 of 48
ADF4372 Data Sheet
–40
DE-EMBEDDED MEASUREMENT
RAW MEASUREMENT

–50
OUTPUT POWER (dBm)

–60

–70

–80

–90

–100

16984-051
7 8 9 10 11 12 13 14 15 16 17
FREQUENCY (GHz)

Figure 25. RF16P and RF16N Output Power When Disabled, De-Embedded
Board and Cable Measurement, Combined Using Balun

Rev. A | Page 14 of 48
Data Sheet ADF4372

THEORY OF OPERATION
RF SYNTHESIZER, A WORKED EXAMPLE The values used in this worked example are as follows:
Use the following equations to program the ADF4372 N = fVCO_OUT/fPFD = 4225.6 MHz/61.44 MHz =
synthesizer: 68.7760416666666667 (3)
 FRAC2  where:
 FRAC1 +
= MOD2  × f PFD (1) N is the desired value of the feedback counter, N.
fRFOUT  INT + 
 MOD1  RF Divider fVCO_OUT is the output frequency of the VCO voltage controlled
  oscillator without using the output divider.
where: fPFD is the frequency of the phase frequency detector.
fRFOUT is the RF output frequency. INT = INT(VCO frequency/fPFD) = 68 (4)
INT is the integer division factor.
FRAC1 is the fractionality. FRAC = 0.7760416666666667 (5)
FRAC2 is the auxiliary fractionality. where:
MOD2 is the auxiliary modulus. FRAC is the fractional part of the N.
MOD1 is the fixed 25-bit modulus. MOD1 = 33,554,432 (6)
RF Divider is the output divider that divides down the VCO
frequency. FRAC1 = INT(MOD1 × FRAC) = 26,039,637 (7)

fPFD = REFIN × ((1 + D)/(R × (1 + T))) (2) Remainder = 0.3333333333 or 1/3 (8)

where: MOD2 = fPFD/GCD(fPFD, fCHSP) =

REFIN is the reference frequency input. 61.44 MHz/GCD(61.44 MHz, 200 kHz) = 1536 (9)
D is the REFIN doubler bit. where:
R is the reference division factor. GCD is the greatest common divider operant.
T is the reference divide by 2 bit (0 or 1). FRAC2 = Remainder × 1536 = 512 (10)
For example, in a universal mobile telecommunication system From Equation 2,
(UMTS) where a 2112.8 MHz fRFOUT is required, a 122.88 MHz
REFIN is available. The ADF4372 VCO operates in the frequency fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz (11)
range of 4 GHz to 8 GHz. Therefore, the RF divider of 2 must be 2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +
used (VCO frequency = 4225.6 MHz, fRFOUT = VCO frequency/RF FRAC2/MOD2)/225))/2 (12)
divider = 4225.6 MHz/2 = 2112.8 MHz). where:
The feedback path is also important. In this example, the VCO INT = 68.
output is fed back before the output divider (see Figure 26). FRAC1 = 26,039,637.
In this example, the 122.88 MHz reference signal is divided by FRAC2 = 512.
2 to generate a fPFD of 61.44 MHz. The desired channel spacing MOD2 = 1536.
is 200 kHz. RF Divider = 2.
fPFD
RFOUT
REFERENCE INPUT SENSITIVITY
PFD VCO ÷2
The slew rate of the input reference signal significantly affects
the performance. The device is functional with signals of very
16984-038

N low amplitude down to 0.4 V p-p and with a slew rate of 21 V/μs.
DIVIDER
However, the optimal performance is achieved with slew rates
Figure 26. Loop Closed Before Output Divider as high as 1000 V/μs. Achieving this slew rate with sinusoidal
waves requires high amplitudes and may not be possible at
low frequencies. The jitter and phase noise performance of
the ADF4372 is shown in Figure 27 and Figure 28 for PFD
frequencies of 250 MHz and 100 MHz, respectively. A high
performance square wave signal with a high slew rate is
recommended as the reference input signal to achieve
the best performance.

Rev. A | Page 15 of 48
ADF4372 Data Sheet
65 –100
Additional Optimization on Loop Filter
60
–102 The PLL filter is designed to find an optimum bandwidth for
the reference, PFD, and VCO noise, depending on the system
PHASE NOISE AT 10kHz
requirements. In addition to this design, when the Σ-Δ modulator

PHASE NOISE (dBm/Hz)

–104
PHASE NOISE AT 1kHz
55 1kHz TO 100MHz
12kHz TO 20MHz (SDM) is enabled, further optimization may be necessary to filter
JITTER (fS)

–106
50
SDM noise.
–108 Reducing Σ-Δ Modulator Noise
45
–110 In fractional mode, SDM noise becomes apparent and starts
to contribute to overall phase noise. This noise can be reduced
40
–112 to insignificant levels by using a series resistor between the
CPOUT pin and the loop filter. Place this resistor close to the
35 –114
CPOUT pin. A reasonable resistor value does not affect the loop

16984-039
–6 –4 –2 0 2 4 6 8 10 12
REFERENCE POWER (dBm) bandwidth and phase margin of the designed loop filter. In most
Figure 27. Jitter and Phase Noise, fPFD = 250 MHz cases, 91 Ω gives the best results. This resistor is not required in
105 integer mode (SDM not enabled) or when a narrow-band loop
PHASE NOISE AT 10kHz
PHASE NOISE AT 1kHz
–96 filter is used (SDM noise attenuated).
95 1kHz TO 100MHz
12kHz TO 20MHz –87 SPUR MECHANISMS
This section describes the two different spur mechanisms that
PHASE NOISE (dBm/Hz)

85
–100
arise with a fractional-N synthesizer and how to minimize them
JITTER (fS)

75
–102 in the ADF4372.
65
–104 Integer Boundary Spurs
55
One mechanism for fractional spur creation is the interactions
–106
between the RF VCO frequency and the reference frequency.
45 –108 When these frequencies are not integer related (which is the
purpose of a fractional-N synthesizer), spur sidebands appear on
35 –110
the VCO output spectrum at an offset frequency that corresponds
16984-040

–6 –4 –2 0 2 4 6 8 10 12
REFERENCE POWER (dBm) to the beat note or the difference in frequency between an integer
Figure 28. Jitter and Phase Noise, fPFD = 100 MHz multiple of the reference and the VCO frequency. These spurs
are attenuated by the loop filter and are more noticeable on
REFERENCE DOUBLER AND REFERENCE DIVIDER channels close to integer multiples of the reference where
The on-chip reference doubler allows the input reference signal the difference frequency can be inside the loop bandwidth.
to be doubled. The doubler is useful for increasing the PFD
Reference Spurs
comparison frequency. To improve the noise performance of
the system, increase the PFD frequency. Doubling the PFD Reference spurs are generally not a problem in fractional-N
frequency typically improves noise performance by 3 dB. synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
The reference divide by 2 divides the reference signal by 2,
that bypasses the loop can cause a problem. Feedthrough of low
resulting in a 50% duty cycle PFD frequency.
levels of on-chip reference switching noise through the prescaler
SPURIOUS OPTIMIZATION AND FAST LOCK back to the VCO can result in reference spur levels as high as
Narrow loop bandwidths can filter unwanted spurious signals. −100 dBc.
However, these bandwidths typically have a long lock time. A LOCK TIME
wider loop bandwidth achieves faster lock times, but can lead
The PLL lock time divides into a number of settings. The total lock
to increased spurious signals inside the loop bandwidth.
time for changing frequencies is the sum of the four separate times:
OPTIMIZING JITTER synthesizer lock, VCO band selection, automatic level calibration
For lowest jitter applications, use the highest possible PFD (ALC), and PLL settling time.
frequency to minimize the contribution of inband noise from the
PLL. Set the PLL filter bandwidth such that the inband noise of the
PLL intersects with the open-loop noise of the VCO, minimizing
the contribution of both to the overall noise.
Use the ADIsimPLL design tool for this task.

Rev. A | Page 16 of 48
Data Sheet ADF4372
Synthesizer Lock ALC
The synthesizer lock timeout ensures that the VCO calibration Use the ALC function to choose the correct bias current in the
DAC, which forces the VCO tune voltage (VTUNE), has settled ADF4372 VCO core. The duration required for VCO bias
to a steady value for the band select circuitry. The SYNTH_LOCK_ voltage to settle for each step is set by the following equation:
TIMEOUT bit and the TIMEOUT bits select the length of time
VCO _ ALC _ TIMEOUT × 1024 + TIMEOUT
the DAC is allowed to settle to the final voltage before the VCO (16)
f PFD
calibration process continues to the next phase (VCO band
selection). where:
The PFD frequency is the clock for this logic, and the duration VCO_ALC_TIMEOUT and TIMEOUT are programmed in
is set using the following equation: Address 0x34, Address 0x32, and Address 0x31.

SYNTH _ LOCK _ TIMEEOUT × 1024 + TIMEOUT The calculated time must be greater than or equal to 50 µs.
(13)
f PFD The total ALC takes 63 steps. Calculate the total duration for
ALC as follows:
where:
SYNTH_LOCK_TIMEOUT is programmed in Address 0x33. VCO _ ALC _ TIMEOUT × 1024 + TIMEOUT
63 × (17)
TIMEOUT is programmed in Address 0x31 and Address 0x32. f PFD
The calculated time must be greater than or equal to 20 µs. The minimum value for VCO_ALC_TIMEOUT is 2 and the
For the SYNTH_LOCK_TIMEOUT bit, the minimum value is maximum value is 31.
2 and the maximum value is 31. For the TIMEOUT bits, the PLL Settling Time
minimum value is 2 and the maximum value is 1023. The time taken for the loop to settle is inversely proportional to
VCO Band Selection the low-pass filter bandwidth. The settling time is accurately
The VCO_BAND_DIV bits (programmed in Address 0x30) and modeled in the ADIsimPLL design tool.
fPFD are used to generate the VCO band selection clock Lock Time, a Worked Example
as follows: Assume that fPFD = 61.44 MHz,
f PFD VCO_BAND_DIV = Ceiling(fPFD/2,400,000) = 26 (18)
f BSC = (14)
VCO _ BAND _ DIV
where Ceiling() rounds up to the nearest integer.
The calculated time must be less than or equal to 2.4 MHz.
SYNTH_LOCK_TIMEOUT × 1024 + TIMEOUT > 1228.8 (19)
16 clock cycles are required for one VCO core and band
VCO_ALC_TIMEOUT × 1024 + TIMEOUT > 3072 (20)
calibration step and the total band selection process takes
11 steps, resulting in the following equation: There are several suitable values that meet these criteria. By
considering the minimum specifications, the following values
16 × VCO _ BAND _ DIV are the most suitable:
11 × (15)
f PFD
• SYNTH_LOCK_TIMEOUT = 2 (minimum value)
The minimum value for VCO_BAND_DIV is 1 and the • VCO_ALC_TIMEOUT = 3
maximum value is 255. • TIMEOUT = 2
Much faster lock times than those detailed in this data sheet are
possible by bypassing the calibration processes. Contact an
Analog Devices, Inc., sales representative for more information.

Rev. A | Page 17 of 48
ADF4372 Data Sheet

CIRCUIT DESCRIPTION
REFERENCE INPUT
RF N COUNTER
Figure 29 shows the reference input stage. The reference input
can accept both single-ended and differential signals. Use the FROM
VCO OUTPUT OR N COUNTER
TO PFD

reference mode bit (Bit 6 in Address 0x22) to select the signal. OUTPUT DIVIDERS
THIRD-ORDER
To use a differential signal on the reference input, program this FRACTIONAL
INTERPOLATOR
bit high. In this case, SW1 and SW2 are open, SW3 and SW4
are closed, and the current source that drives the differential pair of
INT FRAC1 FRAC2 MOD2
transistors switches on. The differential signal is buffered, and VALUE VALUE VALUE VALUE

the signal is provided as an emitter coupled logic (ECL) to the

16984-030
CMOS buffer.
When a single-ended signal is used as the reference, connect the Figure 30. RF N Divider
reference signal to REFP and program Bit 6 in Address 0x22
INT, FRAC, MOD, and R Counter Relationship
to 0. In this case, SW1 and SW2 are closed, SW3 and SW4 are
open, and the current source that drives the differential pair of The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
transistors switches off. conjunction with the R counter, make it possible to generate
output frequencies that are spaced by fractions of fPFD. For more
For optimum integer boundary spur and phase noise performance, information, see the RF Synthesizer, a Worked Example section.
use the single-ended setting for all references up to 500 MHz
(even if using a differential signal). Use the differential setting Calculate fVCO_OUT using the following equation:
for reference frequencies greater than 500 MHz. fVCO_OUT = fPFD × N (21)
REFERENCE
INPUT MODE Calculate fPFD using the following equation:
1+ D (22)
85kΩ =
f PFD REFIN ×
R × (1 + T )
SW2
BUFFER
SW1 where:
SW3
TO REFIN is the reference frequency input.
R COUNTER
MULTIPLEXER D is the REFIN doubler bit.
R is the preset divide ratio of the binary 5-bit programmable
AV DD
reference counter.
ECL TO CMOS T is the REFIN divide by 2 bit (0 or 1)
BUFFER

REFP
Calculate the desired value of the feedback counter N using the
following equation:
FRAC2
REFN FRAC1 +
=
N INT + MOD2 (23)
50Ω 50Ω
MOD1
SW4
where:
16984-029

BIAS
GENERATOR
INT is the 16-bit integer value. In integer mode, INT = 20 to
Figure 29. Reference Input Stage, Differential Mode 32,767 for the 4/5 prescaler, and 64 to 65,535 for the 8/9
prescaler. In fractional mode, INT= = 23 to 32,767 for the 4/5
RF N DIVIDER prescaler, and 75 to 65,535 for the 8/9 prescaler.
The RF N divider allows a division ratio in the PLL feedback FRAC1 is the numerator of the primary modulus (0 to 33,554,431).
path. Determine the division ratio by the INT, FRAC1, FRAC2, FRAC2 is the numerator of the 14-bit auxiliary modulus
and MOD2 values that this divider comprises. (0 to 16,383).
MOD2 is the programmable, 14-bit auxiliary fractional
modulus (2 to 16,383).
MOD1 is a 25-bit primary modulus with a fixed value of
225 = 33,554,432.

Rev. A | Page 18 of 48
Data Sheet ADF4372
These calculations result in a very low frequency resolution HIGH D1 Q1
UP

with no residual frequency error. To apply Equation 23, perform U1

the following steps: +IN CLR1

1. Calculate N by dividing VCOOUT/fPFD. The integer value of

this number forms INT. DELAY U3 CHARGE CP
PUMP
2. Subtract INT from the full N value.
3. Multiply the remainder by 225. The integer value of this
number forms FRAC1.
CLR2
4. Calculate MOD2 based on the channel spacing (fCHSP) HIGH D2 Q2
DOWN

using the following equation: U2

16984-031
–IN
MOD2 = fPFD/GCD(fPFD, fCHSP) (24)
Figure 31. PFD Simplified Schematic
where:
GCD(fPFD, fCHSP) is the greatest common divisor of the MUXOUT AND LOCK DETECT
PFD frequency and the channel spacing frequency. The output multiplexer on the ADF4372 allows the user to
fCHSP is the desired channel spacing frequency. access various internal points on the chip. Figure 32 shows the
5. Calculate FRAC2 using the following equation: MUXOUT section in block diagram form.
AVDD
FRAC2 = ((N – INT) × 225 – FRAC1) × MOD2 (25)
The FRAC2 and MOD2 fraction result in outputs with zero
frequency error for channel spacing when THREE-STATE OUTPUT
AVDD
fPFD/GCD(fPFD, fCHSP) = MOD2 < 16,383 (26)
R DIVIDER OUTPUT
If zero frequency error is not required, the MOD1 and N DIVIDER OUTPUT MUX CONTROL MUXOUT
MOD2 denominators operate together to create a 39-bit ANALOG LOCK DETECT
resolution modulus. DIGITAL LOCK DETECT

RESERVED
Integer-N Mode
When FRAC1 and FRAC2 are equal to 0, the synthesizer

16984-032
operates in integer-N mode. It is recommended that the DIGITAL
GROUND
SD_EN_FRAC0 bit in Address 0x2B be set to 1 to disable the
Figure 32. MUXOUT Schematic
SDMs, which gives an improvement in the inband phase
noise and reduces any additional Σ-Δ noise. DOUBLE BUFFERS
R Counter The main fractional value (FRAC1), auxiliary modulus value
The 5-bit R counter allows the input reference frequency (input (MOD2), auxiliary fractional value (FRAC2), reference doubler,
to REFP and REFN) to be divided down to produce the reference reference divide by 2 (RDIV2), R counter value, and charge pump
clock to the PFD. Division ratios from 1 to 32 are allowed. current setting are double buffered in the ADF4372. Two events
must occur before the ADF4372 uses a new value for any of the
PFD AND CHARGE PUMP double buffered settings. First, the new value must latch into the
The PFD takes inputs from the R counter and N counter and device by writing to the appropriate register, and second, a new
produces an output proportional to the phase and frequency write to Address 0x10 must be performed.
difference between them. Figure 31 is a simplified schematic For example, to ensure that the modulus value loads correctly,
of the PFD. The PFD includes a fixed delay element that sets the Address 0x10 must be written to every time that the modulus
width of the antibacklash pulse. This pulse ensures that there is no value updates.
dead zone in the PFD transfer function and provides a consistent
reference spur level. Set the phase detector polarity to positive
on this device because of the positive tuning of the VCO.

Rev. A | Page 19 of 48
ADF4372 Data Sheet
VCO 100

90
The VCO in the ADF4372 consists of four separate VCO cores:
Core A, Core B, Core C, and Core D, each of which uses 256 80

VCO SENSITIVITY, KV (MHz/V)

overlapping bands, which allows the device to cover a wide 70

frequency range without large VCO sensitivity (KV) and without 60

resultant poor phase noise and spurious performance. 50

The correct VCO and band are chosen automatically by the 40

VCO and band select logic whenever Address 0x10 is updated 30
and automatic calibration is enabled. The VCO tune voltage is
20
disconnected from the output of the loop filter and is connected
to an internal reference voltage. 10

0
The R counter output is used as the clock for the band select

16984-034
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
logic. After band selection, normal PLL action resumes. The FREQUENCY (GHz)

nominal value of KV is 50 MHz/V when the N divider is driven Figure 34. VCO Sensitivity, KV vs. Frequency, VCC_VCO = 3.3 V
from the VCO output, or the KV value is divided by D. D is
VCO ALC THRESHOLD
the output divider value if the N divider is driven from the
RF output divider. Different VCO ALC threshold values are used for different device
revisions for the best performance. The device revision is
The VCO shows variation of KV as the tuning voltage, VTUNE, checked by reading the DEVICE_REVISION bits in Address 0x06.
varies within the band and from band to band. For wideband The default register values for the latest device revision
applications covering a wide frequency range (and changing (DEVICE_REVISION = 0x0A) are given in the register tables.
output dividers), a value of 50 MHz/V provides the most accurate When using the older device revision (DEVICE_REVISION =
KV, because this value is closest to the average value. Figure 33 0x09), the following settings are recommended:
and Figure 34 shows how KV varies with fundamental VCO
frequency along with an average value for the frequency band. • For 3.3 V VCO operation, Address 0x2D, Bits[2:0] = 0x1
Users may prefer Figure 33 and Figure 34 when using narrow- • For 5 V VCO operation, Address 0x2E, Bits[2:0] = 0x2 and
band designs. Address 0x2F, Bits[2:0] = 0x4
150
All other register settings are the same. and there is no difference in
140
130
performance specifications between the two revisions.
120
OUTPUT STAGE
VCO SENSITIVITY, KV (MHz/V)

110
100 The RF8P pin and the RF8N pin of the ADF4372 connect to
90
the collectors of a bipolar negative positive negative (NPN)
80
70
differential pair driven by buffered outputs of the VCO, as
60 shown in Figure 35. The ADF4372 contains internal 50 Ω
50 resistors connected to the VCC_X1 pin. To optimize the power
40
dissipation vs. the output power requirements, the tail current
30
20 of the differential pair is programmable using Bits[1:0] in
10 Address 0x25. Four current levels can be set. These levels give
0 approximate output power levels of −4 dBm, −1 dBm, 2 dBm,
16984-033

4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

FREQUENCY (GHz) and 5 dBm. Levels of −4 dBm and −1 dBm can be achieved by
Figure 33. VCO Sensitivity, KV vs. Frequency, VCC_VCO = 5 V ac coupling into a 50 Ω load. Levels of 2 dBm and 5 dBm
require an external shunt inductor connected to the VCC_X1
pin. Do not use these two higher levels without an inductor
because not using an inductor can cause the compression of the
output stage. An inductor has a narrower operating frequency
than a 50 Ω resistor. For accurate power levels, refer to the
Typical Performance Characteristics section. Add an external
shunt inductor to provide higher power levels, which is less
wideband than the internal bias only. Terminate the unused
complementary output with a circuit similar to the used output.

Rev. A | Page 20 of 48
Data Sheet ADF4372
VCC_X1 VCC_X1
PHASE ADJUST AND SPUR OPTIMIZATION BY
50Ω 50Ω
USING PHASE_WORD
RF8P RF8N
The phase of the VCO output frequency can be adjusted in
BUFFER, 24-bit steps which is set by Register 0x001B, Register 0x001C,
DIVIDE BY
VCO
1, 2, 4, 8, and Register 0x001D (PHASE_WORD). To adjust the phase,
16, 32, 64
take the following steps:

16984-035
1. Lock the desired frequency, as usual.

Figure 35. Output Stage 2. Disable the autocalibration from REG0012, Bit 6
(EN_AUTOCAL).
The RFAUX8P and the RFAUX8N provide the same functionality
as the RF8P and RF8N output, but they can also output the 3. Enable the phase adjust from REG001A, Bit 6 (PHASE_ADJ).
divided RF8x frequency or the VCO frequency if desired. 4. Set PHASE_WORD to the desired value.
These outputs can be powered down when not in use, and the 5. Write to Register 0x10 (each write shifts the output by the
pins can be left open if unused. amount defined in the previous step).
The doubled VCO output (8 GHz to 16 GHz) is available on the When fine tuning on the phase shift is required, set the phase
RF16P pin and the RF16N pin, which can be directly connected word to another value, and write to REG0010 again.
to the next circuit. PHASE_WORD can optimize spur levels. While locking to a
DOUBLER new frequency, the PHASE_WORD value (phase adjust is
The VCO frequency multiplied by 2 is available at the RF16P disabled at this stage) affects the spur levels. A prime number
pin and RF16N pin. This output can be powered down when close to 45°, 90°, or 180° is recommended. (An 8388617 value
not in use, and the RF16P pin and the RF16N pin can be left open shows good performance for most cases). Because this value is
if unused. only important while locking to a new frequency, the phase
adjust can be enabled, and the output phase can be adjusted as
RF16P previously explained after lock is achieved.
×2
SPI
16984-036

RF16N
The SPI of the ADF4372 allows the user to configure the device
Figure 36. Doubler Output Stage as required via a 3-wire or 4-wire SPI port. This interface provides
An automatic tracking filter on the ADF4372 that suppresses users with added flexibility and customization. The serial port
the VCO and other unwanted frequency products ensures the interface consists of four control lines: SCLK, SDIO, CS, and
doubled output is maximized and that the VCO and 3 × VCO MUXOUT (not used in 3-wire SPI). The timing requirements
frequencies are suppressed regardless of the output frequency. for the SPI port are detailed in Table 2.
Suppression of <50 dB is typical. The optimum values are set The SPI protocol consists of a read and write bit and 15 register
automatically by the automatic tracking when it is enabled address bits, followed by eight data bits. Both the address and data
using Bit 1 in Address 0x23. fields are organized with the MSB first and end with the LSB
The settings for optimum output power, phase noise, and by default. The timing diagrams for write mode and read mode
harmonic rejection are given in Table 7. are shown in Figure 3 and Figure 4, respectively. The significant
bit order can be changed via the Bit 1 (LSB_FIRST) setting at
Table 7. Filter and Bias Settings for Doubled Output Address 0x00. The related timing diagram is shown in Figure 2.
Frequency (GHz) Filter Bias The ADF4372 input logic level for the write cycle is compatible
<8.4 7 3 with 1.8 V logic level (see the logic parameters in Table 1). On a
8.4 to 9.4 6 3 read cycle, both the SDIO pin and MUXOUT pin are configurable
9.4 to 10 5 3 for 1.8 V (default) or 3.3 V output levels by the LEV_SEL bit
10 to 11.5 4 3 setting.
11.5 to 12.2 3 3
12.2 to 13.7 2 3
13.7 to 14.5 1 3
>14.5 0 3

Rev. A | Page 21 of 48
ADF4372 Data Sheet
SPI Stream Mode The diagram of 3-byte streaming is shown in Figure 5. The
The ADF4372 supports stream mode, where data bits are loaded instruction header starts with a Logic 0 to indicate a write
to or read from registers serially without writing the register sequence and addresses the register. The data for registers (N, N −
address (instruction word). This mode is useful in time critical 1, and N − 2) are loaded consecutively without any assertion in CS.
applications, when a large amount of data must be transferred or The registers are organized into eight bits, and if a register
when some registers must be updated repeatedly. requires more than eight bits, sequential register addresses
The slave device starts reading or writing data to this address and are used. This organization enables using stream mode and
continues as long as CS is asserted and single-byte writes are not simplifies loading. For example, FRAC1WORD is stored in
enabled (Bit 7 in Address 0x01). The slave device automatically Address 0x16, Address 0x15, and Address 0x14 (MSB to LSB).
increments or decrements the address depending on the setting These registers can be loaded by using Address 0x16 and sending
of the address ascension bit (Bit 2 in Address 0x00). the whole 24-bit data afterward, as shown in Figure 5.

Rev. A | Page 22 of 48
Data Sheet ADF4372

DEVICE SETUP
The recommended sequence of steps to set up the ADF4372 are When using a higher fPFD in normal operation, use half of the
as follows: fPFD routine in the autocalibration process. The routine can be
1. Set up the SPI interface. described shortly as follows: if fPFD > 125 MHz, use
2. Perform the initialization sequence. autocalibration with half of the fPFD by doubling the R value and
3. Perform the frequency update sequence. doubling the N value. Once the lock achieved, disable the
autocalibration and set the desired R and N values.
STEP 1: SET UP THE SPI INTERFACE Therefore, the update sequence must be as follows for fPFD >
First, initialize the SPI. Write the values in Table 8 to Address 0x00 125 MHz:
and Address 0x01.
1. REG001F (with doubled R_WORD[4:0] for halved fPFD)
Table 8. SPI Interface Setup 2. REG001A (MOD2WORD[13:8] for halved fPFD)
Address Setting Notes 3. REG0019 (MOD2WORD[7:0] for halved fPFD)
0x00 0x18 4-wire SPI 4. REG0018 (FRAC2WORD[13:7] for halved fPFD)
0x01 0x00 Stalling, master readback control 5. REG0017 (FRAC2WORD[6:0] for halved fPFD)
6. REG0016 (FRAC1WORD[23:16] for halved fPFD)
7. REG0015 (FRAC1WORD[15:8] for halved fPFD)
STEP 2: INITIALIZATION SEQUENCE 8. REG0014 (FRAC1WORD[7:0] for halved fPFD)
Write to each register in reverse order from Address 0x7C to 9. REG0012 (enable autocalibration: EN_AUTOCAL = 1)
Address 0x10. Choosing appropriate values to generate the desired 10. REG0011 (BIT_INTEGER_WORD[15:8] for halved fPFD)
frequency. The registers that are not given in the datasheet can 11. REG0010 (BIT_INTEGER_WORD[7:0] for halved fPFD)
be skipped in normal SPI mode. If SPI stream mode is used, write 12. Ensure part is locked by checking lock detect.
0x00 to the registers not listed in the Register Summary section. 13. REG001F (R_WORD[4:0] for desired fPFD)
14. REG001A (MOD2WORD[13:8] for desired fPFD)
The frequency update sequence follows to generate the desired 15. REG0019 (MOD2WORD[7:0] for desired fPFD)
output frequency. 16. REG0018 (FRAC2WORD[13:7] for desired fPFD)
STEP 3: FREQUENCY UPDATE SEQUENCE 17. REG0017 (FRAC2WORD[6:0] for desired fPFD)
18. REG0016 (FRAC1WORD[23:16] for desired fPFD)
Frequency updates require updating R, MOD2, FRAC1,
19. REG0015 (FRAC1WORD[15:8] for desired fPFD)
FRAC2, and INT. The autocalibration process works reliably
20. REG0014 (FRAC1WORD[7:0] for desired fPFD)
when fPFD ≤ 125 MHz.
21. REG0012 (disable autocalibration: EN_AUTOCAL = 0)
Therefore, the update sequence must be as follows for fPFD ≤ 22. REG0011 (BIT_INTEGER_WORD[15:8] for desired fPFD)
125 MHz: 23. REG0010 (BIT_INTEGER_WORD[7:0] for desired fPFD)
Frequency updates require updating MOD2, FRAC1, FRAC2,
The frequency change occurs on the second write to REG0010.
and INT. Therefore, the update sequence must be as follows:
Because halved fPFD is used with autocalibration, use half of the
1. REG001F (new R_WORD[4:0])
fPFD value in the calculation of the timeout values explained in
2. REG001A (new MOD2WORD[13:8])
Lock Time section.
3. REG0019 (new MOD2WORD[7:0])
4. REG0018 (new FRAC2WORD[13:7]) The unchanged registers do not need to be updated. For
5. REG0017 (new FRAC2WORD[6:0]) example, for an integer-N PLL configuration (fractional parts are
6. REG0016 (new FRAC1WORD[23:16]) not used), skip Step 1 to Step 8. In this case, the only required
7. REG0015 (new FRAC1WORD[15:8]) updates are Address 0x11 and Address 0x10.
8. REG0014 (new FRAC1WORD[7:0])
9. REG0011 (new BIT_INTEGER_WORD[15:8])
10. REG0010 (new BIT_INTEGER_WORD[7:0])
The frequency change occurs on the write to REG0010.

Rev. A | Page 23 of 48
ADF4372 Data Sheet

APPLICATIONS INFORMATION
POWER SUPPLIES OUTPUT MATCHING
The ADF4372 contains four multiband VCOs that together cover The low frequency output can be ac-coupled to the next circuit,
an octave range of frequencies. To achieve optimal VCO phase if desired. However, if higher output power is required, use a
noise performance, it is recommended to connect a low noise pull-up inductor to increase the output power level.
regulator, such as the ADM7150 or LT3045, to the VCC_VCO VDD_X1

pin. Connect the same regulator to the VCC_VCO pin and the 7.5nH
VCC_LDO pin. It is recommended to connect 1 μF decoupling 10pF
capacitors to the 5 V VCO supply. RF8P

16984-041
50Ω
For all other 3.3 V supply pins, use one ADM7150 or one
LT3045 regulator. A 1 μF capacitor is also recommended for the Figure 37. Optimum Output Stage
VDD_VP pin. Additional decoupling to other supply pins is not
required. When differential outputs are not needed, terminate the unused
output or combine it with both outputs using a balun.
PCB DESIGN GUIDELINES FOR AN LGA PACKAGE
For lower frequencies that are less than 1 GHz, it is recommended
The bottom of the chip scale package has a central exposed to use a 100 nH inductor on the RF8P pin and the RF8N pin.
thermal pad. The thermal pad on the PCB must be at least as
large as the exposed pad. On the PCB, there must be a minimum The RF8P and RF8N pins form a differential circuit. Provide
each output with the same (or similar) components where
clearance of 0.25 mm between the thermal pad and the inner
edges of the pad pattern. This clearance ensures there is no possible, including the same shunt inductor value, bypass
shorting capacitor, and termination.

To improve the thermal performance of the package, use thermal The RFAUX8P pin and the RFAUX8N pin are effectively the
vias on the PCB thermal pad. If vias are used, incorporate them same as the RF8P pin and the RF8N pin and must be treated in
into the thermal pad at the 1.2 mm pitch grid. The via diameter the manner as outlined for the RF8P pin and the RF8N pin.
must be between 0.3 mm and 0.33 mm, and the via barrel must The RF16P pin and the RF16N pin can be directly connected to
be plated with 1 oz. of copper to plug the via into the barrel. the next circuit stage. These pins are internally matched to 50 Ω
and do not require additional decoupling.
For a microwave PLL and VCO synthesizer, such as the
ADF4372, take care with the board stackup and layout. Do not
consider using FR4 material because it causes an amplitude
decrease in signals greater than 3 GHz. Instead, Rogers 4350,
Rogers 4003, or Rogers 3003 dielectric material is suitable.
Take care with the RF output traces to minimize discontinuities
and ensure the best signal integrity. Via placement and grounding
are critical.

Rev. A | Page 24 of 48
Data Sheet ADF4372

REGISTER SUMMARY
Table 9. ADF4372 Register Summary
Reg Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
Addr.
0x00 [7:0] SOFT_RESET_R LSB_FIRST_R ADDRESS_ SDO_ SDO_ACTIVE ADDRESS_ LSB_FIRST SOFT_RESET 0x18 R/W
ASCENSION_ ACTIVE_R ASCENSION
R
0x01 [7:0] SINGLE_ STALLING MASTER_ RESERVED 0x00 R/W
INSTRUCTION READBACK_
CONTROL
0x03 [7:0] RESERVED CHIP_TYPE 0x0X R
0x04 [7:0] PRODUCT_ID[7:0] 0xXX R/W
0x05 [7:0] PRODUCT_ID[15:8] 0xXX R/W
0x06 [7:0] PRODUCT_GRADE DEVICE_REVISION 0xXX R
0x10 [7:0] BIT_INTEGER_WORD[7:0] 0x32 R/W
0x11 [7:0] BIT_INTEGER_WORD[15:8] 0x00 R/W
0x12 [7:0] RESERVED EN_AUTOCAL PRE_SEL RESERVED 0x40 R/W
0x14 [7:0] FRAC1WORD[7:0] 0x00 R/W
0x15 [7:0] FRAC1WORD[15:8] 0x00 R/W
0x16 [7:0] FRAC1WORD[23:16] 0x00 R/W
0x17 [7:0] FRAC2WORD[6:0] FRAC1WORD 0x00 R/W
[24]
0x18 [7:0] RESERVED FRAC2WORD[13:7] 0x00 R/W
0x19 [7:0] MOD2WORD[7:0] 0xE8 R/W
0x1A [7:0] RESERVED PHASE_ADJ MOD2WORD[13:8] 0x03 R/W
0x1B [7:0] PHASE_WORD[7:0] 0x00 R/W
0x1C [7:0] PHASE_WORD[15:8] 0x00 R/W
0x1D [7:0] PHASE_WORD[23:16] 0x00 R/W
0x1E [7:0] CP_CURRENT PD_POL PD RESERVED CNTR_RESET 0x48 R/W
0x1F [7:0] RESERVED R_WORD 0x01 R/W
0x20 [7:0] MUXOUT MUXOUT_EN LEV_SEL RESERVED 0x14 R/W
0x22 [7:0] RESERVED REFIN_MODE REF_DOUB RDIV2 RESERVED 0x00 R/W
0x23 [7:0] RESERVED CLK_DIV_MODE RESERVED TRACKING_FIL RESERVED 0x00 R/W
TER_MUX_SEL
0x24 [7:0] FB_SEL DIV_SEL RESERVED 0x80 R/W
0x25 [7:0] MUTE_LD RESERVED RF_DIVSEL_ X4_EN X2_EN RF_EN RF_OUT_POWER 0x07 R/W
DB
0x26 [7:0] BLEED_ICP 0x32 R/W
0x27 [7:0] LD_BIAS LDP BLEED_GATE BLEED_EN VCOLDO_P RF_PBS 0xC5 R/W
D
0x28 [7:0] DOUBLE_BUFF RESERVED LD_COUNT LOL_EN 0x03 R/W
0x2A [7:0] RESERVED BLEED_POL RESERVED LE_SEL RESERVED READ_SEL 0x00 R/W
0x2B [7:0] RESERVED LSB_P1 VAR_MOD_EN RESERVED SD_LOAD_ RESERVED SD_EN_FRAC0 0x01 R/W
ENB
0x2C [7:0] RESERVED ALC_RECT_ ALC_REF_ ALC_REF_DAC_NOM_VCO1 VTUNE_ DISABLE_ALC 0x44 R/W
SELECT_ DAC_LO_ CALSET_EN
VCO1 VCO1
0x2D [7:0] RESERVED ALC_RECT_ ALC_REF_DAC_ ALC_REF_DAC_NOM_VCO2 0x11 R/W
SELECT_VCO2 LO_VCO2
0x2E [7:0] RESERVED ALC_RECT_ ALC_REF_DAC_ ALC_REF_DAC_NOM_VCO3 0x10 R/W
SELECT_VCO3 LO_VCO3
0x2F [7:0] SWITCH_LDO_ RESERVED ALC_RECT_ ALC_REF_DAC_ ALC_REF_DAC_NOM_VCO4 0x92 R/W
3P3V_5V SELECT_VCO4 LO_VCO4
0x30 [7:0] VCO_BAND_DIV 0x3F R/W
0x31 [7:0] TIMEOUT[7:0] 0xA7 R/W
0x32 [7:0] ADC_MUX_ RESERVED ADC_FAST_ ADC_CTS_ ADC_ ADC_ TIMEOUT[9:8] 0x04 R/W
SEL CONV CONV CONVERSION ENABLE
0x33 [7:0] RESERVED SYNTH_LOCK_TIMEOUT 0x0C R/W
0x34 [7:0] VCO_FSM_TEST_MODES VCO_ALC_TIMEOUT 0x9E R/W
0x35 [7:0] ADC_CLK_DIVIDER 0x4C R/W
0x36 [7:0] ICP_ADJUST_OFFSET 0x30 R/W
0x37 [7:0] SI_BAND_SEL 0x00 R/W
0x38 [7:0] SI_VCO_SEL SI_VCO_BIAS_CODE 0x00 R/W
0x39 [7:0] RESERVED VCO_FSM_TEST_MUX_SEL SI_VTUNE_CAL_SET 0x07 R/W
0x3A [7:0] ADC_OFFSET 0x55 R/W
0x3D [7:0] RESERVED SD_RESET RESERVED 0x00 R/W
0x3E [7:0] RESERVED CP_TMODE RESERVED 0x0C R/W
Rev. A | Page 25 of 48
ADF4372 Data Sheet
Reg Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
Addr.
0x3F [7:0] CLK1_DIV[7:0] 0x80 R/W
0x40 [7:0] RESERVED TRM_IB_VCO_BUF CLK1_DIV[11:8] 0x50 R/W
0x41 [7:0] CLK2_DIVIDER_1[7:0] 0x28 R/W
0x47 [7:0] TRM_RESD_VCO_MUX RESERVED 0xC0 R/W
0x52 [7:0] TRM_RESD_VCO_BUF TRM_RESCI_VCO_BUF RESERVED 0xF4 R/W
0x6E [7:0] VCO_DATA_READBACK[7:0] 0x00 R
0x6F [7:0] VCO_DATA_READBACK[15:8] 0x00 R
0x70 [7:0] BAND_SEL_X2 RESERVED BIAS_SEL_X2 0x03 R/W
0x71 [7:0] BAND_SEL_X4 RESERVED BIAS_SEL_X4 0x60 R/W
0x72 [7:0] RESERVED AUX_FREQ_ POUT_AUX PDB_AUX RESERVED COUPLED_ RESERVED 0x32 R/W
SEL VCO
0x73 [7:0] RESERVED ADC_CLK_ PD_NDIV LD_DIV 0x00 R/W
DISABLE
0x7C [7:0] RESERVED LOCK_DETECT 0x00 R
_READBACK

Rev. A | Page 26 of 48
Data Sheet ADF4372

REGISTER DETAILS
Address: 0x00, Default: 0x18, Name: REG0000
7 6 5 4 3 2 1 0
0 0 0 1 1 0 0 0

[7] SOFT_RESET_R (R/W) [0] SOFT_RESET (R/W)

Copy of Bit-0. Soft Reset.
[6] LSB_FIRST_R (R/W) [1] LSB_FIRST (R/W)
Copy of Bit-1. Reads LSB first when Active.
[5] ADDRESS_ASCENSION_R (R/W) [2] ADDRESS_ASCENSION (R/W)
Copy of Bit-2. Set Address in Ascending Order (Default
is Ascending).
[4] SDO_ACTIVE_R (R/W)
Copy of Bit-3. [3] SDO_ACTIVE (R/W)
Choose Between 3-Pin or 4-Pin Operation.

Table 10. Bit Descriptions for REG0000

Bit(s) Bit Name Description Default Access
7 SOFT_RESET_R Copy of Bit 0. 0x0 Read/Write
(R/W)
6 LSB_FIRST_R Copy of Bit 1. 0x0 R/W
5 ADDRESS_ASCENSION_R Copy of Bit 2. 0x0 R/W
4 SDO_ACTIVE_R Copy of Bit 3. 0x1 R/W
3 SDO_ACTIVE Choose Between 3-Pin or 4-Pin Operation. 0x1 R/W
0: 3-pin.
1: 4-pin. Enables SDIO pin and the SDIO pin becomes an input only.
2 ADDRESS_ASCENSION Set Address in Ascending Order (Default Is Ascending). 0x0 R/W
0: descending.
1: ascending.
1 LSB_FIRST Reads LSB First when Active. 0x0 R/W
0 SOFT_RESET Soft Reset. 0x0 R/W
0: normal operation.
1: soft reset.

Address: 0x01, Default: 0x00, Name: REG0001

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] SINGLE_INSTRUCTION (R/W) [4:0] RESERVED

Single Instruction.
[5] MASTER_READBACK_CONTROL (R/W)
[6] STALLING (R/W) Master Readback Control.
Stalling.

Table 11. Bit Descriptions for REG0001

Bit(s) Bit Name Description Default Access
7 SINGLE_INSTRUCTION Single Instruction. SPI stream mode is disabled if this bit is set to 1. 0x0 R/W
6 STALLING Stalling. For internal use. 0x0 R/W
5 MASTER_READBACK_CONTROL Master Readback Control. For internal use. 0x0 R/W
[4:0] RESERVED Reserved. 0x0 Read
Only (R)

Rev. A | Page 27 of 48
ADF4372 Data Sheet
Address: 0x03, Default: 0x0X, Name: REG0003
7 6 5 4 3 2 1 0
0 0 0 0 X X X X

[7:4] RESERVED [3:0] CHIP_TYPE (RP)

Chip Type.

Table 12. Bit Descriptions for REG0003

Bit(s) Bit Name Description Default Access
[7:4] RESERVED Reserved. 0x0 R
[3:0] CHIP_TYPE Chip Type. 0x0 Read Programmable
(RP)
Address: 0x04, Default: 0xXX, Name: REG0004
7 6 5 4 3 2 1 0
X X X X X X X X

[7:0] PRODUCT_ID[7:0] (R/WP)

Product ID.

Table 13. Bit Descriptions for REG0004

Bit(s) Bit Name Description Default Access
[7:0] PRODUCT_ID[7:0] Product ID. 0x0 Read/Write Programmable
(R/WP)

Address: 0x05, Default: 0xXX, Name: REG0005

7 6 5 4 3 2 1 0
X X X X X X X X

[7:0] PRODUCT_ID[15:8] (R/WP)

Product ID.

Table 14. Bit Descriptions for REG0005

Bit(s) Bit Name Description Default Access
[7:0] PRODUCT_ID[15:8] Product ID. 0x0 R/WP

Address: 0x06, Default: 0xXX, Name: REG0006

7 6 5 4 3 2 1 0
X X X X X X X X

[7:4] PRODUCT_GRADE (RP) [3:0] DEVICE_REVISION (RP)

Product Grade. Device Revision.

Table 15. Bit Descriptions for REG0006

Bit(s) Bit Name Description Default Access
[7:4] PRODUCT_GRADE Product Grade. 0x0 RP
[3:0] DEVICE_REVISION Device Revision. 0x0 RP

Address: 0x10, Default: 0x32, Name: REG0010

7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 0

[7:0] BIT_INTEGER_WORD[7:0] (R/W)

16-Bit Integer Word.

Table 16. Bit Descriptions for REG0010

Bit(s) Bit Name Description Default Access
[7:0] BIT_INTEGER_WORD[7:0] 16-Bit Integer Word. Sets the integer value of N. Updates to the PLL N counter, 0x32 R/W
including FRAC1, FRAC2, and MOD2, are double buffered by this bitfield.

Rev. A | Page 28 of 48
Data Sheet ADF4372
Address: 0x11, Default: 0x00, Name: REG0011
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] BIT_INTEGER_WORD[15:8] (R/W)

16-Bit Integer Word.

Table 17. Bit Descriptions for REG0011

Bit(s) Bit Name Description Default Access
[7:0] BIT_INTEGER_WORD[15:8] 16-Bit Integer Word. Sets the integer value of N. 0x0 R/W

Address: 0x12, Default: 0x40, Name: REG0012

7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0

[7] RESERVED [4:0] RESERVED

[6] EN_AUTOCAL (R/W) [5] PRE_SEL (R/W)
Enables Autocalibration. Prescaler Select.

Table 18. Bit Descriptions for REG0012

Bit(s) Bit Name Description Default Access
7 RESERVED Reserved. 0x0 R
6 EN_AUTOCAL Enables Autocalibration. 0x1 R/W
0: VCO autocalibration disabled.
1: VCO autocalibration enabled.
5 PRE_SEL Prescaler Select. The dual modulus prescaler is set by this bit. The prescaler, at the input to 0x0 R/W
the N divider, divides down the VCO signal. This action occurs so the N divider can handle the
signal. The prescaler setting affects the RF frequency and the minimum and maximum INT
value.
0: 4/5 prescaler.
1: 8/9 prescaler.
[4:0] RESERVED Reserved. 0x0 R

Address: 0x14, Default: 0x00, Name: REG0014

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] FRAC1WORD[7:0] (R/W)

25-Bit FRAC1 Value.

Table 19. Bit Descriptions for REG0014

Bit(s) Bit Name Description Default Access
[7:0] FRAC1WORD[7:0] 25-Bit FRAC1 Value. Sets the FRAC1 value. 0x0 R/W

Address: 0x15, Default: 0x00, Name: REG0015

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] FRAC1WORD[15:8] (R/W)

25-Bit FRAC1 Value.

Table 20. Bit Descriptions for REG0015

Bit(s) Bit Name Description Default Access
[7:0] FRAC1WORD[15:8] 25-Bit FRAC1 Value. Sets the FRAC1 value. 0x0 R/W

Rev. A | Page 29 of 48
ADF4372 Data Sheet
Address: 0x16, Default: 0x00, Name: REG0016
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] FRAC1WORD[23:16] (R/W)

25-Bit FRAC1 Value.

Table 21. Bit Descriptions for REG0016

Bit(s) Bit Name Description Default Access
[7:0] FRAC1WORD[23:16] 25-Bit FRAC1 Value. Sets the FRAC1 value. 0x0 R/W

Address: 0x17, Default: 0x00, Name: REG0017

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:1] FRAC2WORD[6:0] (R/W) [0] FRAC1WORD[24] (R/W)

14-Bit FRAC2 Value. 25-Bit FRAC1 Value.

Table 22. Bit Descriptions for REG0017

Bit(s) Bit Name Description Default Access
[7:1] FRAC2WORD[6:0] 14-Bit FRAC2 Value. Sets the FRAC2 value. 0x0 R/W
0 FRAC1WORD[24:24] 25-Bit FRAC1 Value. Sets the FRAC1 value. 0x0 R/W

Address: 0x18, Default: 0x00, Name: REG0018

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] RESERVED [6:0] FRAC2WORD[13:7] (R/W)

14-Bit FRAC2 Value.

Table 23. Bit Descriptions for REG0018

Bit(s) Bit Name Description Default Access
7 RESERVED Reserved. 0x0 R
[6:0] FRAC2WORD[13:7] 14-Bit FRAC2 Value. Sets the FRAC2 value. 0x0 R/W

Address: 0x19, Default: 0xE8, Name: REG0019

7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0

[7:0] MOD2WORD[7:0] (R/W)

14-Bit MOD2 Value.

Table 24. Bit Descriptions for REG0019

Bit(s) Bit Name Description Default Access
[7:0] MOD2WORD[7:0] 14-Bit MOD2 Value. Sets the MOD2 value. 0xE8 R/W

Rev. A | Page 30 of 48
Data Sheet ADF4372
Address: 0x1A, Default: 0x03, Name: REG001A
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 1

[7] RESERVED [5:0] MOD2WORD[13:8] (R/W)

14-Bit MOD2 Value.
[6] PHASE_ADJ (R/W)
Phase Adjust Enable.

Table 25. Bit Descriptions for REG001A

Bit(s) Bit Name Description Default Access
7 RESERVED Reserved. 0x0 R
6 PHASE_ADJ Phase Adjust Enable. Set to 1 to enable phase adjust. Phase adjust increases the phase 0x0 R/W
of the output relative to the current phase.
0: phase adjust disabled.
1: phase adjust enabled.
[5:0] MOD2WORD[13:8] 14-Bit MOD2 Value. Sets the MOD2 value. 0x3 R/W

Address: 0x1B, Default: 0x00, Name: REG001B

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] PHASE_WORD[7:0] (R/W)

24-Bit Phase Value.

Table 26. Bit Descriptions for REG001B

Bit(s) Bit Name Description Default Access
[7:0] PHASE_WORD[7:0] 24-Bit Phase Value. Sets the phase word for phase adjust. The phase of the RF output 0x0 R/W
frequency can be adjusted in 24-bit steps. Phase Step = Phase Word ÷ 16,777,216 × 360.

Address: 0x1C, Default: 0x00, Name: REG001C

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] PHASE_WORD[15:8] (R/W)

24-Bit Phase Value.

Table 27. Bit Descriptions for REG001C

Bit(s) Bit Name Description Default Access
[7:0] PHASE_WORD[15:8] 24-Bit Phase Value. Sets the phase word for phase adjust. The phase of the RF output 0x0 R/W
frequency can be adjusted in 24-bit steps. Phase Step = Phase Word ÷ 16,777,216 × 360°.

Address: 0x1D, Default: 0x00, Name: REG001D

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] PHASE_WORD[23:16] (R/W)

24-Bit Phase Value.

Table 28. Bit Descriptions for REG001D

Bit(s) Bit Name Description Default Access
[7:0] PHASE_WORD[23:16] 24-Bit Phase Value. Sets the phase word for phase adjust. The phase of the RF output 0x0 R/W
frequency can be adjusted in 24-bit steps. Phase Step = Phase Word ÷ 16,777,216 × 360°.

Rev. A | Page 31 of 48
ADF4372 Data Sheet
Address: 0x1E, Default: 0x48, Name: REG001E
7 6 5 4 3 2 1 0
0 1 0 0 1 0 0 0

[7:4] CP_CURRENT (R/W) [0] CNTR_RESET (R/W)

Charge Pum p Current Setting. Counter Reset.
[3] PD_POL (R/W) [1] RESERVED
Phase Detector Polarity.
[2] PD (R/W)
Power-Down.

Table 29. Bit Descriptions for REG001E

Bit(s) Bit Name Description Default Access
[7:4] CP_CURRENT Charge Pump Current Setting. Sets the charge pump current. Set these bits to the charge 0x4 R/W
pump current that the loop filter is designed for.
0: 0.35 mA.
1: 0.70 mA.
10: 1.05 mA.
11: 1.4 mA.
100: 1.75 mA.
101: 2.1 mA.
110: 2.45 mA.
111: 2.8 mA.
1000: 3.15 mA.
1001: 3.5 mA.
1010: 3.85 mA.
1011: 4.2 mA.
1100: 4.55 mA.
1101: 4.9 mA.
1110: 5.25 mA.
1111: 5.6 mA.
3 PD_POL Phase Detector Polarity. If using a noninverting loop filter and a VCO with positive tuning 0x1 R/W
slope, set phase detector polarity to positive. If using an inverting loop filter and a VCO with a
negative tuning slope, set phase detector polarity to positive. If using a noninverting loop
filter and a VCO with a negative tuning slope, set phase detector polarity to negative. If using
an inverting loop filter and a VCO with a positive tuning slope, set phase detector polarity to
negative.
0: negative phase detector polarity.
1: positive phase detector polarity.
2 PD Power-Down. Setting to 1 powers down all internal PLL blocks of the ADF4372. The VCO and 0x0 R/W
multipliers remain powered up. The registers do not lose their values. After bringing the
ADF4372 out of power-down (setting to 0) a write to Address 0x10 is required to relock the
loop.
0: normal operation.
1: power-down.
1 RESERVED Reserved. 0x0 R
0 CNTR_RESET Counter Reset. Setting to 1 holds the N divider and R counter in reset. There are no signals 0x0 R/W
entering the PFD.
0: normal operation.
1: counter reset.

Rev. A | Page 32 of 48
Data Sheet ADF4372
Address: 0x1F, Default: 0x01, Name: REG001F
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1

[7:5] RESERVED [4:0] R_WORD (R/W)

5-Bit R Counter.

Table 30. Bit Descriptions for REG001F

Bit(s) Bit Name Description Default Access
[7:5] RESERVED Reserved. 0x0 R
[4:0] R_WORD 5-Bit R Counter. b'00000 corresponds to divide by 32. 0x1 R/W
0: 32.
1: 1.
10: 2.
11: 3.
…
11111:31

Address: 0x20, Default: 0x14, Name: REG0020

7 6 5 4 3 2 1 0
0 0 0 1 0 1 0 0

[7:4] MUXOUT (R/W) [1:0] RESERVED

Mux Out.
[2] LEV_SEL (R/W)
[3] MUXOUT_EN (R/W) Mux Out Level Select.
Mux Out Enable.

Table 31. Bit Descriptions for REG0020

Bit(s) Bit Name Description Default Access
[7:4] MUXOUT Mux Out. This bit is used to set the mux out signal when MUXOUT_EN = 1. 0x1 R/W
0: tristate, high impedance output (only works when MUXOUT_EN = 0).
1: digital lock detect.
10: charge pump up.
11: charge pump down.
100: R divider/2.
101: N divider/2.
110: VCO test modes.
111: reserved.
1000: high.
1001: VCO calibration R band/2.
1010: VCO calibration N band/2.
3 MUXOUT_EN Mux Out Enable. Set to 0 if using 4-wire SPI. 0x0 R/W
0: MUXOUT pin is configured as the serial data output for the 4-wire SPI. Mux out
functionality is disabled.
1: MUXOUT pin is configured for mux out functionality.
2 LEV_SEL Mux Out Level Select. Select the voltage level of the logic at the mux out. 0x1 R/W
0: 1.8 V logic.
1: 3.3 V logic.
[1:0] RESERVED Reserved. 0x0 R

Rev. A | Page 33 of 48
ADF4372 Data Sheet
Address: 0x22, Default: 0x00, Name: REG0022
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] RESERVED [3:0] RESERVED

[6] REFIN_MODE (R/W) [4] RDIV2 (R/W)
Choose Between Single-Ended or RDIV2.
Differential REFin.
[5] REF_DOUB (R/W)
Reference Doubler.

Table 32. Bit Descriptions for REG0022

Bit(s) Bit Name Description Default Access
7 RESERVED Reserved. 0x0 R
6 REFIN_MODE Choose Between Single-Ended or Differential REFIN. 0x0 R/W
0: single-ended REFIN.
1: differential REFIN.
5 REF_DOUB Reference Doubler. Controls the reference doubler block. 0x0 R/W
0: doubler disabled.
1: doubler enabled.
4 RDIV2 RDIV2. Controls the reference divide by 2 clock. This feature can be used to provide a 50% 0x0 R/W
duty cycle signal to the PFD.
0: RDIV2 disabled.
1: RDIV2 enabled.
[3:0] RESERVED Reserved. 0x0 R

Address: 0x23, Default: 0x00, Name: REG0023

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [0] RESERVED

[5:4] CLK_DIV_MODE (R/W) [1] TRACKING_FILTER_MUX_SEL (R/W)
Reserved. Tracking Filter Mux Select.
[3:2] RESERVED

Table 33. Bit Descriptions for REG0023

Bit(s) Bit Name Description Default Access
[7:6] RESERVED Reserved. 0x0 R
[5:4] CLK_DIV_MODE Reserved. 0x0 R/W
[3:2] RESERVED Reserved. 0x0 R
1 TRACKING_FILTER_MUX_SEL Tracking Filter Mux Select. 0x0 R/W
0: normal, tracking filter coefficients set automatically.
1: tracking filter coefficients set manually from SPI (Address 0x70 and
Address 0x71).
0 RESERVED Reserved. 0x0 R

Rev. A | Page 34 of 48
Data Sheet ADF4372
Address: 0x24, Default: 0x80, Name: REG0024
7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7] FB_SEL (R/W) [3:0] RESERVED

Feedback.
[6:4] DIV_SEL (R/W)
Division Selection.

Table 34. Bit Descriptions for REG0024

Bit(s) Bit Name Description Default Access
7 FB_SEL Feedback. 0x1 R/W
0: divider feedback to N counter.
1: fundamental feedback to N counter.
[6:4] DIV_SEL Division Selection. 0x0 R/W
0: divide 1.
1: divide 2.
10: divide 4.
11: divide 8.
100: divide 16.
101: divide 32.
110: divide 64.
111: reserved.
[3:0] RESERVED Reserved. 0x0 R

Address: 0x25, Default: 0x07, Name: REG0025

7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 1

[7] MUTE_LD (R/W) [1:0] RF_OUT_POWER (R/W)

Reserved. Select Output Power Level.
[6] RESERVED [2] RF_EN (R/W)
RFOUT Enable.
[5] RF_DIVSEL_DB (R/W)
Select if DIV_SEL is Double Buffered. [3] X2_EN (R/W)
Doubler Path Enable.
[4] X4_EN (R/W)
Not Used.

Table 35. Bit Descriptions for REG0025

Bit(s) Bit Name Description Default Access
7 MUTE_LD Reserved. 0x0 R/W
6 RESERVED Reserved. 0x0 R
5 RF_DIVSEL_DB Select if DIV_SEL is Double Buffered. 0x0 R/W
4 X4_EN Not Used. 0x0 R/W
3 X2_EN Doubler Path Enable. 0x0 R/W
0: RF doubler off.
1: RF doubler on.
2 RF_EN RFOUT Enable. 0x1 R/W
0: RF8P and RF8N are disabled.
1: RF8P and RF8N are enabled.
[1:0] RF_OUT_POWER Select Output Power Level. 0x3 R/W
0: −4 dBm.
1: −1 dBm.
10: 2 dBm.
11: 5 dBm.

Rev. A | Page 35 of 48
ADF4372 Data Sheet
Address: 0x26, Default: 0x32, Name: REG0026
7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 0

[7:0] BLEED_ICP (R/W)

Bleed Current.

Table 36. Bit Descriptions for REG0026

Bit(s) Bit Name Description Default Access
[7:0] BLEED_ICP Bleed Current. Sets the bleed current. The optimum bleed current is set by ((4/N) × ICP)/3.75, 0x32 R/W
where ICP is the charge pump current in μA.

Address: 0x27, Default: 0xC5, Name: REG0027

7 6 5 4 3 2 1 0
1 1 0 0 0 1 0 1

[7:6] LD_BIAS (R/W) [1:0] RF_PBS (R/W)

Lock Detect Bias. Reserved.
[5] LDP (R/W) [2] VCOLDO_PD (R/W)
Lock Detect Precision. VCO LDO Enable.
[4] BLEED_GATE (R/W) [3] BLEED_EN (R/W)
Gated Bleed. Bleed Enable.

Table 37. Bit Descriptions for REG0027

Bit(s) Bit Name Description Default Access
[7:6] LD_BIAS Lock Detect Bias. The lock detector window size is set by adjusting the lock detector bias in 0x3 R/W
conjunction with the lock detector precision.
0: 5 ns lock detect delay if LDP = 0.
1: 6 ns.
10: 8 ns.
11: 12 ns lock detect delay (for large values of bleed)
5 LDP Lock Detect Precision. Controls the sensitivity of the digital lock detector, depending on INT 0x0 R/W
or FRAC operation selected.
0: FRAC Mode (5 ns).
1: INT Mode (2.4 ns).
4 BLEED_GATE Gated Bleed. 0x0 R/W
0: gate bleed disabled.
1: gate bleed on, digital lock detect (digital lock detect must be enabled)
3 BLEED_EN Bleed Enable. Bleed current applies to a current inside the charge pump to improve the 0x0 R/W
linearity of the charge pump. This current leads to lower phase noise and improved spurious
performance. Set to 1 to enable negative bleed.
0: negative bleed disabled.
1: negative bleed enabled.
2 VCOLDO_PD VCO LDO Enable. For optimal spurious and phase noise performance, disable VCO LDO. 0x1 R/W
0: VCO LDO enabled.
1: VCO LDO disabled.
[1:0] RF_PBS Reserved. 0x1 R/W

Rev. A | Page 36 of 48
Data Sheet ADF4372
Address: 0x28, Default: 0x03, Name: REG0028
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 1

[7:3] RESERVED [0] LOL_EN (R/W)

Loss of Lock Enable.
[2:1] LD_COUNT (R/W)
Lock Detector Count.

Table 38. Bit Descriptions for REG0028

Bits Bit Name Description Reset Access
[7:3] RESERVED Reserved. 0x0 R
[2:1] LD_COUNT Lock Detector Count. Initial value of the lock detector. This field sets the number of counts of PFD 0x1 R/W
within lock window before asserting digital lock detect high.
0: 1024 cycles.
1: 2048 cycles.
10: 4096 cycles.
11: 8192 cycles.
0 LOL_EN Loss of Lock Enable. When loss of lock is enabled, if digital lock detect is asserted, and the 0x1 R/W
reference signal is removed, digital lock detect goes low. It is recommended to set this bit to 1 to
enable loss of lock.
0: loss of lock disabled
1: loss of lock enabled.

Address: 0x2A, Default: 0x00, Name: REG002A

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [0] READ_SEL (R/W)

Readback Select.
[5] BLEED_POL (R/W)
Bleed Polarity. [2:1] RESERVED
[4] RESERVED [3] LE_SEL (R/W)
Reserved.

Table 39. Bit Descriptions for REG002A

Bit(s) Bit Name Description Default Access
[7:6] RESERVED Reserved. 0x0 R
5 BLEED_POL Bleed Polarity. Controls the polarity of the bleed current. Negative is typical usage. 0x0 R/W
0: negative bleed.
1: positive bleed (not recommended).
4 RESERVED Reserved. 0x0 R
3 LE_SEL Reserved. 0x0 R/W
[2:1] RESERVED Reserved. 0x0 R
0 READ_SEL Readback Select. Selects the value to be read back. 0x0 R/W
0: readback VCO, band, and bias compensation data.
1: readback device version ID.

Rev. A | Page 37 of 48
ADF4372 Data Sheet
Address: 0x2B, Default: 0x01, Name: REG002B
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1

[7:6] RESERVED [0] SD_EN_FRAC0 (R/W)

ΣΔ Enable.
[5] LSB_P1 (R/W)
Adds 1/2 bit to FRAC1 when auxiliary [1] RESERVED
SDM is off (VAR_MOD_EN=0) .
[2] SD_LOAD_ENB (R/W)
[4] VAR_MOD_EN (R/W) Mask ΣΔ Reset when REG0010 is
Enable Auxiliary SDM. updated.
[3] RESERVED

Table 40. Bit Descriptions for REG002B

Bit(s) Bit Name Description Default Access
[7:6] RESERVED Reserved. 0x0 R
5 LSB_P1 Adds a half bit to FRAC1 when auxiliary SDM is off (VAR_MOD_EN = 0). Set to 0 for normal 0x0 R/W
operation.
4 VAR_MOD_EN Enable Auxiliary SDM. If FRAC2 is different than 0, this bit is programmed to 1. 0x0 R/W
0: normal operation.
1: enable auxiliary SDM.
3 RESERVED Reserved. 0x0 R
2 SD_LOAD_ENB Mask Σ-Δ Reset when Address 0x10 is Updated. 0x0 R/W
0: reset Σ-Δ when REG0010 is updated.
1: do not reset Σ-Δ when REG0010 is updated.
1 RESERVED Reserved. 0x0 R
0 SD_EN_FRAC0 Σ-Δ Enable. Set to 1 when in integer mode (when FRAC1 = FRAC2 = 0), and set to 0 when in 0x1 R/W
fractional mode.
0: Σ-Δ enabled (for fractional mode).
1: Σ-Δ disabled (for integer mode).

Address: 0x2C, Default: 0x44, Name: REG002C

7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0

[7] RESERVED [0] DISABLE_ALC (R/W)

Autom atic VCO Bias Control (ALC).
[6] ALC_RECT_SELECT_VCO1 (R/W)
Select ALC Rectifier DC Bias (Core [1] VTUNE_CALSET_EN (R/W)
D). Tem perature Dependent VCO Calibration
Voltage.
[5] ALC_REF_DAC_LO_VCO1 (R/W)
Select ALC Threshold Voltage (Core [4:2] ALC_REF_DAC_NOM_VCO1 (R/W)
D). Select VCO ALC Threshold (Core
D).

Table 41. Bit Descriptions for REG002C

Bit(s) Bit Name Description Default Access
7 RESERVED Reserved. 0x0 R
6 ALC_RECT_SELECT_VCO1 Select ALC Rectifier DC Bias (Core D). 0x1 R/W
0: 3.3 V VCO operation.
1: 5 V VCO operation.
5 ALC_REF_DAC_LO_VCO1 Select ALC Threshold Voltage (Core D). 0x0 R/W
0: 5 V VCO operation.
1: 3.3 V VCO operation.
[4:2] ALC_REF_DAC_NOM_VCO1 Select VCO ALC Threshold (Core D). 0x1 R/W
001: 3.3 V and 5 V VCO operation.
1 VTUNE_CALSET_EN Temperature Dependent VCO Calibration Voltage. 0x0 R/W
0: disable temperature dependent VCO calibration voltage.
1: enable temperature dependent VCO calibration voltage.
0 DISABLE_ALC Automatic VCO Bias Control (ALC). 0x0 R/W
0: ALC enabled.
1: ALC disabled.
Rev. A | Page 38 of 48
Data Sheet ADF4372
Address: 0x2D, Default: 0x11, Name: REG002D
7 6 5 4 3 2 1 0
0 0 0 1 0 0 0 1

[7:5] RESERVED [2:0] ALC_REF_DAC_NOM_VCO2 (R/W)

Select VCO ALC Threshold (Core
[4] ALC_RECT_SELECT_VCO2 (R/W) C).
Sets ALC Rectifier DC Bias (Core
C). [3] ALC_REF_DAC_LO_VCO2 (R/W)
Select ALC Threshold Voltage (Core
C).

Table 42. Bit Descriptions for REG002D

Bit(s) Bit Name Description Default Access
[7:5] RESERVED Reserved. 0x0 R
4 ALC_RECT_SELECT_VCO2 Sets ALC Rectifier DC Bias (Core C). 0x1 R/W
0: 3.3 V VCO operation.
1: 5 V VCO operation.
3 ALC_REF_DAC_LO_VCO2 Select ALC Threshold Voltage (Core C). 0x0 R/W
0: 5 V VCO operation.
1: 3.3 V VCO operation.
[2:0] ALC_REF_DAC_NOM_VCO2 Select VCO ALC Threshold (Core C). 0x1 R/W
001: 5 V VCO operation.
010: 3.3 V VCO operation.

Address: 0x2E, Default: 0x10, Name: REG002E

7 6 5 4 3 2 1 0
0 0 0 1 0 0 0 0

[7:5] RESERVED [2:0] ALC_REF_DAC_NOM_VCO3 (R/W)

Select VCO ALC Threshold (Core
[4] ALC_RECT_SELECT_VCO3 (R/W) B).
Sets ALC Rectifier DC Bias (Core
B). [3] ALC_REF_DAC_LO_VCO3 (R/W)
Sets ALC Threshold Voltage (Core
B).

Table 43. Bit Descriptions for REG002E

Bit(s) Bit Name Description Default Access
[7:5] RESERVED Reserved. 0x0 R
4 ALC_RECT_SELECT_VCO3 Sets ALC Rectifier DC Bias (Core B). 0x1 R/W
0: 3.3 V VCO operation.
1: 5 V VCO operation.
3 ALC_REF_DAC_LO_VCO3 Sets ALC Threshold Voltage (Core B). 0x0 R/W
0: 5 V VCO operation.
1: 3.3 V VCO operation.
[2:0] ALC_REF_DAC_NOM_VCO3 Select VCO ALC Threshold (Core B). 0x0 R/W
000: 5 V VCO operation.
010: 3.3 V VCO operation.

Rev. A | Page 39 of 48
ADF4372 Data Sheet
Address: 0x2F, Default: 0x92, Name: REG002F
7 6 5 4 3 2 1 0
1 0 0 1 0 1 0 0

[7] SWITCH_LDO_3P3V_5V (R/W) [2:0] ALC_REF_DAC_NOM_VCO4 (R/W)

Switch LDO Operation Between 3.3 Select VCO ALC Threshold (Core
V and 5 V. A).
[6:5] RESERVED [3] ALC_REF_DAC_LO_VCO4 (R/W)
Select ALC Lower Threshold Voltage
[4] ALC_RECT_SELECT_VCO4 (R/W) Range (Core A).
Sets ALC Rectifier DC Bias (Core
A).

Table 44. Bit Descriptions for REG002F

Bit(s) Bit Name Description Default Access
7 SWITCH_LDO_3P3V_5V Switch LDO Operation Between 3.3 V and 5 V. 0x1 R/W
0: 3.3 V VCO operation.
1: 5 V VCO operation.
[6:5] RESERVED Reserved. 0x0 R
4 ALC_RECT_SELECT_VCO4 Sets ALC Rectifier DC Bias (Core A). 0x1 R/W
0: 3.3 V VCO operation.
1: 5 V VCO operation.
3 ALC_REF_DAC_LO_VCO4 Select ALC Lower Threshold Voltage Range (Core A). 0x0 R/W
0: 5 V VCO operation.
1: 3.3 V VCO operation.
[2:0] ALC_REF_DAC_NOM_VCO4 Select VCO ALC Threshold (Core A). 0x2 R/W
010: 3.3 V and 5 V VCO operation.

Address: 0x30, Default: 0x3F, Name: REG0030

7 6 5 4 3 2 1 0
0 0 1 1 1 1 1 1

[7:0] VCO_BAND_DIV (R/W)

Sets the Autocalibration Tim e per
Stage.

Table 45. Bit Descriptions for REG0030

Bit(s) Bit Name Description Default Access
[7:0] VCO_BAND_DIV Sets the Autocalibration Time per Stage. See the Lock Time section for details. 0x3F R/W

Address: 0x31, Default: 0xA7, Name: REG0031

7 6 5 4 3 2 1 0
1 0 1 0 0 1 1 1

[7:0] TIMEOUT[7:0] (R/W)

Used as Part of the ALC Wait Tim e
and Synthetic Lock Tim e.

Table 46. Bit Descriptions for REG0031

Bit(s) Bit Name Description Default Access
[7:0] TIMEOUT[7:0] Used as Part of the ALC Wait Time and Synthetic Lock Time. See the Lock Time section for details. 0xA7 R/W

Rev. A | Page 40 of 48
Data Sheet ADF4372
Address: 0x32, Default: 0x04, Name: REG0032
7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0

[7] ADC_MUX_SEL (R/W) [1:0] TIMEOUT[9:8] (R/W)

ADC Mux Select. Used as Part of the ALC Wait Tim e
and Synthetic Lock Tim e.
[6] RESERVED
[2] ADC_ENABLE (R/W)
[5] ADC_FAST_CONV (R/W) ADC Enable.
ADC Fast Conversion.
[3] ADC_CONVERSION (R/W)
[4] ADC_CTS_CONV (R/W) Enables ADC Conversion.
ADC Continuous Conversion.

Table 47. Bit Descriptions for REG0032

Bit(s) Bit Name Description Default Access
7 ADC_MUX_SEL Analog-to-Digital Converter (ADC) Mux Select. 0x0 R/W
0: proportional to absolute temperature (PTAT) voltage muxed to ADC input.
1: scaled VTUNE voltage muxed to ADC input.
6 RESERVED Reserved. 0x0 R
5 ADC_FAST_CONV ADC Fast Conversion. 0x0 R/W
0: disabled.
1: enabled.
4 ADC_CTS_CONV ADC Continuous Conversion. 0x0 R/W
0: disabled.
1: enabled.
3 ADC_CONVERSION Enables ADC Conversion. 0x0 R/W
0: no ADC conversion.
1: performs ADC conversion.
2 ADC_ENABLE ADC Enable. 0x1 R/W
0: disabled.
1: enabled.
[1:0] TIMEOUT[9:8] Used as Part of the ALC Wait Time and Synthetic Lock Time. See the Lock Time section 0x0 R/W
for details.

Address: 0x33, Default: 0x0C, Name: REG0033

7 6 5 4 3 2 1 0
0 0 0 0 1 1 0 0

[7:5] RESERVED [4:0] SYNTH_LOCK_TIMEOUT (R/W)

Part of VCO Calibration Routine.

Table 48. Bit Descriptions for REG0033

Bit(s) Bit Name Description Default Access
[7:5] RESERVED Reserved. 0x0 R
[4:0] SYNTH_LOCK_TIMEOUT Part of VCO Calibration Routine. See the Lock Time section for details. 0xC R/W

Address: 0x34, Default: 0x9E, Name: REG0034

7 6 5 4 3 2 1 0
1 0 0 1 1 1 1 0

[7:5] VCO_FSM_TEST_MODES (R/W) [4:0] VCO_ALC_TIMEOUT (R/W)

Reserved. Wait Tim e for ALC Loop to Settle.

Table 49. Bit Descriptions for REG0034

Bit(s) Bit Name Description Default Access
[7:5] VCO_FSM_TEST_MODES Reserved. 0x4 R/W
[4:0] VCO_ALC_TIMEOUT Wait Time for ALC Loop to Settle. See the Lock Time section for details. 0x1E R/W

Rev. A | Page 41 of 48
ADF4372 Data Sheet
Address: 0x35, Default: 0x4C, Name: REG0035
7 6 5 4 3 2 1 0
0 1 0 0 1 1 0 0

[7:0] ADC_CLK_DIVIDER (R/W)

ADC Clock Divider.

Table 50. Bit Descriptions for REG0035

Bit(s) Bit Name Description Default Access
[7:0] ADC_CLK_DIVIDER ADC Clock Divider. ADC_CLK = fPFD/((ADC_CLK_DIV × 4) + 2). Target 100 kHz 0x4C R/W
for ADC_CLK. Refer to AN-2005 for more details.

Address: 0x36, Default: 0x30, Name: REG0036

7 6 5 4 3 2 1 0
0 0 1 1 0 0 0 0

[7:0] ICP_ADJUST_OFFSET (R/W)

Reserved.

Table 51. Bit Descriptions for REG0036

Bit(s) Bit Name Description Default Access
[7:0] ICP_ADJUST_OFFSET Reserved. 0x30 R/W

Address: 0x37, Default: 0x00, Name: REG0037

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] SI_BAND_SEL (R/W)

Selects Band in Core when Test Mode
is Enabled.

Table 52. Bit Descriptions for REG0037

Bit(s) Bit Name Description Default Access
[7:0] SI_BAND_SEL Selects Band in Core when Test Mode is Enabled. 0x0 R/W

Address: 0x38, Default: 0x00, Name: REG0038

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:4] SI_VCO_SEL (R/W) [3:0] SI_VCO_BIAS_CODE (R/W)

Selects Core when Test Mode is Sets VCO Bias when Test Mode is
Enabled. Enabled.

Table 53. Bit Descriptions for REG0038

Bit(s) Bit Name Description Default Access
[7:4] SI_VCO_SEL Selects Core when Test Mode is Enabled. 0x0 R/W
0: all cores off.
1: VCO Core D.
10: VCO Core C.
100: VCO Core B.
1000: VCO Core A.
[3:0] SI_VCO_BIAS_CODE Sets VCO Bias when Test Mode is Enabled. 0x0 R/W
0000: maximum VCO bias (approximately 3.2 V).
1111: minimum VCO bias (approximately 1.8 V).

Rev. A | Page 42 of 48
Data Sheet ADF4372
Address: 0x39, Default: 0x07, Name: REG0039
7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 1

[7] RESERVED [3:0] SI_VTUNE_CAL_SET (R/W)

Select VCO VTUNE Target Voltage
[6:4] VCO_FSM_TEST_MUX_SEL (R/W) when Test Mode is Enabled.
VCO Test Mux Select.

Table 54. Bit Descriptions for REG0039

Bit(s) Bit Name Description Default Access
7 RESERVED Reserved. 0x0 R
[6:4] VCO_FSM_TEST_MUX_SEL VCO Test Mux Select. 0x0 R/W
0: busy.
1: N band.
10: R band.
11: reserved.
100: timeout clock.
101: bias minimum.
110: ADC busy.
111: logic low.
[3:0] SI_VTUNE_CAL_SET Select VCO VTUNE Target Voltage when Test Mode is Enabled. 0x7 R/W
0: 1.18 V.
1: 1.18 V.
10: 1.18 V.
11: 1.18 V.
100: 1.33 V.
101: 1.48 V.
110: 1.63 V.
111: 1.78 V.
1000: 1.93 V.
1001: 2.08 V.
1010: 2.23 V.
1011: 2.38 V.
1100: 2.53 V.
1101: 2.53 V.
1110: 2.53 V.
1111: 2.53 V.

Address: 0x3A, Default: 0x55, Name: REG003A

7 6 5 4 3 2 1 0
0 1 0 1 0 1 0 1

[7:0] ADC_OFFSET (R/W)

VCO Calibration ADC Offset Correction.

Table 55. Bit Descriptions for REG003A

Bit(s) Bit Name Description Default Access
[7:0] ADC_OFFSET VCO Calibration ADC Offset Correction. 0x55 R/W

Rev. A | Page 43 of 48
ADF4372 Data Sheet
Address: 0x3D, Default: 0x00, Name: REG003D
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] RESERVED [5:0] RESERVED

[6] SD_RESET (R/W)
Reserved.

Table 56. Bit Descriptions for REG003D

Bit(s) Bit Name Description Default Access
7 RESERVED Reserved. 0x0 R
6 SD_RESET Reserved. 0x0 R/W
[5:0] RESERVED Reserved. 0x0 R

Address: 0x3E, Default: 0x0C, Name: REG003E

7 6 5 4 3 2 1 0
0 0 0 0 1 1 0 0

[7:4] RESERVED [1:0] RESERVED

[3:2] CP_TMODE (R/W)
Charge Pum p Test Modes.

Table 57. Bit Descriptions for REG003E

Bit(s) Bit Name Description Default Access
[7:4] RESERVED Reserved. 0x0 R
[3:2] CP_TMODE CP Test Modes 0x3 R/W
0: CP tristate
11: normal operation
[1:0] RESERVED Reserved. 0x0 R

Address: 0x3F, Default: 0x80, Name: REG003F

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7:0] CLK1_DIV[7:0] (R/W)

Reserved.

Table 58. Bit Descriptions for REG003F

Bit(s) Bit Name Description Default Access
[7:0] CLK1_DIV[7:0] Reserved. 0x80 R/W

Address: 0x40, Default: 0x50, Name: REG0040

7 6 5 4 3 2 1 0
0 1 0 1 0 0 0 0

[7] RESERVED [3:0] CLK1_DIV[11:8] (R/W)

Reserved.
[6:4] TRM_IB_VCO_BUF (R/W)
Reserved.

Table 59. Bit Descriptions for REG0040

Bit(s) Bit Name Description Default Access
7 RESERVED Reserved. 0x0 R
[6:4] TRM_IB_VCO_BUF Reserved. 0x5 R/W
[3:0] CLK1_DIV[11:8] Reserved. 0x0 R/W

Rev. A | Page 44 of 48
Data Sheet ADF4372
Address: 0x41, Default: 0x28, Name: REG0041
7 6 5 4 3 2 1 0
0 0 1 0 1 0 0 0

[7:0] CLK2_DIVIDER_1[7:0] (R/W)

Reserved.

Table 60. Bit Descriptions for REG0041

Bit(s) Bit Name Description Default Access
[7:0] CLK2_DIVIDER_1[7:0] Reserved. 0x28 R/W

Address: 0x47, Default: 0xC0, Name: REG0047

7 6 5 4 3 2 1 0
1 1 0 0 0 0 0 0

[7:5] TRM_RESD_VCO_MUX (R/W) [4:0] RESERVED

Reserved.

Table 61. Bit Descriptions for REG0047

Bit(s) Bit Name Description Default Access
[7:5] TRM_RESD_VCO_MUX Reserved. 0x6 R/W
[4:0] RESERVED Reserved. 0x0 R

Address: 0x52, Default: 0xF4, Name: REG0052

7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0

[7:5] TRM_RESD_VCO_BUF (R/W) [1:0] RESERVED

Reserved.
[4:2] TRM_RESCI_VCO_BUF (R/W)
Reserved.

Table 62. Bit Descriptions for REG0052

Bit(s) Bit Name Description Default Access
[7:5] TRM_RESD_VCO_BUF Reserved. VCO buffer trim. 0x7 R/W
[4:2] TRM_RESCI_VCO_BUF Reserved. 0x5 R/W
[1:0] RESERVED Reserved. 0x0 R

Address: 0x6E, Default: 0x00, Name: REG006E

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] VCO_DATA_READBACK[7:0] (R)

Open-Loop VCO Counter Readback.

Table 63. Bit Descriptions for REG006E

Bit(s) Bit Name Description Default Access
[7:0] VCO_DATA_READBACK[7:0] Open-Loop VCO Counter Readback. 0x0 R

Address: 0x6F, Default: 0x00, Name: REG006F

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] VCO_DATA_READBACK[15:8] (R)

Open-Loop VCO Counter Readback.

Table 64. Bit Descriptions for REG006F

Bit(s) Bit Name Description Default Access
[7:0] VCO_DATA_READBACK[15:8] Open-Loop VCO Counter Readback. 0x0 R

Rev. A | Page 45 of 48
ADF4372 Data Sheet
Address: 0x70, Default: 0x03, Name: REG0070
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 1

[7:5] BAND_SEL_X2 (R/W) [1:0] BIAS_SEL_X2 (R/W)

Filter Select for Doubler Output Tracking Bias Select for Doubler Output Tracking
Filter. Filter.
[4:2] RESERVED

Table 65. Bit Descriptions for REG0070

Bit(s) Bit Name Description Default Access
[7:5] BAND_SEL_X2 Filter Select for Doubler Output 0x0 R/W
Tracking Filter.
[4:2] RESERVED Reserved. 0x0 R
[1:0] BIAS_SEL_X2 Bias Select for Doubler Output 0x3 R/W
Tracking Bias.

Address: 0x71, Default: 0x60, Name: REG0071

7 6 5 4 3 2 1 0
0 1 1 0 0 0 0 0

[7:5] BAND_SEL_X4 (R/W) [1:0] BIAS_SEL_X4 (R/W)

Not Used. Not Used.
[4:2] RESERVED

Table 66. Bit Descriptions for REG0071

Bit(s) Bit Name Description Default Access
[7:5] BAND_SEL_X4 Not Used. 0x3 R/W
[4:2] RESERVED Reserved. 0x0 R
[1:0] BIAS_SEL_X4 Not Used. 0x0 R/W

Address: 0x72, Default: 0x32, Name: REG0072

7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 0

[7] RESERVED [0] RESERVED

[6] AUX_FREQ_SEL (R/W) [1] COUPLED_VCO (R/W)
Auxillary RF Output Frequency Select. Reserved.
[5:4] POUT_AUX (R/W) [2] RESERVED
Auxiliary RF Output Power.
[3] PDB_AUX (R/W)
Power-Down Auxiliary RF Output.

Table 67. Bit Descriptions for REG0072

Bit(s) Bit Name Description Default Access
7 RESERVED Reserved. 0x0 R
6 AUX_FREQ_SEL Auxiliary RF Output Frequency Select. 0x0 R/W
0: divided output.
1: VCO output.
[5:4] POUT_AUX Auxiliary RF Output Power. Sets the output power at the auxiliary RF output ports. 0x3 R/W
0: −4.5 dBm single-ended ÷ −1.5 dBm differential.
1: 1 dBm single-ended ÷ 4 dBm differential.
10: 4 dBm single-ended ÷ 7 dBm differential.
11: 6 dBm single-ended ÷ 9 dBm differential.
3 PDB_AUX Power-Down Auxiliary RF Output. 0x0 R/W
0: auxiliary RF off.
1: auxiliary RF on.
2 RESERVED Reserved. 0x0 R
1 COUPLED_VCO Reserved. 0x1 R/W
0 RESERVED Reserved. 0x0 R
Rev. A | Page 46 of 48
Data Sheet ADF4372
Address: 0x73, Default: 0x00, Name: REG0073
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:3] RESERVED [0] LD_DIV (R/W)

Lock Detector Count Divider.
[2] ADC_CLK_DISABLE (R/W)
Disable ADC clock. [1] PD_NDIV (R/W)
Power-Down N divider.

Table 68. Bit Descriptions for REG0073

Bits Bit Name Description Default Access
[7:3] RESERVED Reserved. 0x0 R
2 ADC_CLK_DISABLE Disable ADC Clock. ADC_ENABLE setting overwrites this bit. 0x0 R/W
1 PD_NDIV Power-Down N Divider. 0x0 R/W
0 LD_DIV Lock Detector Count Divider. Divides the lock detector count cycles by 32 so that the 0x0 R/W
LD_COUNT bits in Address 0x28 can be selected as 32, 64, 128, and 256.

Address: 0x7C, Default: 0x00, Name: REG007C

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:1] RESERVED [0] LOCK_DETECT_READBACK (R)

Readback of the Lock Detect Bit.

Table 69. Bit Descriptions for REG007C

Bit(s) Bit Name Description Default Access
[7:1] RESERVED Reserved. 0x0 R
0 LOCK_DETECT_READBACK Readback of the Lock Detect Bit. 0x0 R

Rev. A | Page 47 of 48
ADF4372 Data Sheet

OUTLINE DIMENSIONS
7.10
0.30
7.00
PIN 1 0.25
INDICATOR 6.90
AREA
0.20 PIN 1
INDICATOR
37 48
C 0.30 × 0.45°
1
36

5.50 REF EXPOSED 5.00 BSC

SQ PAD SQ

25 12

24 13
0.50 0.45
TOP VIEW BSC BOTTOM VIEW
0.10 0.40
1.158 BSC 0.30
0.70 REF
1.058 SIDE VIEW
FOR PROPER CONNECTION OF
0.958 THE EXPOSED PADS, REFER TO
0.398
THE PIN CONFIGURATION AND
0.358

10-29-2018-A
SEATING FUNCTION DESCRIPTIONS
PLANE
PKG-005474

0.318 SECTION OF THIS DATA SHEET.

Figure 38. 48-Terminal Land Grid Array [LGA]

(CC-48-4)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADF4372BCCZ −40°C to +105°C 48-Terminal Land Grid Array [LGA] CC-48-4
ADF4372BCCZ-RL7 −40°C to +105°C 48-Terminal Land Grid Array [LGA] CC-48-4
EV-ADF4372SD2Z Evaluation Board
1
Z = RoHS Compliant Part.

©2019–2021 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D16984-9/21(A)

Rev. A | Page 48 of 48