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DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
ACADEMIC YEAR 2018-19

LABORATORY MANUAL
SUBJECT: DIGITAL SYSTEM DESIGN LAB

SUB CODE: 18ECL38

SEMESTER: III

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VISION AND MISSION OF THE

INSTITUTE

VISION
Development of academically excellent, culturally vibrant, socially
responsible and globally competent human resources.

MISSION

• To keep pace with advancements in knowledge and make the

students competitive and capable at the global level.
• To create an environment for the students to acquire the right
physical, intellectual, emotional and moral foundations and shine
as torch bearers of tomorrow's society.
• To strive to attain ever-higher benchmarks of educational
excellence.

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ATME COLLEGE OF ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Vision
To develop highly skilled and globally competent professionals in the field of Electronics and
Communication Engineering to meet industrial and social requirements with ethical
responsibility.
Mission

• To provide State-of-art technical education in Electronics and Communication at

undergraduate and post-graduate levels, to meet the needs of the profession and
society and achieve excellence in teaching-learning and research.
• To develop talented and committed human resource, by providing an opportunity for
innovation, creativity and entrepreneurial leadership with high standards of
professional ethics, transparency and accountability.
• To function collaboratively with technical Institutes/Universities/Industries, offer
opportunities for interaction among faculty-students and promote networking with
alumni, industries and other stake-holders.

Program outcomes (POs)

Engineering Graduates will be able to:

PO1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.

PO2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.

PO3. Design/development of solutions: Design solutions for complex engineering problems

and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.

PO4. Conduct investigations of complex problems: Use research-based knowledge and

research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.

PO5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modelling to complex engineering
activities with an understanding of the limitations.

PO6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.

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PO7. Environment and sustainability: Understand the impact of the professional

engineering solutions in societal and environmental contexts, and demonstrate the knowledge
of, and need for sustainable development.

PO8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.

PO9. Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.

PO10. Communication: Communicate effectively on complex engineering activities with

the engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give and
receive clear instructions.

PO11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.

PO12. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological change.

Program Specific Outcomes (PSOs)

At the end of graduation the student will be able,

• To comprehend the fundamental ideas in Electronics and Communication
Engineering and apply them to identify, formulate and effectively solve complex
engineering problems using latest tools and techniques.
• To work successfully as an individual pioneer, team member and as a leader in
assorted groups, having the capacity to grasp any requirement and compose viable
solutions.
• To be articulate, write cogent reports and make proficient presentations while
yearning for continuous self improvement.
• To exhibit honesty, integrity and conduct oneself responsibly, ethically and legally;
holding the safety and welfare of the society paramount.
Program Educational Objectives (PEOs)

• Graduates will have a successful professional career and will be able to pursue higher
education and research globally in the field of Electronics and Communication
Engineering thereby engaging in lifelong learning.
• Graduates will be able to analyse, design and create innovative products by adapting
to the current and emerging technologies while developing a conscience for
environmental/ societal impact.
• Graduates with strong character backed with professional attitude and ethical values
will have the ability to work as a member and as a leader in a team.
• Graduates with effective communication skills and multidisciplinary approach will be
able to redefine problems beyond boundaries and develop solutions to complex
problems of today’s society.

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B. E. (EC / TC)
Choice Based Credit System (CBCS) and Outcome Based Education (OBE)
SEMESTER – III
DIGITAL SYSTEM DESIGN LABORATORY
Laboratory Code 18ECL38 IA Marks 40
Number of Lecture 02Hr Tutorial (Instructions)
Exam Mark 60
Hours/Week + 02 Hours Laboratory
Exam Hour 03
CREDITS – 02
Course objectives: This laboratory course enables students to get practical
experience in design, realization and verification of
• Demorgan’s Theorem, SOP, POS forms
• Full/Parallel Adders, Subtractors and Magnitude Comparator
• Multiplexer using logicgates
• Demultiplexers and Decoders
• Flip-Flops, Shift registers and Counters.
NOTE:
1. Use discrete components to test and verify the logic gates. The IC Revised
numbers given are suggestive; any equivalent ICs can be used. Bloom’s
Taxonomy
2. For experiment No. 11 and 12 any open source or licensed (RBT) Level
simulation tool may be used.
Laboratory Experiments:
1. Verify
(i) Demorgan’sTheoremfor2variables.
L1, L2, L3
(ii) The sum-of product and product-of-sum expressions using
universal gates.
2. Design and implement
(i) Half Adder & Full Adder using i) basic gates. ii) NAND gates L3, L4
(ii) Half subtractor& Full subtractor using i) basic gates ii) NAND gates
3.Designandimplement
(i) 4-bitParallelAdder/Subtractor using IC 7483. L3, L4
(ii) BCD to Excess-3 code conversion and vice-versa.
4. Design and Implementation of
(i) 1-bit Comparator L3, L4
(ii) 5-bit Magnitude Comparator using IC 7485.

5. Realize
(i) Adder &Subtactors using IC 74153. L2, L3, L4
(ii) 4-variable function using IC74151(8:1MUX).
6. Realize (i) Adder &Subtractors using IC74139.
(ii) Binary to Gray code conversion & vice-versa (74139) L2, L3, L4

7. Realize the following flip-flops using NANDGates.

L2, L3
Master-Slave JK, D & T Flip-Flop.

8. Realize the following shift registers usingIC7474/7495

L2, L3
(i) SISO (ii) SIPO (iii)) PISO(iv) )PIPO (v) Ring (vi) Johnson counter

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9. Realize (i) Design Mod – N Synchronous Up Counter & Down Counter

using 7476 JK Flip-flop
L2, L3
(ii) Mod-N Counter using IC7490 / 7476
(iii) Synchronous counter using IC74192

10. Design Pseudo Random Sequence generator using 7495. L2, L3

11. Design Serial Adder with Accumulator and Simulate using Simulation tool. L2, L3, L4

12. Design Binary Multiplier and Simulate using Simulation tool. L2, L3, L4

Course Outcomes: On the completion of this laboratory course, the students will be able to:
• Demonstrate the truth table of various expressions and combinational circuits
using logicgates.
• Design various combinational circuits such as adders, subtractors,
comparators, multiplexers and demultiplexers.
• Construct flips-flops, counters and shift registers.
• Simulate Serial adder and Binary Multiplier.
Conduct of Practical Examination:
• All laboratory experiments are to be included for practical examination.
• Students are allowed to pick one experiment from the lot.
• Strictly follow the instructions as printed on the cover page of answer script for
breakup of marks.
• Change of experiment is allowed only once and 15% Marks allotted to the procedure
part to be made zero.

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

INTRODUCTION

Verification of Logic Gates

Aim: To verify the Truth tables of logic gates

Learning Objective: To study about the functionalities of the logic gates.

Equipments and Components

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7408 (AND Gate) 01
3 IC 7432 (OR Gate) 01
4 IC 7404 (NOT Gate) 01
5 IC 7400 (NAND 2 i/p) 01
6 IC 7402 (NOR Gate) 01
7 IC 7486 (XOR Gate) 01
8 IC 7410 (NAND Gate – 3 i/p) 01
9 IC 7420 (NAND Gate – 4 i/p) 01
10 Patch chords 1 set

Theory

The basic logic gates are the building blocks of more complex logic circuits. These logic gates
perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive OR,
Exclusive-NOR. The small circle on the output of the circuit symbols designates the logic complement. The
AND, OR, NAND, and NOR gates can be extended to have more than two inputs. A gate can be extended
to have multiple inputs if the binary operation it represents is commutative and associative. These basic
logic gates are implemented as small-scale integrated circuits (SSICs) or as part of more complex medium
scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC gates are classified not only by their
logic operation, but also the specific logic-circuit family to which they belong. Each logic family has its
own basic electronic circuit upon which more complex digital circuits and functions are developed. The
following logic families are the most frequently used.
TTL - Transistor-transistor logic
ECL - Emitter-coupled logic
MOS - Metal-oxide semiconductor
CMOS - Complementary metal-oxide semiconductor

DEPT. OF ECE, ATMECE Page 1

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

TTL and ECL are based upon bipolar transistors. TTL has a well-established popularity among
logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS are based on
field effect transistors. They are widely used in large scale integrated circuits because of their high
component density and relatively low power consumption. CMOS logic consumes far less power than
MOS logic. There are various commercial integrated circuit chips available. TTL ICs are usually
distinguished by numerical designation 5as the 5400 and 7400 series.
Procedure

1. Connect the inputs and outputs as shown in the pin diagrams of each IC respectively.
2. Give different inputs and verify the output as in the Truth table for each gate.

TWO INPUT AND GATE

Vcc

1 14 13 LOGIC SYMBOL
2 12

7 A
3 4 11
0 B Y = A.B
4 8 10
5 9

7
6 8
Gnd

TRUTH TABLE

INPUT OUTPUT
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

DEPT. OF ECE, ATMECE Page 2

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

TWO INPUT OR GATE

Vcc

1 14 13
12
2
LOGIC SYMBOL
7 A
3
4 11 B Y=A+B

4 3 10
5 2 9

6 8
7

Gnd

Truth Table

INPUT OUTPUT
A B Y
0 0 0
Truth
0 Table
1 1
NOT GATE 1 0 1
Vcc 1 1 1
1 14 13

2 7 12 Logic Symbol
3 4 11
0
4 4 10 A Y=A

5 9
Truth Table

6 7 8 INPUT OUTPUT
A Y
Gnd 0 1
1 0

DEPT. OF ECE, ATMECE Page 3

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

TWO INPUT NAND GATE

Vcc

1 14 13 Logic Symbol
2 12
A

B Y = AB
3 7 11
4
4 0 10
5 0 9 Truth Table
INPUT OUTPUT
A B Y
0 0 1
0 1 1
6 7 8
1 0 1
1 1 0
Gnd

TWO INPUT NOR GATE

DEPT. OF ECE, ATMECE Page 4

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

TWO INPUT EXOR GATE

THREE – INPUT NAND GATE

Vcc

1 14 13
2 12 LOGIC SYMBOL

A
B
C Y = ABC
3 11
4 7 10 TRUTH TABLE
5 4 9 INPUTS OUTPUT
A B C Y = ABC
1 0 1 0 1
0 0 0 1 1
0 0 0 1
6 8 0 0 1 1
7 1 0 0 1
1 0 1 1
Gnd 1 1 0 1
1 1 1 0

DEPT. OF ECE, ATMECE Page 5

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FOUR INPUT NAND

INPUTS OUTPUT
A B C D Y = ABCD
0 0 0 0 1
0 0 0 1 1
1 14 13 0 0 1 0 1
2 12
0 0 1 1 1
0 1 0 0 1
3 11
0 1 0 1 1
0 1 1 0 1
4 7 10 0 1 1 1 1
5 4 9 1 0 0 0 1
2 1 0 0 1 1
1 0 1 0 1
0 1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
6
1 1 1 0 1
7 8
1 1 1 1 0

OUTCOME:

Understood the fundamentals of the logic gates and ICs.

DEPT. OF ECE, ATMECE Page 6

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

Experiment No. 1

(a) DEMORGAN’S THEOREM FOR 2 VARIABLES

(b) THE SUM-OF PRODUCT AND PRODUCT-OF-SUM EXPRESSIONS USING
UNIVERSAL GATES

Aim: Simplification and realization of given Boolean expression using logic gates [Basic and Universal
gates]

Learning Objectives: After completion of this experiment the students will be able
• To verify De Morgan’s Theorem using logic gates.
• To design and implement SOP and POS expressions using universal gates.

Equipments and components

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7408 02
3 IC 7432 01
4 IC 7410 02
5 IC 7402 03
6 Patch chords 1 set

Procedure
1. Setup the circuit as shown in the diagram

2. Apply different input combinations, observe the output corresponding to input combinations and
verify the Truth Table.

Demorgan’s Theorems are two additional simplification techniques that can be used to simplify Boolean
expressions. Again, the simpler the Boolean expression the simpler the resulting the Boolean expression,
the simpler the resulting logic. ___ _ _
A B =A +B
____ _ _
A+B =A B

Demorgan’s Theorem 1 ____ _ _

A B =A +B

DEPT. OF ECE, ATMECE Page 7

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

Demorgan’s Theorem 2
____ _ _
A+B =A B

Realization of Boolean Expression

F (A, B, C, D) = Σ (7, 13, 14, 15)
F = ABCD + ABCD + ABCD + ABCD – SOP Form
INPUTS OUTPUTS
A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

DEPT. OF ECE, ATMECE Page 8

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

i) K – Map in SOP form

CD
AB 00 01 11 10
00 0 0 0 0
01 0 0 0
1
11 0
1 1 1
10 0 0 0 0
F = ABD + BCD + ABC
Implementation of SOP Form Realization Using Basic Gates
A B C D

1
3 4
6
2
5 1
3
13
11
10 2
8
12 4
6
9
5
1'
3' 4' F = BCD+ABC+ABD
6'

2'
5'

Realization Using Nand Gates

A B C D

1 12
2
13

3 6 1’
4 2’ 12’
5 13’

F = ABD + BCD + ABC

11
10 8
9

DEPT. OF ECE, ATMECE Page 9

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

Result: The above truth table is verified.

Outcome:
• Able to verify DeMorgans Theorem using logic gates.
• Able to optimize simple logic using universal gates.

Viva:

1. Define Universal Gates

2. Why NAND and NOR Gates are called as Universal Gates?
3. State DeMorgons theorem.

DEPT. OF ECE, ATMECE Page 10

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

Experiment No. 2
DESIGN AND IMPLEMENT
(a) HALF ADDRER & FULL ADDER USING BASIC LOGIC GATES & NAND
GATES
(b) HALF SUBTRACTOR & FULL SUBTRACTOR USING BASIC LOGIC
GATES & NAND GATES
Aim:
1. To Realize and verify the Truth Table Full adder using Basic gates and NAND gates.
2. To Realize and verify the Truth Table Full subtractor using Basic gates NAND gates.

Objective:
To study the design and implementation of full adder and full subtractor using basic gates and NAND
gates.

Equipments and Components:

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7486 01
3 IC 7408 01
4 IC 7432 01
5 IC 7404 01
6 IC 7400 03
7 IC 7410 01
8 Patch chords 1 set

Theory:

Half adder adds two single binary digits A and B. It has two outputs, sum (S) And carry (C). The carry
signal represents an overflow into the next digit of a multi-digit Addition. The value of the sum is 2C + S.
The simplest half-adder design, pictured on the Right, incorporates an XOR gate for S and an AND gate for
C.

Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry bit
from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B,
and a carry-in bit, Cin, is called a full-adder. The Boolean functions describing the full-adder are:
S = (A ⊕ B) ⊕ Cin C = AB + Cin (A ⊕ B)
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a
difference bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions describing
the full-subtractor are:
D = (A ⊕ B) ⊕ Cin Br= A ’ B + A’ (Cin) + B (Cin)

DEPT. OF ECE, ATMECE Page 11

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

Procedure

1. For each Adder / subtractor setup the circuit as shown in the diagram

2. Give the input bit combinations, observe the output corresponding to input combinations and
Verify the respective truth tables.

Half Adder using Logic Gates: Half Adder Using Basic Gates

1
A 7486 3
A B S C
B 2
0 0 0 0
1
7408 3
0 1 1 0
2

1 0 1 0

1 1 0 1

i. Full Adder
Truth Table

INPUTS OUTPUTS
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S = A BC + ABC + ABC + ABC

S=A B C

C = AB + BC + AC
Realization of Full Adder Using Basic Gates

DEPT. OF ECE, ATMECE Page 12

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Realization of Full Adder Using Ex-OR and Basic Gates

DEPT. OF ECE, ATMECE Page 13

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

A B C
1
3

2 4 7486
6
S = A B C
5

1
3
1 74323
2

4 2
6
4
6
5
13 5 C = AB+BC+AC
11

12
Full adder using NAND gates

Figure: Full adder using NAND gates

DEPT. OF ECE, ATMECE Page 14

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

Half Subtractor Using Logic Gates

Half Subtractor Using Basic Gates

A B D Bo

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

ii. Full – Subtractor

Truth Table

INPUTS OUTPUTS
A B C D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

D = ABC + A BC + ABC + ABC

D=A B C

B = AC + AB + BC

DEPT. OF ECE, ATMECE Page 15

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

REALIZATION OF FULL SUBTRACTOR USING BASIC GATES

DEPT. OF ECE, ATMECE Page 16

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

REALIZATION USING XOR & BASIC GATES

A B C

1
3

2 4
6
D = A B C
5

1 2 1
3
1 7432
2 4
3 6

4 6 2
5 B = AB + AC + BC
5

9
8

10

Full Subtractor using NAND gates

Figure: Full Subtractor using NAND gates

DEPT. OF ECE, ATMECE Page 17

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

Result: The above truth table is verified.

Outcome:
• Understood the design and implementation of Full Adder and Full Subtractor using basic gates and
NAND gates.
Viva:
1) What is a half adder?
2) What is a full adder?
3) What are the applications of adders?
4) What is a half subtractor?
5) What is a full subtractor?
6) What are the applications of subtractors?
7) Obtain the minimal expression for above circuits.
8) Realize a full adder using two half adders
9) Realize a full subtractors using two half subtractors

DEPT. OF ECE, ATMECE Page 18

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

Experiment No. 3

DESIGN AND IMPLEMENT

a. 4-BIT PARALLEL ADDER / SUBTRACTOR USING IC 7483
b. BCD TO EXCESS-3 CODE CONVERSION USING 7483
Aim: To construct a four-bit binary adder or subtractor using IC 7483

Objective: The students will be able

• To understand the working of IC 7483
• Design Parallel Adder /Subtractor using IC7483

Equipments and Components

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7483 01
3 IC 7486 01
4 Patch chords 1 set
Theory:

The Full adder can add single-digit binary numbers and carries. The largest sum that can be obtained
using a full adder is 112. Parallel adders can add multiple-digit numbers. If full adders are placed in
parallel, we can add two- or four-digit numbers or any other size desired. Figure below uses standard
symbols to show a parallel adder capable of adding two; two-digit binary numbers. The addend would be
on A inputs, and the augend on the B inputs. For this explanation we will

assume there is no input to C0 (carry from a previous circuit To add 102 (addend) and 012 (augend),
the addend inputs will be 1 on A2 and 0 on A1. The augend inputs will be 0 on B2 and 1 on B1.
Working from right to left, as we do in normal addition, let’s calculate the outputs of each full adder.
With A1 at 0 and B1 at 1, the output of adder1 will be a sum (S1) of 1 with no carry (C1). Since A2 is

DEPT. OF ECE, ATMECE Page 19

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

1 and B2 is 0, we have a sum (S2) of 1 with no carry (C2) from adder1. To determine the sum, read
the outputs (C2, S2, and S1) from left to right. In this case, C2 = 0, S2 = 1, and S1 = 1. The sum, then,
of 102 and 012 is 0112. To add four bits we require four full adders arranged in parallel. IC 7483 is a
4- bit parallel adder whose pin diagram is shown.
Procedure
1. Set the circuit.
2. The Mode control is put to zero for addition mode. In this case XOR gate passes that data B0 to
B3. it is then added to A.
3. The Mode control is put to 1 for substraction mode. In this XOR gate passes the date i.e.
complemented values of B0 to B3.
4. Different sets of inputs are taken and output is verified.

Parallel Adder / Subtractor

i) Addition: Mode Control – CIN = 0

A B OUTPUTS
COUT
A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0
1 0 0 0 1 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 1 1 1 0

ii) Subtraction: Mode Control – CIN = 1

A B OUTPUTS
COUT
A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0
0 0 1 1 0 0 1 0 1 0 0 0 1
1 0 0 0 1 0 1 0 0 1 1 1 0
1 0 1 0 1 1 1 0 0 1 1 0 0

16 15 14 13 12 11 10 9
B3 S3 Cout Ci GND B0 A0 S0

IC7483

A3 S2 A2 B2 Vcc S1 B1 A1

1 2 3 4 5 6 7 8

DEPT. OF ECE, ATMECE Page 20

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DIGITAL SYSTEM DESIGN LABORATORY 18ECL38

VCC Output
Carry
A4 5 1
1 C4 7486'
3
Cout
A3 14
3 2

Input Data A A2
8 S4
15
A1 S3
10 2
S2
Data
1 6 Output
3 16 S1
7486 9
B4 2
4
7486
6
4 7483
Input Data B3 5
9
B 8
7486 7
B2 10
12
11
7486 11
B1 13
12
13

GND
C0
S=0
4-BIT Parallel Adder Using 7483 where S=0

IC7483 AS ADDER AND SUBTRACTOR

B3 B2 B1 B0

12 13 9 10
5 4 2 1

7406

A3 A2 A1 A0
11 8 6 3

1 3 8 10 16 4 7 11
Vcc
5
Cin
IC7483 13
Gnd Mode
12
control
Cin = 1- Substraction
14 15 2 6 9
0- Addition

Cout S3 S2 S1 S0

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Example
• 4bit adder operation using 7483

if control input S=0,addition can be performed

Ex: If
↓C0=0
A4 A3 A2 A1=1100
B4 B3 B2 B1=0011
then Sum,S4 S3 S2 S1 =1111
and C0C4 = Cout.

• 4 bit subtraction operation using 7483 for A>B here S=1

A4 A3 A2 A1= 1001
B4 B3 B2 B1= 1101 (2's complement) of +3=0011
The end around carry is disregarded 1 0110
C0 C4 = Bout = 0

Difference, S4 S3 S2 S1 = 0110
2's complement method of subtraction can be performed, if S=1(i.e. C0=1).

Consider the above Example A4 A_

3 A_
2 A_
1= _
1001 and B4 B3 B2 B1= 0011
1’s Complement of B4 B3 B2 B1is B4 B3 B2 B1= 1100

. A4 A3 A2 A1= 1001
_B _B _B _B = 1100→ (1's complement) of +3 = 0011
2’s Complement
of
4 3 2 1
B input = -B
+1 ←C0=1(S&C0 shorted)
The end around carry is disregarded 1 0110
C0 C4 = Bout = 0 +6

• 4 bit subtraction operation using 7483 for A<B here S=1

_A4 _A3_A2_A1= 1110

B4 B3 B2 B1= 0000→ (1's complement) of +15=1111 2’s Complement
of
B input = -B

The end around carry is disregarded 0 1111 → (2's complement) of +1=0001

C0 C4 = Bout = 1 +1 ← C0=1(S&C0
shorted)
-1

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II.BCD to Excess-3 And Vice-Versa Conversion Using 7483 Chip

BCD TO EXCESS-3 CONVERTER
Note: S = 0 and B3, B2, B1, B0 = 0011 vary the BCD input at A3, A2, A1, A0.
Circuit Diagram:

VCC

A3 5
1
A2 14 C4
X NC
3
Input Data A A1
8 E3
15
A0 E2
10 2
E1
Data
1 6 Output
3 16 E0
7486 9
B3 = 0 2

Input Data 4
6
4 7483
7486
B B2 = 0 5
9
8
7486 7
B1 = 1 10
12
11
7486 11
B0 = 1 13
12
13

GND
C0
S=0
BCD to XCS3 using 7483

Truth Table:
Consider Constant Value for B3B2B1B0 = 0011 and S=0
BCD Inputs Excess – 3 Outputs
A3 A2 A1 A0 E3 E2 E1 E
0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X

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1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X

EXCESS-3 to BCD CONVERTER

Note: S=1 and B3,B2,B1,B0 = 0011 vary the Excess-3 input at A3(E3),A2(E2),A1(E1),A0(E0).
Circuit Diagram:

VCC

A3 5
1
A2 14 C4
X NC
3
Input Data A A1
8 D
15
A0 C
10 2
B
Data
1 6 Output
3 16 A
7486 9
B3 = 0 2

Input Data 4
6
4 7483
7486
B B2 = 0 5
9
8
7486 7
B1 = 1 10
12
11
7486 11
B0 = 1 13
12
13

GND
C0
S=1
XCS3 to BCD using 7483

Truth Table:
Consider Constant Value for B3B2B1B0 = 0011 and S=1

Excess-3 Inputs BCD Outputs

E3 E2 E1 E0 A B C D
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

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Result: The 4 bit parallel adder/subtractor and BCD to Excess 3 is verified.

Outcome:
• Students are able to apply knowledge of the Parallel Adder & Subtractor to solve multiple bit
addition/subtraction problems and to convertion of BCD to Excess 3 is verified.
Viva:
Explain the procedure for subtraction of two 4 bit numbers.

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Experiment No. 4

DESIGN AND IMPLEMENTATION OF

a. 1-BIT COMPARATOR
b. 5-BIT MAGNITUDE COMPARATOR USING IC7485
Aim:
Realization of 5 bit comparator using IC 7485.

Objectives:
To study the IC 7485 as a 5 bit Magnitude comparator.

Equipments and Components:

Sl.No. Components Quantity

1 Trainer Kit 01
2 IC 7404 01
3 IC 7485 01
4 IC 7400 01
5 IC 7410 01
6 IC 7402 01
7 IC 7486 01
8 Patch chords 1 set

Theory:
Magnitude Comparator is a logical circuit, which compares two signals A and B and generates three logical
outputs, whether A > B, A = B, or A < B. IC 7485 is a high speed 4-bit Magnitude comparator, which
compares two 4-bit words . The A = B Input must be held high for proper compare operation.
Procedure:

1. Make the connections as shown in the circuit diagrams.

2. Compare the input bit combinations and observe the output in each case.

3. For four – bit comparator compare any two arbitrary 4-bit assumed binary numbers and verify the
truth table
One bit Comparator:
Truth Table

A B A>B A=B A<B

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

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One Bit Comparator Circuit Diagram:

A B

1 3
7404
2 4
1 7408
3
A>B
2
1 7486
3 5 6
A=B
2
4 6
A<B
5

To compare the 4-bit data using 7485 Chip:

Truth Table

INPUTS INPUTS RESULT

A3 A2 A1 A0 B3 B2 B1 B0
0 0 0 1 0 0 0 0 A>B
0 0 0 1 0 0 0 1 A=B
0 0 0 0 0 0 0 1 A<B

To compare two sets of Four Bit Data using 7485 Chip:

Truth Table

Comparing Inputs Cascading Inputs Outputs

A3 B3 A2 B2 A1 B1 A0 B0 A>B A=B A<B A>B A=B A<B
A3> B3 X X X X X X 1 0 0
A3< B3 X X X X X X 0 0 1
A3 = B3 A2 > B2 X X X X X 1 0 0
A3 = B3 A2 < B2 X X X X X 0 0 1

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A3 = B3 A2 = B2 A1 > B1 X X X X 1 0 0
A3 = B3 A2 = B2 A1 < B1 X X X X 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 0 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 1 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 0 0 1 0

0 = Low Level 1 = High Level X = Irrelevant

To compare the given data using 7485 Chip:

Result: The 5 bit magnitude comparator using IC 7485 is verified.

Outcome:
• Students will able to construct, analyze, verify and test 5-bit Magnitude Comparator using IC 7485.

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Viva:
1) What is a comparator?
2) What are the applications of comparator?
3) Derive the Boolean expressions of one bit comparator and two bit comparators.
4) How do you realize a higher magnitude comparator using lower bit comparator?
5) Design a 2 bit comparator using a single Logic gates?

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Experiment No. 5
REALIZE
(a) Adder & Subtractor using IC 74153.
(b) 3-VARIABLE FUNCTION USING IC 74151(8:1 MUX)

Aim:
1. To setup a Half /Full – adder and Half / Full – subtractor using IC74153
2. To verify various functioning of IC 74151

Objective:
• Students will able to realize half adder and half subtractor using IC 74153 and implement 3-variable
function using IC 74151(8:1MUX).

Equipments and components:

Sl.No Components Quantity
1 Trainer Kit 01
2 IC 7420 03
3 IC 7400 01
4 IC 7404 01
5 IC 74151 01
6 Patch chords 1 set

Theory:

Multiplexers are very useful components in digital systems. They transfer a large number of information
units over a smaller number of channels, (usually one channel) under the control of selection signals.
Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one output. By using
control signals (select lines) we can select any input to the output. Multiplexer is also called as data selector
because the output bit depends on the input data bit that is selected. The general multiplexer circuit has 2n
input signals, n control/select signals and 1 output signal.

Procedure:
1) The Pin [16] is connected to + Vcc and Pin [8] is connected to ground.
2) The inputs are applied either to ‘A’ input or ‘B’ input.
3) If MUX ‘A’ has to be initialized, EA is made low and if MUX ‘B’ has to be initialized, EB is
made low.
4) Based on the selection lines one of the inputs will be selected at the output, and thus the truth
table is verified.
5) In case of half adder using MUX, apply constant inputs at (I0a, I1a, I2a, I3a)and(I0b, I1b, I2b and I3b)
as shown.
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6) The corresponding values of select input lines, A and B (S1 and S0) are changed as per table and
the output is taken at Za as sum and Zb as carry.
7) In this case, the inputs A and B are varied. Making Ea and Eb zero and the output is taken at Za,
and Zb.
8) In case of Half Subtractor, connections are made according to the circuit, Inputs are applied at
A and B as shown, and outputs are taken at Za (Difference) and Zb (Borrow). Verify outputs.
9) In full adder using MUX, the inputs are applied at Cn-1, An and Bn according to the truth table.
The corresponding outputs are taken at Sn (pin Za) and Cn (pin Zb) and are verified according to
the truth table.
10) In full subtractor using MUX, the inputs are applied at Cn-1, An and Bn according to the truth
table. The corresponding outputs are taken at pin Za(Difference) and pin Zb(Borrow) and are
verified according to the truth table.

Half Adder Using 74153 Half Subtractor using 74153

Truth Table:
Inputs Half Adder Outputs Half Subtractor Outputs
A B Sum Carry Diff Borrow
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 0 1 0
1 1 0 1 0 0

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Full Adder Using 74153 Full Subtractor using 74153

Truth Tables for Full Adder/Subtractor using 74153

Inputs Full Adder Outputs Full Subtractor Outputs
A B Cin/Bin S Cout D Bout
0 0 0 0
0 0 0
1 0 1 1
0 0 1
1 0 1 1
0 1 0
0 1 0 1
0 1 1
1 0 1 0
1 0 0
0 1 0 0
1 0 1
0 1 0 0
1 1 0
1 1 1 1
1 1 1

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Block diagram and Truth Table of 8:1 MUX :

Pin Diagram of IC 74151:

Ex: Implement the following Boolean function using 8:1 multiplexer.

F (A, B, C, D) = ∑m (2, 4, 5, 7, 10, 14)

Design Using MSB Bit A:

Fig: Design Table

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Fig: Logic Diagram

Design Using LSB Bit D:

Fig: Design Table Fig: Logic Diagram

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Full Adder using 74151:

Result: 4:1 Multiplexer using gates and 3-variable function using 74151 is verified.

Outcome:

Understood the realization of half adder, half subtractor and 3 variable function using Multiplexers.

Viva:

1 What is a multiplexer?

2 How many select lines are there in a 4:1 Mux?

3 What are the applications of Multiplexer?

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Experiment No. 6(A)

REALIZE BOOLEAN EXPRESSION USING IC 74139

Aim:

To realize Boolean Expression Using IC 74139

Objective:
• To study the IC 74139 and to implement Boolean function using IC 74139.

Equipments and components:

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 74138 02
3 IC 7420 02
4 IC 7410 02
5 IC 7400 02
6 IC 7404 01
7 Patch chords 1 set

Theory:
Decoder IC 74139 is a Dual Demux (2 Line to 4 Line Decoder). De-multiplexers perform the opposite
function of multiplexers. They transfer a small number of information units (usually one unit) over a larger
number of channels under the control of selection signals. The general de-multiplexer circuit has 1 input
signal, n control/select signals and 2n output signals. De-multiplexer circuit can also be realized using a
decoder circuit with enable. A decoder is a combinational circuit that connects the binary information from
‘n’ input lines to a maximum of 2n unique output lines. Decoder is also called a min-term generator/max-
term generator. A min-term generator is constructed using AND and NOT gates. The appropriate output is
indicated by logic 1 (positive logic). Max-term generator is constructed using NAND gates. The
appropriate output is indicated by logic 0 (Negative logic).
Procedure:

1) The Pin [16] is connected to + Vcc and Pin [8] is connected to ground.
2) The inputs are applied either to ‘A’ input or ‘B’ input.
3) If DEMUX ‘A’ has to be initialized, EA is made low and if DEMUX ‘B’ has to be
initialized, EB is made low.
4) Based on the selection lines one of the inputs will be selected at the set of outputs, and thus
the truth table is verified.

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5) In case of half adder using DEMUX, Ea is set to 0, the corresponding values of select input
lines, A and B (S1a and S0a) are changed as per table and the output is taken at Sum and
Carry. Verify outputs.
6) In case of Half Subtractor, connections are made according to the circuit, Inputs are applied
at A and B as shown, and outputs are taken at Difference and Borrow. Verify outputs.
7) In full adder using DEMUX, the inputs are applied at Cn-1, An and Bn according to the truth
table. The corresponding outputs are taken at Sum and Carry, and are verified according to
the truth table.
8) In full subtractor using DEMUX, the inputs are applied at Cn-1, An and Bn according to the
truth table. The corresponding outputs are taken at Difference and Borrow as shown, and are
verified according to the truth table.

Half Adder Using 74139

Half Subtractor Using 74139

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Truth Table:
Half Subtractor
Inputs Half Adder Outputs
Outputs
A B Sum Carry Diff Borrow
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 0 1 0
1 1 0 1 0 0

Full Adder Using 74139

Full Subtractor Using 74139

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Truth Table:
Full Adder Full Subtractor
Inputs Outputs Outputs
A B Cin/Bin S Cout D Bout
0 0 0 0
0 0 0
1 0 1 1
0 0 1
1 0 1 1
0 1 0
0 1 0 1
0 1 1
1 0 1 0
1 0 0
0 1 0 0
1 0 1
0 1 0 0
1 1 0
1 1 1 1
1 1 1

Result:

Realized Boolean expression using IC 74139

Outcome:

Acquired the knowledge to implement the Boolean expression using IC 74139.

Viva:

1. What is a decoder?
2. What are the differences between decoders and encoders?

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Experiment No. 6(B)

BINARY TO GRAY CONVERTER AND VICE VERSA(74139)

Aim: To realize
i. Binary to Gray Converter using logic gates.
ii. Gray to Binary Converter using logic gates.
Objective:
• To study the IC 74139 and to implement Binary to Gray and Gray to Binary using IC 74139.

Components Required: IC 7486, trainer Kit, IC 74139 and Patch chords etc.

Theory: Binary code is a way of representing the text or the data generated by the computers and other
devices. In binary coding the text or the data is represented in a stream of bits of 1's and 0’s. Binary is a
weighted system. That is weighted as ......8,4,2,1. So for forming 7, you just need 111. Similar computation
for other decimal numbers. GRAY CODES are non weighted codes that is they cannot be provided a
weight to calculate their equivalent in decimal .Gray codes are often called reflected binary code , the
reason is clear if you compare the column of gray code with the binary code .
If we want to calculate the gray code of 0110. The following steps are performed-
1) The M.S.B is written as it is, that is 0.
2) Then the M.S.B and the digit and right side of it is XOR'ed to obtain the next digit in gray
code. 0 is XOR'ed with 1, so the output next digit is 1.
3) Similarly other digits are XORed to obtain the gray code.
The conversion of gray to binary code also requires XOR'ing .but this time bits of gray code is
XOR'ed with output binary code bits.

The M.S.B is written as it is. Then the output M.S.B in binary is XOR'ed with the adjacent bit in the gray
code. And then the next adjacent bit if gray code is XOR'ed with last obtained binary bit.

Procedure: -
1) Verify that the gates are working properly.
2) Write the proper truth table for the given Binary to Gray converter.
3) Draw Karnaugh maps for each bit of output. Simplify the Karnaugh maps to get simplified
Boolean Expressions.
4) Make connections on the trainer kit as shown in the circuit diagram for the Binary to Gray
converter.
5) Apply the Binary inputs at B3-B0 pins, according to the truth table.
6) Check the outputs at the G3-G0 pins and note them down in the table for the corresponding inputs.
7) Verify that the outputs match with the expected results.
8) Repeat the procedure to design, test and verify the working of a Grey to Binary Converter.

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Binary to Gray Converter.

Truth Table:
Binary Input Gray Code Output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Karnaugh Maps:
For G3: For G2:

G3 = B3

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For G1: For G0:

Circuit:

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Gray to Binary Converter

Truth Table
Gray Code Input Binary Output
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

Karnaugh Maps:
For B3: For B2:

B3 = G3

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For B1: For B0:

Circuit:

Result: The above truth table is verified.

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Experiment No. 7

REALIZE MASTER SLAVE JK, D AND T FLIPFLOP USING NAND GATES

Aim: To verify the truth table of master slave JK, D and T Flip flop.

Objective:
To study the Master Slave JK, D and T Flip Flop.

Equipments and components:

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7400 02
3 IC 7410 02
4 Patch chords 1 set

Theory:

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state
information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals
applied to one or more control inputs and will have one or two outputs. It is the basic storage element in
sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used
in computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state,
and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next
state depend not only on its current input, but also on its current state (and hence, previous inputs). It can
also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference
timing signal.
Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the
simple ones are commonly called latches. The word latch is mainly used for storage elements, while
clocked devices are described as flip-flops. A latch is level-sensitive, whereas a flip-flop is edge-sensitive.

Procedure:

1. Connections are made as shown in circuit diagram

2. The clock pulses are applied, different inputs are given and for each circuit, the truth table is
verified.

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Master Slave J.K.Flip Flop:

Present and Clear Functions:

Clock Pr Clr Q Comment
X 0 1 1 Set
X 1 0 0 Reset
X 0 0 ☼ Invalid
1 1 - Normal F / F

Truth Table:
Comment
Clock Pr Clr J K Q
Q
X 1 1 0 0 No change Previous

1 1 0 1 0 1 Reset

1 1 1 0 1 0 Set

1 1 1 1 Q Toggle
Q

Master Slave JK Flip – Flop Circuit [Using NAND]:

Pr
1 7410 9
10 8 4 7400
J 2 12 6 1'
3'
11 Q
13 5
1 2'
3
clk
2
1' 10 13
3 8 Q
6 2' 12'
K 12 11
4 9
5 13'
clr

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Master Slave T Flip Flop:

Truth Table:

Preset Clear T Clock

1 1 0

1 1 1

Master Slave T Flip – Flop Circuit [Using NAND]:

Master Slave D Flip Flop:

Truth Table:

Preset Clear D Clock

1 1 0 0 1

1 1 1 1 0

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Master Slave D Flip – Flop Circuit [Using NAND]:

Result: Master Slave JK, T and D Flip Flops are verified using NAND gates.

Outcome:
• Students got familiarized with the fundamentals of sequential circuits.
• Understood the concepts of MS JK, T and T FF.
Viva:
1. What are the differences between combinational and sequential circuits?
2. What is the limitation in SR latch?
3. What is race around condition? How to eliminate it?
4. What do you mean by 0’s and 1’s catching? How to eliminate it?
5. Draw the waveforms of master slave flip flops.
6. What are edge triggered flip flops?

DEPT. OF ECE, ATMECE Page 48

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Experiment No. 8(a)

REALIZE THE FOLLOWING SHIFT REGISTERS USING IC7474/IC 7495

(A)SISO (B) SIPO (C) PISO (D) PIPO

Aim: To realize and verify the shift registers.

Objective:
• To make the students competent in performing Shift Left, Shift Right, SISO, SIPO, PISO, PIPO
operations using IC 7474/IC 7495.

Equipments and Components:

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7495 02
3 Patch chords 1 set

Theory: In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the
output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a
circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its input and
shifting out the last bit in the array, at each transition of the clock input.

More generally, a shift register may be multidimensional, such that its "data in" and stage outputs are
themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in
parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often configured as 'serial-in,
parallel-out' (SIPO) or as 'parallel-in, serial-out' (PISO). There are also types that have both serial and
parallel input and types with serial and parallel output. There are also 'bidirectional' shift registers which
allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register can also
be connected to create a 'circular shift register'

Procedure:
A. Serial In-Parallel Out (Left Shift):
1) Make the connections as shown in the respective circuit diagram.
2) Make sure the 7495 is operating in Parallel mode by ensuring Pin 6 (Mode M) is set to
HIGH, and connect clock input to Pin 8 (Clk 2).
3) Apply the first data at pin 5 (D) and apply one clock pulse. We observe that this data appears
at pin 10 (QD).
4) Now, apply the second data at D. Apply a clock pulse. We now observe that the earlier data
is shifted from QD to QC, and the new data appears at QD.
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5) Repeat the earlier step to enter data, until all bits are entered one by one.
6) At the end of the 4th clock pulse, we notice that all 4 bits are available at the parallel output
pins QA (MSB), QB, QC, QD (LSB).
7) Enter more bits to see there is a left shifting of bits with each succeeding clock pulse.
B. Serial In-Parallel Out (Right Shift):
1) Make the connections as shown in the respective circuit diagram.
2) Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode M) is set to LOW,
and connect clock input to Pin 9 (Clk 1).
3) Apply the first data at pin 1 (SD1) and apply one clock pulse. We observe that this data
appears at pin 13 (QA).
4) Now, apply the second data at SD1. Apply a clock pulse. We now observe that the earlier
data is shifted from QA to QB, and the new data appears at QA.
5) Repeat the earlier step to enter data, until all bits are entered one by one.
6) At the end of the 4th clock pulse, we notice that all 4 bits are available at the parallel output
pins QA through QD.
7) Enter more bits to see there is a right shifting of bits with each succeeding clock pulse.
C. Serial In-Serial Out Mode:
1) Connections are made as shown in the SISO circuit diagram.
2) Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set to LOW, and
connect clock input to Clk 1(Pin 9).
3) The 4 bits are applied at the Serial Input pin (Pin 1), one by one, with a clock pulse in
between each pair of inputs to load the bits into the IC.
4) At the end of the 4th clock pulse, the first data bit, ‘d0’ appears at the output pin QD.
5) Apply another clock pulse, to get the second data bit ‘d1’ at QD. Applying yet another clock
pulse gets the third data bit ‘d2’ at QD, and so on.
6) Thus we see the IC 7495 operating in SISO mode, with serially applied inputs appearing as
serial outputs.

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D. Parallel In-Serial Out Mode:

1) Connections are made as shown in the PISO circuit diagram.
2) Now apply the 4-bit data at the parallel input pins A, B, C, D (pins 2 through 5)
3) Keeping the mode control M on HIGH, apply one clock pulse. The data applied at the
parallel input pins A, B, C, D will appear at the parallel output pins QA, QB, QC, QD
respectively.
4) Now set the Mode Control M to LOW, and apply clock pulses one by one. Observe the data
coming out in a serial mode at QD.
5) We observe now that the IC operates in PISO mode with parallel inputs being transferred to
the output side serially.
E. Parallel In-Parallel Out Mode:
1) Connections are made as shown in the PIPO mode circuit diagram.
2) Set Mode Control M to HIGH to enable Parallel transfer.
3) Apply the 4 data bits as input to pins A, B, C, D.
4) Apply one clock pulse at Clk 2 (Pin 8).
5) Note that the 4 bit data at parallel inputs A, B, C, D appears at the parallel output pins QA,
QB, QC, QD respectively.

IC 7495 Pin Diagram:

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A. SIPO Mode (Left Shift)

Circuit: Truth Table:

Serial
Clock QA QB QC QD
I/P

1 1 X X X 1
1
2 0 X X 1 0

3 1 X 1 0 1

4 1 1 0 1 1

A. SIPO MODE (Right Shift)

Circuit: Truth Table:

Serial
Clock QA QB QC QD
I/P

1 1 1 X X X

2 0 0 1 X X

3 1 1 0 1 X

4 1 1 1 0 1

B. SISO Mode
Circuit: Serial
Clock QA QB QC QD
I/P
1 d0=0 0 X X X
2 d1=1 1 0 X X
3 d2=1 1 1 0 X
4 d3=1 1 1 1 0=d0
5 X X 1 1 1=d1
6 X X X 1 1=d2
7 X X X X 1=d3

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A. PISO Mode
Circuit: Truth Table:

Cl
Mode Parallel I/P Parallel O/P
k
Q Q Q Q
A B C D
A B C D

1 1 1 0 1 1 1 0 1 1
0 2 X X X X X 1 0 1
0 3 X X X X X X 1 0
0 4 X X X X X X X 1

B. PIPO Mode
Circuit: Truth Table:

Clk Parallel I/P Parallel O/P

A B C D QA QB QC QD
1 1 0 1 1 1 0 1 1

Result: The shift registers using IC 7495 are verified.

Outcome:
• Students got exposure to Shift Left, Shift Right, SISO, SIPO, PISO, PIPO operations using IC 7495.

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Experiment No. 8(b)

Realize the (A) RING COUNTER (B) JOHNSON COUNTER using IC
7474/IC7495
Aim: To design and study the operation of a ring counter and a Johnson Counter.

Objective : To study the operation of Ring counter and Johnson counter.

Components Required: IC 7495, IC 7404, etc.

Theory: A ring counter is a type of counter composed of a type circular shift register. The output of the
last shift register is fed to the input of the first register.

Procedure: -
1) Make the connections as shown in the respective circuit diagram for the Ring Counter.
2) Apply an initial input (1000) at the A, B, C, D pins respectively.
3) Keep Select Mode = HIGH (1) and apply one clock pulse.
4) Next, Select Mode = LOW (0) to switch to serial mode and apply clock pulses.
5) Observe the output after each clock pulse, record the observations and verify that they match the
expected outputs from the truth table.
6) Repeat the same procedure as above for the Johnson Counter circuit and verify its operation.

A. Ring Counter

Circuit: Truth Table:

Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 0 1 0 0
0 3 0 0 1 0
0 4 0 0 0 1
0 5 1 0 0 0
0 6 0 1 0 0

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B. Johnson Counter
Circuit: Truth Table:

Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 1 1 0 0
0 3 1 1 1 0
0 4 1 1 1 1
0 5 0 1 1 1
0 6 0 0 1 1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0
0 10 1 1 0 0

Result: The Ring Counter and Johnson Counter using IC 7495 are verified.

Outcome:
• Students got exposure to Ring Counter and Johnson Counter operations using IC 7495.

Viva:
1. What are shift registers?
2. Explain the operations of shift registers?
3. Explain the operation of switch tail counter.
4. Give the applications of shift registers.

DEPT. OF ECE, ATMECE Page 55

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Experiment No. 9

REALIZE MOD-N COUNTER USING IC7476/IC7490/IC 74192

Aim: Realize i) Design Mod N Synchronous Up Counter using IC7476 JK Flip Flop
ii) Mod N Asynchronous counter using IC7490 and
iii) Mod-N Synchronous counters using IC 74192.
Objective:
• To make the students competent in realizing of Mod N counter using IC 7490/ IC 74192.

Equipments and components:

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7490 01
3 IC 7400 01
4 IC 74192 01
5 Patch chords 1 set

Theory:
In digital logic and computing, a counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in relationship to a clock signal. In
electronics, counters can be implemented quite easily using register-type circuits such as the flip-flop, and a
wide variety of classifications exist:

• Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-flops
• Synchronous counter – all state bits change under control of a single clock
• Decade counter – counts through ten states per stage

Counters are useful for digital clocks and timers, and in oven timers, VCR clocks, etc.

Procedure:

1. Connections are made as shown in circuit diagram.

2. Apply clock pulses and observe the output and verify the Truth Table.

a) Asynchronous counter using

IC7490

Internal Diagram of 7490:

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Function Table :

Clock MR1 MR2 MS1 MS2 Q3 Q2 Q1 Q0 Remarks

X 1 1 0 X 0 0 0 0 Reset
X 1 1 X 0 0 0 0 0 Reset
X X X 1 1 1 0 0 1 Set to 9
X 0 X 0 Count
0 X 0 X Count
0 X X 0 Count
X 0 0 X Count

Logic Diagram of Mod-10 counter (Decade Counter):

Truth Table

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Clock Outputs
Pulses Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Mod 8 Counter using 7490:

Truth Table for Mod-8 Counter:

Synchronous counter using IC74192

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Pin Configuration:

Function Table:

Truth table:

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Result: MOD N Counter using IC 7490 and IC 74192 is verified.

Outcome:
• Understood the synchronous and Asynchronous counter using IC 74192 and IC 7490.

Viva:
1. Bring out the differences between synchronous and asynchronous counters.
2. What is a counter?
3. Give the applications of counters.

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Experiment No. 10
Design Pseudo Random Sequence generator using 7495
Aim: Design pseudo random sequence generator using IC 7495.

Objective: To design and study the operation of a Sequence Generator.

Components Required: IC 7495, IC 7486, etc.

Theory: In order to generate a sequence of length ‘S’, it is necessary to use at least ‘N’ number of Flip-
flops, in order to satisfy the condition. .
The given sequence length S = 15
Therefore, N = 4

Note: There is no guarantee that the given sequence can be generated by 4 flip-flops. If the sequence is not
realizable by 4 flip-flops, we need to use 5 flip-flops, and so on.

Procedure:
1) Truth table is constructed for the given sequence, and Karnaugh maps are drawn in order to obtain a
simplified Boolean expression for the circuit.
2) Connections are made as shown in the circuit diagram.
3) Mode M is set to LOW (0), and clock pulses are fed through Clk 1 (pin 9).
4) Clock pulses are applied at CLK 1 and the output values are noted, and checked against the expected
values from the truth table.
5) The functioning of the circuit as a sequence generator is verified.

Circuit:

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Truth Table: Karnaugh Map:

.
O/p
Map
Clock QA QB QC QD
Value
D
15 1 1 1 1 1 0
7 2 0 1 1 1 0
3 3 0 0 1 1 0
1 4 0 0 0 1 1
8 5 1 0 0 0 0
4 6 0 1 0 0 0
2 7 0 0 1 0 1
9 8 1 0 0 1 1
12 9 1 1 0 0 0
6 10 0 1 1 0 1
11 11 1 0 1 1 0
5 12 0 1 0 1 1
10 13 1 0 1 0 1
13 14 1 1 0 1 1
14 15 1 1 1 0 1
1 1 1
1 1
1

Result: Pseudo random sequence is generated using IC 7495.

Outcome: Understood the IC 7495 as a sequence generator.

Viva:
1. What is a sequence generator?
2. Explain how to generate the sequence using IC 7495.

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Experiment No. 11

DESIGN SERIAL ADDER WITH ACCUMULATOR AND DESIGN USING SIMULATION TOOL

Aim: To Simulate Serial Adder with Accumulator using logic-sim.

Objectives:
• Students will study the design of serial adder with accumulator.

Software Required:
Theory:
Logic Diagram:

Truth Table:

Result: The Serial adder with accumulator output is verified using Electronic Work Bench.

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Outcome:
• Acquired the knowledge about the simulation of Serial adder with accumulator using Electronic
work bench.

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Experiment No. 12

BINARY MULTIPLIER AND SIMULATE USING SIMULATION TOOL.

Aim: To Simulate Binary multiplier using Logicsim.

Objectives:
• Students will study the design of Binary multiplier.

Software Required:
Theory:
Logic Diagram:

Truth table:

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Result: The Binary Multiplier output is verified using Electronic Work Bench.

Outcome:
• Acquired the knowledge about the simulation of Binary Multiplier using Electronic work bench.

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Additional Viva Questions

1. Define a logic gate.
2. What are basic gates?
3. Why NAND and NOR gates are called as universal gates.
4. State De-Morgan’s theorem
5. Give examples for SOP and POS
6. Explain how transistor can be used as NOT gate
7. Explain AND and OR gate using diodes
8. Realize logic gates using NAND and NOR gates only
9. Define LSI, MSI , SSI
10. List the applications of EX-OR and EX~NOR gates
11. What is a truth table?
12. What is a half adder?
13. Differentiate between half adder and half subtractor
14. What is a full adder?
15. Differentiate between combinational and sequential circuits. Give examples
16. Give the applications of combinational and sequential circuits
17. Give the block diagram of sequential circuits
18. Define flip flop
19. What is an excitation table/functional table
20. Differentiate between flip flop and latch
21. What is race around condition?
22. How do you eliminate race around condition
23. Give the block diagram of parallel adders
24. What are BCD Give their applications or uses
25. What are minterms and maxterms?
26. Explain the working of 7483 adder chip. Explain how it can be used as EX-3 to BCD
conversion and vice versa
27. Define multiplexer/ data selector
28. What is a Demultiplexer?
29. Give the applications of mux and demux
30. What is a encoder and decoder
31. Compare mux and encoder
32. Compare demux and decoder
33. What is a priority encoder?
34. What is a code converter?
35. What are counters? Give their applications
36. Compare synchronous and asynchronous counters
37. What is a ripple counter?
38. What is modulus of a number?
39. What is a shift register?
40. Explain how a shift register can be used as ring and johnson counter
41. Give the applications of johnson and ring counters
42. What is an up counter and down counter?
43. What is common cathode and common anode LED?
44. What is LCD and LED.
45. What is a static and a dynamic display.
DEPT. OF ECE, ATMECE Page 67
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46. List the types of LCD's and LED's.

47. What does LS stand for, in 74LS00?
48. Mention the different logic families.
49. Which is the fastest logic?

VIVA QUESTIONS WITH ANSWER

1) What are logic gates?

In electronics, a logic gate is an idealized or physical device implementing a Boolean function;

that is, it performs a logical operation on one or more logical inputs, and produces a single logical
output.
2) What are universal gates?
A Logic Gate which can infer any of the gate among Logic Gates. OR a gate which can be use to
create any Logic gate is called Universal Gate. NAND and NOR Gates are called Universal Gates
because all the other gates can be created by using these gates
3) What are combinational circuits and sequential circuits?

In digital circuit theory, combinational logic (sometimes also referred to as time-independent

logic[1] ) is a type of digital logic which is implemented by Boolean circuits, where the output is
a pure function of the present input only. This is in contrast to sequential logic, in which the output
depends not only on the present input but also on the history of the input. In other words, sequential
logic has memory while combinational logic does not.

4) How many variables does octet quad and pair eliminate?

Quad -2, octet -3, pair –one.
5) What are k maps?
A Karnaugh map (K-map for short) is a useful tool used in the simplification of combinational
boolean equations and the creation of sequential logic circuits. Karnaugh maps were created by
Maurice Karnaugh in 1953.
6) What codes are used for row and column heading in K maps?
Gray Codes.
7) Which is the most suitable reduction technique for more variables?
VEM

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8) What is a multiplexer?
A multiplexer (or mux) is a device that selects one of several analog or digital input signals and
forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are
used to select which input line to send to the output.
9) What is the relation between select line and data line in multiplexer?
LoWg2 N. N=Data lines
10) What is Demux?
A demultiplexer, sometimes abbreviated demux, is a circuit that has one input and more than one
output. It is used when a circuit wishes to send a signal to one of many devices. This description sounds
similar to the description given for a decoder, but a decoder is used to select among many devices while
a demultiplexer is used to send a signal among many devices.
11) What is a decoder?
A decoder is a circuit that changes a code into a set of signals. It is called a decoder because it does
the reverse of encoding, but we will begin our study of encoders and decoders with decoders because
they are simpler to design.
12) What is a encoder?
An encoder is a circuit that changes a set of signals into a code
13) How many half adders are required to construct full adder
TWO.
14) How many full adders does N bit parallel adder use
N
15) What is the disadvantage of RCA
Propagation delay
16) What is a Carry look ahead adder?
The Carry Look Ahead 4-bit adder can also be used in a higher-level circuit by having each CLA
Logic circuit produce a propagate and generate signal to a higher-level CLA Logic circuit. The group
propagate ( ) and group generate ( ) for a 4-bit CLA are
17) What is half adder?
Half Adder: is a combinational circuit that performs the addition of two bits, this circuit needs
two binary inputs and two binary outputs.
18) What is Full Adder?

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The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary
numbers, a sum (S) and a carry (C1)
19) What is a bistable element?
It has 2 stable states
20) What is a latch?
A latch is an electronic logic circuit that has two inputs and one output. One of the inputs is called the
SET input; the other is called the RESET input
21) What is a flip flop?
A flip-flop or latch is a circuit that has two stable states and can be used to store state information.
A flip-flop is a bistable multivibrator.
22) What are registers?
Group of flip flops
23) What are counters?
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number
of times a particular event or process has occurred
23) What is difference between asynchronous and synchronous counter?
Asynchronous- Clock for only first Flip Flop.
Synchronous-Clock for all Flip flops.
24) What is a decade counter?
Counts from 0-9
25) What is the difference between ring and Johnson counter?
Ring Counter- Last flip flop out fed to first flip flop.
Johnson Counter- Last flip flop inversion fed to first flip flop.

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