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Schematic-V1 3

The document contains a schematic diagram for an encoder counter circuit, detailing various components such as the STM32G030F6P6 microcontroller, resistors, capacitors, and connections for Grove I2C interfaces. It includes pin assignments for communication protocols like USART and GPIO, as well as power supply connections. The layout is designed for use with a 0.96" OLED display and incorporates multiple integrated circuits for signal processing.
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0% found this document useful (0 votes)
20 views1 page

Schematic-V1 3

The document contains a schematic diagram for an encoder counter circuit, detailing various components such as the STM32G030F6P6 microcontroller, resistors, capacitors, and connections for Grove I2C interfaces. It includes pin assignments for communication protocols like USART and GPIO, as well as power supply connections. The layout is designed for use with a 0.96" OLED display and incorporates multiple integrated circuits for signal processing.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1 2 3 4 5 6

+3.3V U1
STM32G030F6P6
J1

2
GROVE_SDA 1 20 GROVE_SCL
Grove 3 1 PB7/PB8 PB3/PB4/PB5/PB6
1 2 19 SWCLK_CANCEL
GND PB9/PC14-OSC32_IN PA15/PA14-BOOT0
2 R1 JP1 R2 SET 3 18 SWDIO
VCCQ 10k 10k PC15-OSC32_OUT PA13
3 GROVE_SDA 4 17 OLED_SDA
+3.3V VDD/VDDA PA12[PA10]
4 GROVE_SCL 5 16 OLED_SCL
GND VSS/VSSA PA11[PA9] J3
C1 NRST 6 15 DIFF_MODE
NRST PB0/PB1/PB2/PA8 0.96" OLED
A 0.1u 7 14 OUT_B 1 A
2 PA0 PA7 GND
+5V GND OUT_Z 8 13 OUT_A 2
J5

1 PA1 PA6 +3.3V


GND USART2_TX 9 12 DOWN OLED_SCL 3
2 A PA2 PA5
USART2_RX 10 11 UP OLED_SDA 4
J6

1 ~{A} PA3 PA4


2 B
J8

1 ~{B} +3.3V
J4 NRST
2 Z Debug +3.3V SET DOWN UP
1
J9

1 ~{Z} +3.3V
2 SWCLK_CANCEL C2
3
GND 0.1u
4 SWDIO SW5 U9
SW1 SW2 SW3 SW4 +5V XC6206P332 +3.3V
J2 5 NRST
1 USART2_TX GND SWCLK_CANCEL 3 2
GND VI VO
GND GND GND

GND
2 USART2_RX R5 C13
10k C7 C8
3
VBUS 1u 1u 10u

1
4
GND
5 GND
VCCQ
6 GROVE_SDA GND
7 GROVE_SCL
L1 +5V
4.7u D1
SW_5V
B B
J10
1 D3
+5V VIN_buf 5 1
2 A VCCQ IN SW

110k
R3
C4 4 C3
3 ~{A} +5V D2 EN

GND
6 3
4 B VBUS 10u OC FB 10u

R19

R4
15k
68k
5 ~{B}
R8
10k

U3A U2 MT3608L

2
6 Z A 1 2 ENC_SINGLE_A
+5V +5V
7 ~{Z}
+5V 74HC14 GND
8 C12
GND

R18
10k
U3D
0.1u DIFF_MODE 9 8 INV_TTL_DIFF_MODE
R9
10k

U3B
B 3 4 ENC_SINGLE_B U6
J7 74HC14

V_{CC}
USB_C_VCP

16
VBUS GND 74HC4053D,653
+5V 74HC14
A4 11 TTL_DIFF_MODE
VBUS S1
U4 10
S2 U3E
R10
VP

R16
10k

SRV05-4 U3C
5

A5 9 11 10 TTL_DIFF_MODE
CC1 5.1k Z 5 6 ENC_SINGLE_Z S3 VBUS C14
B5 GND 12 14 OUT_A
CC2 5.1k 1Y0 1Z 74HC14 0.1u
R17 74HC14 13

16
1Y1 U7 GND

4
VBUS
A7 D- IO1 IO3

VCC
V3
D- +5V 2 USART2_RX
B7 1 4 +5V 2 15 OUT_B C5 TXD
D- 2Y0 2Z 15 3 USART2_TX
C A6 D+ IO2 IO4 0.1u C6 1 R232 RXD C
D+ 2Y1 0.1u

14
B6 3 6 U8
D+ U3G D+ 5 9
16

GND AM26x32 5 4 OUT_Z UD+ ~{CTS}

V_{EE}
3Y0 3Z GND 6 10

VCC
D-
VDD

GND
A 2 3 6 UD- ~{DSR}
1A 3Y1 ~{E} 11
VN
SHIELD

C11 Y1 ~{RI}
2

A8 3 ENC_DIFF_A 20p
R6
120

SBU1 1Y C9 12MHz 7 12
GND

XI ~{DCD}
8
7
B8 ~{A} 1

3
SBU2 1B 0.1u 2 4 13
B 6 ~{DTR}

GND

GND
2A 8 14

1
5 ENC_DIFF_B GND XO ~{RTS}
A1
S1

R7
120

2Y C10 20p
~{B} 7
2B 74HC14 CH340G/CH340C

1
7
GND TTL_DIFF_MODE 4 GND GND
G GND
GND only for CH340G
INV_TTL_DIFF_MODE 12
~{G}

Z 10 DRA1
3A
11 ENC_DIFF_Z
R13
120

3Y
~{Z} 9
3B
14
+5V 4A
13 DRA2
4Y
GND

GND
15
4B
Sheet: /
D File: encoder_counter.kicad_sch D
U3F
8

13 12 H1 H2 H3 H4
Title: Encoder Counter
GND Size: A4 Date: Rev: 1.3
GND 74HC14 KiCad E.D.A. 8.0.3 Id: 1/1
1 2 3 4 5 6

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