2.

HARDWARE AND SOFTWARE DESIGN ISSUES

Chapter 2: Hardware and Software Design Issues

2.1 Hardware Design Issues
2.1.1 Combinational and Sequential Logic
Combinational and Sequential circuits are the most used type of digital circuits in digital electronics.

a) Combinational Logic Circuit

A combinational circuit is the digital logic circuit in which the output depends on the combination of
inputs at that point of time with total disregard to the past state of the inputs. The digital logic gate
is the building block of combinational circuits. The function implemented by combinational circuit
depends upon the Boolean expressions. The combinational circuit is time-independent. The output it
generates does not depend on any of its previous inputs.
Example: Multiplexer, demultiplexer, encoder, decoder, half-adder, full-adder etc.

Characteristics of a Combinational Circuit

1. Output generation depends upon only the current input.
2. This type of circuit is a time-independent circuit i.e. independent of a clock signal.
3. Its elementary building block is a logic gate.
4. It does not have any memory elements.
5. It does not have any feedback path between input and output.
6. It is used for arithmetic circuits and boolean circuits.
7. It is fast in speed.
8. It is easy to design and also easy to use.

Logic gates

A logic gate is a device that acts as a building block for digital circuits. They perform basic logical
functions that are fundamental to digital circuits. them.

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Logic functions provide ways to combine different digital signals or signals that can only take one of
two possible levels; low level (0) and high level (1) - based on the laws of Boolean algebra. These
laws are applied using logic gates. Logic gates can be used to combine digital signals based on basic
Boolean functions.
Each logic gate has an equivalent electric circuit. However, an electronic gate is very different from
its electrical equivalent. It is much faster, smaller, and consumes less electric energy.

Figure: Equivalent electric circuit of AND, OR and NOT gate

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CMOS :
In the IC design, the basic and most essential component is the transistor. So MOSFET is one kind of
transistor used in many applications. One of the most popular MOSFET technologies available today
is the CMOS technology. Complementary Metal Oxide Semiconductor (CMOS) transistor consists of
P-channel MOS (PMOS) and N-channel MOS (NMOS). Types:
• PMOS:
– When a high voltage is applied to the gate, the
PMOS will not conduct.
– When a low voltage is applied to the gate, the
PMOS will conduct.
• NMOS:
– When a high voltage is applied to the gate, the
NMOS will conduct.
– Similarly, when a low voltage is applied to the
gate, NMOS will not conduct.

CMOS logic gate circuits:

In combinational circuits, the output at any time is a function of the values of input signals at that
time. Thus, these circuits do not have memory and do not empty feedback. Therefore, these are fast
in operation than sequential circuit.
Combinational logic circuits are used in large quantities in a wide range of applications; every digital
system contains large number of combinational logic circuits.

i) The CMOS Inverter or NOT Gate

A NOT gate reverses the input logic state. Figure below shows a NOT gate employing two series-
connected enhancement-type MOSFETS, one n-channel (NMOS) and one p-channel (PMOS).

Figure: NOT gate using CMOS Table:Truth table for NOT gate

• The input is connected to the gate terminal of the two transistors, and the output is
connected to both drain terminals.
• Applying +V (logic 1) to the input (Vi), transistor Q2 is “on,” and transistor Q1 remains “off.”
Under this condition, the output voltage (Vo) is close to 0 V (logic 0).
• Connecting the input to ground (Vi = 0 V), transistor Q2 is “off,” and transistor Q1 is “on.”
Now, the output voltage is close to +V (logic 1).

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ii) The CMOS NAND Gate

Figure below shows a CMOS two-input NAND gate. P-channel transistors Q1 and Q2 are
connected in parallel between +V and the output terminal. N-channel transistors Q3 and Q4 are
connected in series between the output terminal and ground.

Figure: A CMOS two-input NAND gate Table: NAND gate truth table

• With Q3 and Q4 transistors “ON” and Q1 and Q2 transistors “OFF”, the output is a logic 0.
This condition happens when both inputs, A and B, are logic 1, confirming the lowest row in
the above truth table.
• With logic 0 in inputs A and B, Q3 and Q4 transistors are “off,” and Q1 and Q2 transistors are
“on,” producing a logic 1 output. This is consistent with the first row of the truth table.
• When one of the inputs is a logic “1” and the other one is a logic “0”, either Q3 is “off” and
Q2 is “on” or Q4 is “off” and Q1 is “on.” The output in both cases is a logic “1,” validating the
second and the third rows of the truth table.

iii) The CMOS NOR Gate

Figure below shows a CMOS two-input NOR gate. P-channel transistors Q1 and Q2 are
connected in series between +V and the output terminal. N-channel transistors Q3 and Q4 are
connected in parallel between the output and ground.

Figure: A CMOS two-input NOR gate Table: NOR gate truth table

• When both inputs, A and B, are logic 0, Q1 and Q2 are “on,” and Q3 and Q4 are “off,” and
the output is logic 1. This confirms the first row of the truth table above.
• With both inputs logic 1, Q3 and Q4 are “on,” and Q1 and Q2 are “off,” producing a logic 0
output that confirms the last row of the truth table.

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• For the two remaining input combinations, either Q1 is “off” and Q3 is “on” or Q2 is “off”
and is Q4 “on”. In these cases, the output is logic 0 which is consistent with the above truth
table.

Design procedure for a combinational circuit:

1. Problem is stated/ problem description

2. Number of input and output variable is determined.
3. Truth table is generated that defines the relationships between inputs and outputs.
4. Boolean function for each output is simplified using K-map
5. The logic diagram is drawn.

Sample 1:

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Sample 2: Design a 4-bit gray code converter.

Gray code – also known as Cyclic Code, Reflected Binary Code (RBC), Reflected Binary (RB) or Grey
code – is defined as an ordering of the binary number system such that each incremental value can
only differ by one bit. In gray code, while traversing from one step to another step only one bit in the
code group changes. That is to say that two adjacent code numbers differ from each other by only
one bit.
Gray code is the most popular of the unit distance codes, but it is not suitable for arithmetic
operations. Gray code has some applications in analog to digital converters, as well as being used for
error correction in digital communication. Gray code can be difficult to understand initially, but
becomes much easier to understand when looking at the gray code tables below. A table showing
the conversion between binary code to gray code and decimal to gray code is shown below:

Assignment:

1. Design a 2-bit comparator circuit that have one single output “less than” using the approach
of combinational design technique.
2. Design a 3x8 decoder. Start from the truth table, use K-map to minimize the logic gates and
draw the final circuit.

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RT Level Combinational Components

Although we can design all combinational circuits, large circuits would be very complex to design.
For e.g., a circuit with 16 inputs would have 216 or 64 K rows in its truth table. To reduce such
complexity, combinational components (more powerful than logic gates often called RT level
components are used. Some of these Register-Transfer (RT) level combinational components are:
• Multiplexer
• Decoder
• Adder
• Comparator
• ALU
• Shifter

a) Multiplexer
A multiplexer is also called selector. It means many to one. It is a combinational circuit that
selects single information from multiple inputs, one at a time. Selection of single information is
controlled by the selection or control lines. For ‘n’ inputs, there are ‘m’ selection lines and a
single output where 2m=n. Figure below show the block diagram, truth table and logic circuits for
a 4x1 MUX.
Application:
• As a building blocks in the CPU
• Used in the telecommunication at the transmitter

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b) Decoder
Decoder is a combinational circuit that converts binary information’s from ‘n’ input to a
maximum of 2n unique output lines. It decodes binary data. Only one output is present at
a time.
For a 3 x 8 decoder, it has three inputs and eight output lines. If the input is 000, the n the
output O0 would be 1 and others remaining should be 0.
When enable is 0, all outputs are 0. If enable is 1, the decoder functions as intended.

c) Adder
An adder is a combinational logic circuit that are used for addition of numbers. Adders are
classified into two types: half adder and Full Adder.

i) Half Adder:
The half adder circuit has two inputs: A and B, which add two input digits and generates a
carry and a sum.

Block Diagram Truth Table Logic Circuit

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ii) Full Adder

The full adder circuit has three inputs: A and C, which add three input numbers and
generates a carry and sum.

Block Diagram Truth Table Logic Circuit

d) Comparator
A comparator is a combinational circuit that takes two N-bit binary inputs and compare them.
Only one output among x=y, x>y and x<y is activated.

Figure below shows the block diagram, truth table and logic diagram of a 1-bit magnitude
comparator.

Block Diagram Truth Table Logic Circuit

e) ALU
An Arithmetic Logic Unit (ALU) can perform a variety of arithmetic and logic functions on its N-
bits inputs A and B. The select lines S choose which function to be performed. For 2n functions,
there are N select lines. The binary value of S defines which function to be selected. Some
common functions are: addition, subtraction, AND , OR and so on.

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f) Shifter
Another RT level component is a shifter. An n-bit input ‘A’ can be shifted left or right, and then
output to an ‘O’.
For eg. A 4-bit shifter with an input 1010 will be 0101 when shifting right one position.
Shifters usually come with an additional input indicating what value should be shifted in and an
additional output indicating the value of the bit being shifted out.

b) Sequential Logic Circuit

A sequential circuit is the digital logic circuit in which the output depends on clock cycle and present
inputs as well as past inputs. The combinational circuit is time-dependent. The output it generates
depend on any of its previous inputs.

Example: Flip-flops like SR flip-flop, JK flip-flop, T flip-flop, registers, counters, etc.

Characteristics of a Sequential Circuit

1. Output generation depends upon the previous output and current input signals.
2. It depends upon its previous feedback or previous output. It uses the current state (previous
output) as control inputs for the next operations.
3. This type of circuit depends upon time instant i.e. depends upon clock cycles.
4. This can be two types- Synchronous circuit (uses clock pulse) and Asynchronous circuit (does
not use clock pulse).
5. Its basic building block is a flip-flop (binary storage device).
6. It has memory elements.
7. It is mostly used to build memory devices.
8. It is slow in speed.
9. Its design and use are complex in comparison with combinational circuits.

Flipflops

A flip-flop is a sequential circuit which is popularly known as a basic digital memory circuit. It stores 1
bit; therefore, it is called as 1-bit memory cell. It has two stable states: logic 1 and logic 0, i.e. two
outputs, one normal (Q) and another inverted complement (𝑄̅ ). It can flip from one state to another
and then flip back, so it is called flip flop. It is also known as bitable multivibrator, latch or toggle.
It is the basic storage element in sequential logic and fundamental building blocks of digital
electronic systems. They can be used to keep a record of the value of a variable. Flip-flop is also used
to control the functionality of a circuit.
• The outputs Q and 𝑄̅ are always complementary to each other.
• If Q= 0, 𝑄̅ = 1 , and vice-versa; Q =𝑄̅ = 0 or 1 is invalid
• If Q=1, 𝑄̅ = 0 → set
• If Q=0, 𝑄̅ = 1→ Reset
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a) Basic RS Flip Flop

• At starting point. Assume that the set input is 1 and the reset input is 0.
• ̅ must be 0, which puts both inputs of gate 1 at 0, so
Since gate 2 has an input 1, its output 𝑸
that output Q is 1.
• When the set input is returned to 0, the outputs remain the same, because output Q
remains a 1, leaving one input of gate 2 at 1.
• This causes output 𝑸̅ to stay at 0, which leaves both inputs of gate number 1 at 0, so that
̅
output Q to 0 and 𝑄 to 1. When the reset input returns to 0, the outputs do not change.
• When a 1 is applied to both the set and the reset inputs, both Q and 𝑄̅ outputs go to 0. This
condition violates the fact that outputs Q and 𝑄̅ are the complements of each other, hence,
should be avoided.

b) SR Flip Flop

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c) D-Flip Flop

d) JK Flip flop

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e) T-Flip flop

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Flip flop excitation table

Refer: https://www.youtube.com/watch?v=xjHGjxTNW9A

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RT Level Sequential Components

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Differences between Combinational and Sequential logic

Basis of Combinational circuit Sequential Circuit

Comparison

Definition 1. These are the types of circuits 1. These are the types of circuits
that give output depending only that give output depending upon
on present input. present input and previous output.

Feedback 2. It does not use any feedback. 2. It has a feedback path from output to
input. This feedback path is used to
get previous output and provide
present output.

Time 3. It is not time-dependent. 3. It uses clock pulse i.e. it is time-

dependency dependent.

Performance 4. Its performance is fast in speed 4. Its performance is slow in speed

compared to sequential circuits compared to combinational circuits
because it only uses present because it uses present input as well
input to give present output. as previous output to give output.

Complexity 5. It is easy to build and easy to use 5. It is complex to build and also
and handle. complex to use compared to
combinational circuits.

Elementary 6. Its elementary building blocks are 6. Its elementary building blocks are flip-
building logic gates i.e. AND, OR, NOT, flops i.e. memory units.
units NAND, NOR.

Memory 7. It does not have any memory 7. It has flip-flops as memory elements,
elements elements, so it cannot store data. so it can store the previous output in
it.

Operations 8. It is used for arithmetic and 8. It is used as a memory device to store

boolean operations. data in digital circuits.

Example 9. Multiplexer, De- 9. Flip-flops, Registers, Counters, etc.

multiplexer, Encoder, Decoder, that are used to store data.
Half-adder, Full-adder, etc. that
are used for arithmetic operation
and boolean operation.

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Design of Synchronous Sequential Circuit

Sequential Machine Design Steps:

1. Select the model to be implemented: either Moore or Mealy

2. Obtain the state diagram from the statement of the problem.
3. Obtain the next state table from the given information.
4. Reduce the number of states using state reduction method if necessary. Assign binary codes
to the states.
5. Choose the type of flip flop to be used. Determine the number of flip flop to be used and
derive the excitation table and synthesis table.
6. Derive the simplified flip-flop input equations from the state table using K-map.
7. Draw the logic diagram with the flip-flops and combinational gates according to those
equations.

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1. Design a 3-bit gray code counter using JK flip flop.

Step 1: State Diagram

State Diagram for a 3-bit Gray code counter:

Step 2: Next-State Table

Next state table for a 3-bit Gray code counter

Step 3: Flip-Flop Transition Table

Transition table for a J-K Flip-Flop

Step 4: Karnaugh Maps

The following diagram shows the steps to create separate next states of separate J and K from the
current states of J and K.

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Karnaugh maps for present-state J and K inputs for the 3-bit Gray code counter.

Step 5: Logic Expressions for Flip-flop Inputs

The next-state J and K outputs for a 3-bit Gray code counter.

J0 = Q2Q1 + 𝑸̅2 𝑸
̅1
K0 = ̅ ̅
Q2 𝑸1 + 𝑸2 Q1
J1 = ̅ 2 Q0
𝑸
K1 = Q2 Q0
J2 = Q1 𝑸̅0
K2 = ̅
𝑸1 𝑸̅0

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Step 6: Counter Implementation

The hardware diagram of the 3-bit Gray code counter:

Note: There is a slight

mistake in the ckt.
diagram for input J0 ,
please find and make
correction.

Assignment:
Design a 3-bit Grey code counter using D- Flipflop.

2. Design a sequential detector that receives binary data stream at its input ‘x’ and when a
combination ‘1101’ arrives ar the input, its output ‘y’ is set high.

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Note: There is a slight mistake in the ckt. diagram for D1, please find and make correction.

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Assignment:
1. Design a 2-bit comparator circuit that have one single output “less than” using the approach
of combinational design technique.
2. Design a 3x8 decoder. Start from the truth table, use k-map to minimize the logic gates and
draw the final circuit.
3. Construct a clock divider. Show down your pre-existing clock so that you output a 1 for every
four clock cycles.
4. Design a soda controller machine given that a soda costs 75 cents and your machine accepts
quarters only. Draw the black box view, come up with state diagram, and draw the final
circuit.
5. Design a sequence detector that produces a true output whenever it detects the sequence
010 at its input.
6. Design an overlapping sequence detector for the sequence 1010. [2019 Fall]
7. Design a sequential circuit to implement 2-bit counter with an input that controls up
(increase value) or down (decrease value) count. [2019 Fall]
8. Design a 3-bit counter that counts the following sequence 1, 2, 4, 5, 7, 1, 2, etc. This counter
has an output “odd” whose value is 1 when the current count value is odd. Use the
sequential design technique of the chapter. Start from a state diagram, draw he state table,
minimize the logic and draw the final circuit.

Refer teaching slides that have been provided to you.

2.1.2 Custom Single-purpose Processor Design

A basic processor is composed from a controller and a datapath as illustrated in figure below.

Fig: A Basic processor a) controller and datapath b) inside view of controller and datapath

• The data path stores and manipulates the system data. Examples of data in embedded
system includes binary numbers representing external conditions like temperature or speed,
the character to be displayed on the screen or digitized photographic image to be stored and
compressed.
• The data path consists register unit, functional unit, and connection unit like wires and
multiplexer.
• The data path can be configured to read the data from register, fed that data into the
functional unit configured to carry the operations like add, subtract, shift etc. and stores the
result back to the designated register.
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• A controller caries out the configuration of data path. It sets the data path control signals
like load input to register, select inputs for selecting the register, operation selection for
functional unit and connection unit to obtain the desired configuration at particular instant
of time.
• It monitors the external control input as well as data path control outputs known as status
signal, coming from the functional units and it sets the external control output as well.
• The combinational or sequential logic can be applied to design controller and data path.

Steps to Design Single Custom Processor Steps:

1. Draw a black box that shows the abstract view of the implementation logic.
2. Derive the algorithms to implement the functionality of system.
3. Derive the state diagram to implement the operational logic in terms of control flow,
dataflow and applicable logic using different statements.
4. Design the data path, functional unit as well as controller to implement the complex logic
specified in step 2.

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Sample:

Design a custom single processor to compute factorial of a number.

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2.1.3 Optimizing Custom single-purpose Processor

Optimization is the technique of improving the design metrics so as to get the best possible values of
various design metrics. The optimization opportunities in custom SPP are as follows:-

1. Optimization of original program:

The algorithms are analyzed in terms of time complexity and space complexity, and hence we try to
develop more efficient alternative algorithms. It involves decreasing of number of computations and
size of variables if possible.
E.g. Optimized GCD Program

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int x,y,r;
while(1)
{
while(!go_i);
if(x_i >=y_i)
{
x=x_i ;
y=y_i ;
}
else
{
x=y_i;
y=x_i ;
}
while(y!=0)
{
x=x%y;
x=y;
y=x;
}
d_o = x ;
}

2. Optimizing FSMD
The states that can be merged to reduce the number of states. The design must be aware if whether
output timing may or may not be modified
E.g. Optimized GCD FSMD

Draw FSMD from the above optimized algorithm of GCD.

3. Optimizing Datapath
Many functional operations can share a single functional unit if those operations occur in different
stages. E.g. In GCD Datapath, single subtractor can be used and selection can be done using
multiplexor.

4. Optimizing FSM
FSM can be optimized using state encoding and state minimization.
State encoding is the task of assigning a unique log2(n) bits to encode n states.
State minimization is the task of merging equivalent states into a single state.

2.2 Software Design Issues

General Purpose Processor (Software) Introduction:

General Purpose Processor (GPP) is a processor designed for a variety of computational tasks. There
are several benefits that a designer choosing a GPP may achieve. They are:
• Low unit cost due to spread of NRE cost over large number of units.
• System designer may incur low NRE cost since the designer need only write the software.
• Time to prototype and Time to marker will be short, since the processor IC can be purchased
and then programmed in the designer’s own lab.
• Greater flexibility since the designer can rewrite the software in a straight forward manner.

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2.2.1 Basic Architecture

The general-purpose processor sometimes called as central

processing unit (CPU) or a microprocessor. It consists of a
datapath and a control unit, tightly coupled with memory as
shown in figure. The general-purpose basic architecture
consists of:
• Datapath
• Control unit
• Memory

i) Datapath

The data path consists the circuitry to transfer the data from one place to another and storing the
temporary data. The datapath contains the ALU capable of transferring the data from different
operation like additions, subtraction, bitwise OR, AND etc. ALU also generates the status signals
often stored in status register. These status bit conditions are known as flags. The flags may be zero,
sign carry overflow etc. It also contains register and stores the data temporarily during ALU
operation.
The temporary data includes:
• Data read from memory but not yet send to ALU.
• Result from ALU operation that is used for next operation or going to write on memory.

The capacity of processor measured by bandwidth of datapath i.e. data carrying capacity. The n-bit
size processor consists: -
• N bit registers set
• N bit internal and external system bus
• N bit ALU
The processor size may be 4, 8, 16, 32 or 64 bit.

ii) Control Unit

It consists a circuitry that generates the control signal to read the instruction stored in memory, its
execution and transferring the data from datapath, storing the result on memory and IO operation.
A register called as program counter (PC) that is use to sequence the program i.e. it points the
address of next instruction that is going to fetch and execute. Another register called as instruction
register (IR) is used to hold the instruction read from memory. The register called as Address
Register (AR) is used to store the memory address during memory read/write operation. The control
unit has a controller, consisting of a status register plus next state and control logic. It controls the
data flow on datapath and such flow includes:
• Inputting the two-particular register for ALU operation.
• Storing the ALU results in particular register.
• Moving the data between memory and register.
An m bit sized address memory consists the address space of 2m and controller goes through the
following operation to execute an instruction.
• Fetching the instruction from memory.
• Decode the instruction.
• Fetch the operand from memory
• Perform the operation on memory.
• Store the result.

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iii) Memory
Registers are used as the short-term storage whereas memory is used as the mid-term and long –
term storage. Memory be classified as: Program Memory and Data memory.
• The program memory is used to store the sequence of instruction called as program which is
used to achieve a given functionality.
• Data memory is used to store the data information and represents the values of input,
output, and transformed by program.
We can store the data and program together or separately. The memory architecture follow one of
two models: Princeton Architecture or Harvard Architecture.
• The Princeton architecture shares the common memory space to store the data and
program and requires one to one connection with hardware.
• The Harvard architecture uses the separate memory space to store program as well as data
and requires different connection. The microcontroller 8051/52 follow this model.

Fig: a) Harvard architecture (b), Princeton Architecture, (c) Cache Memory

To reduce the time needed to access (read or write) memory, a local copy of a portion of memory
may be kept in a small but especially fast memory called cache.

2.2.2 GPP Operation

The instruction be executed in microprocessor by taking following steps:

• Fetch Instruction (FI): It is a task that reads the instruction from memory pointed by PC and
loaded into the instruction register.
• Decode Instruction (DI): In this phase, an instruction be decoded to separate the operand
reference as well as operation code to represent the particular operation as ADD, MOV,
AND, SUB etc.
• Fetch Operand (FO): In this stage, the operand be read from the memory represented by the
effective address (EA). EA calculation is needed for indirect address.
• Execute Instruction (EI): In this phase, the instruction be executed in accordance with its
opcode an operand and generates the result.
• Store Result (SR): The result is stored on the particular destination that may be register or
memory.

Program execution performance can be improved by mainly three ways:

1. Faster clock (but there is always a physical limit of clock speed)
2. Pipelining
3. Multiple ALUs to support more than one instruction stream.

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Pipeline for Instruction Execution:

The pipeline is a common process to increase the instruction throughput of a microprocessor. Figure
below illustrates instruction pipelining.

Figure: Instruction Pipelining

Superscalar and VLIW Architecture:

We can use multiple ALUs to further speed up a processor.
• A superscalar microprocessor can execute two or more scalar operations in parallel,
requiring two or more ALUs.
• A VLIW (Very long instruction word) architecture is a type of static superscalar architecture
that encodes several (four or more) operations in a single machine instruction. A set of
instructions is bundled together into a VLIW packet which may be executed together. The
execution of the next packet will not start until all the instructions in the current packet have
finished executing.

2.2.3 Programmer’s View

A programmer writes the program instruction carryout the desired functionality on GPP. For this
purpose, programmer doesn’t need to know about the detailed structure of the processor where as
he/she need to know how instruction be executed. He/she needs to deal with an architectural
abstraction.
The level of abstraction depends upon the level of programming: Assembly level, Structured level
and Machine level.

Instruction set:
An assembly language programmer must know the processor’s instruction set. The instruction set
describes the bit configurations allowed in the Instruction Register (IR). An instruction typically has
two parts: opcode and operand. The opcode identifies the type of operation to be performed and
operand specify the source or destination of data.
Eg: MOV A, B

Addressing modes:
For a given instruction set architecture, addressing mode defines how machine language instructions
identify the operand to each instruction. Simply, it is the way of specifying operand.
The various addressing modes are: Immediate, Direct, Indirect, Register Direct, Register Indirect and
so on.

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Figure: Addressing modes

Program and data memory space:

An ES programmer must be aware of the size of the available program and data memory space. He
must be aware of on-chip program and data memory capacity and must not exceed these limits.

Registers:
Assembly level programmers must know how many registers are available for general purpose data
storage. They must be familiar with other registers having special functions. For eg: a base register, it
permits programmer to use a data transfer instruction where processor adds and operand field to
the base register to obtain an actual memory address.

I/O:
An ES programmer should be aware of the processors input and output functionality.

Interrupts:
Programmers should be aware of types of interrupts supported by the processor and must write ISRs
when necessary. The AL programmer places each ISR at a specific address in program memory.

Operating System:
Programmers should have well knowledge of the OS which he is going to use. An Operating System
(OS) is an interface between a computer user and computer hardware. An operating system is a
software which performs all the basic tasks like file management, memory management, process
management, handling input and output, and controlling peripheral devices such as disk drives and
printers. An operating system is a program that acts as an interface between the user and the
computer hardware and controls the execution of all kinds of programs.

2.2.4 Development Environment

The general design flow for programming applications that run on a desktop starts with writing our
source code. Possibly organized in a number of files for modularity, using an editor.
Then we compile or assemble the code in each file, using a compiler or assembler, into
corresponding binary files.
Next using a linker, we combine these binary files into a final executable. These tasks, collectively,
can be considered as the implementation phase.
Next, we test our program by running the executable file under the command of a debugger.
Sometimes we may use a profiler to pinpoint the performance bottlenecks of our program, during

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this phase, i.e. we discover errors or performance bottlenecks, we return to the implementation
phase, make improvements, and repeat the process.
Typically, all of these tools have been combined into a single Integrated Development Environment
(IDE), which greatly simplifies the design process.

Figure: Software Design Process: (a) Desktop, (b) Embedded

2.2.5 Application Specific Instruction-set Processors

Today’s ES (e.g. HDTV) requires high computing power and very specific functionality. GPP cannot
deal efficiently with performance, power, cost or size demands in this case. CSPP are inflexible and
too prohibitive. The solution is to use instruction set processor which provides intermediate solution
between GPP and SPP because they are designed specifically for an application. ASIPs are the
instruction set processors that can be programmed by writing software, resulting in short time-to-
market and good flexibility while other constraints (performance) may be efficiently satisfied.
ASIPs tend to come in three major varieties:

a) Microcontroller
b) Digital Signal Processor (DSP)
c) Less-General ASIP environments

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a) Microcontroller:

b) Digital Signal Processor:

c) Less-General ASIP environments:

2.2.6 Selecting a Microprocessor

The choice of a processor depends on technical and non-technical aspects.

From a technical perspective, one must choose a processor that can achieve the desired speed
within certain power, size and cost constraints. Non-technical aspects may include prior expertise
with a processor and its development environment, specially licensing arrangements, and so on.

The selection basis is the requirement, what the processor needs to do. A processor may be selected
on the basis of following parameters.
1. Speed: How fast a processor can compute has always been a point of high interest for
designers and developers. There is always demand for fast processors. But good practice is
to use a processor required by application. A data logging application that records

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temperature in every 5 minutes might not require a faster processor but a X-ray machine in
the emergency ward should have faster one. MIPS (Millions instruction set second) is also
used to measure Speed.
2. Instruction Set: The instruction set defines what a processor can do. Based on task to be
performed, an additional set of instruction or totally different instruction set may be
required. In robotic system the processor for driving a motor and analyzing an environment
are required to perform different task, instruction set may be different for them.
3. Bit/ Word Length: It is a size of data the processor can handled, the length of register
around processor. If processor needs to process floating point data, the word length that
works for integer type data is no sufficient. A narrower option may work but takes more
time.
4. Power Consumption: Power consumption may not a deciding factor for fixed system but
when it comes to a portable handheld device, it becomes a crucial point. Both the standby
and peak power consumption of processor are to be considered. For example, the low
power consumed by mobile phone in standby or sleep and active mode should low.
5. Prior Experience: While working in a project, a designer would choose a processor with
which he has experience. The availability of development and libraries for the SW for a
processor contributes to the performance.
6. Size: The actual physical size of the processor may impact the design when the trend is going
for slim smart devices. Everything, including processor is required to be small.
7. Cost: The price of the processor is the ultimate selection factor. The available project budget
may not accommodate expensive processor then designer selects the low-cost processor.

Other factors may be type/ version, no of register etc., may also be used as selection criteria.

2.2.7 General-purpose Processor Design

The general-purpose processor design follows the states as like in singe processor design as:

1. Create a FSMD to describe a behavior of processor. I.e. design instruction set.

2. Built the data path to carry the data flow between different functional units.
3. Rewrite the FSMD to FSM
4. Design the FSM controller

Example: Design a General Purpose Processor (GPP) to create the instruction given
below:

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Figure: A Simple GPP FSMD

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Figure: Architecture of a GPP: controller and Datapath

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Exam questions:

1. Design a 3-bit gray code counter using J-K flip-flop. [2021 Fall]
2. Define target and development processor. Explain any three ways of testing the program
intended for embedded system. [2021 Fall]
3. Explain the optimization of single purpose processor in detail. [2021 Fall]
4. State the differences between combinational and sequential circuits? Describe sequential circuit
design process with a suitable example. [2019 Spring]
5. Design custom single purpose processor to calculate LCM between two integers. [2019 Spring]
6. Define Datapath and control units with it sub operations. . [2019 Spring]
7. Define Combinational and sequential circuit. Design a NOR gate using CMOS transistor. [2020
Fall]
8. Define optimization. Explain the different optimization opportunities. [2020 Fall
9. What are the key factors a programmer needs to consider when choosing a General-purpose
controller? [2020 Fall]
10. Design an overlapping sequence detector for the sequence 1010. [2019 Fall]
11. Design a sequential circuit to implement 2-bit counter with an input that controls up (increase
value) or down (decrease value) count. [2019 Fall]
12. Design a synchronous sequential machine that produces output 1 when input is 1101 using T-
flip flop. [2018 Spring]
13. Design a custom single-purpose processor that generates Fibonacci series up to n places. Start
with a function computing the desired result, translate it into a state diagram, and sketch a
probable Datapath. [2018 Spring]
14. Discuss basic architecture of general-purpose processor with necessary diagram. [2018 Spring]
15. Design a circuit to implement 2-bit gray counter. [2018 Fall]
16. Suppose you are appointed as an officer in a criminal investigation department, are provided a
lot of phone record for analysis. How you will solve this problem and which processor is suitable
for this analysis purpose? [2018 Fall]
17. Explain the programmer view in the embedded system. [2018 Fall]
18. What is optimization? Explain optimization of single purpose processor in detail. [2017 spring]
19. Design a processor that calculates the GCD of two numbers. Show the design of Datapath only
and construct the diagram of controller. [2017 spring]
20. How does a programmer view a microprocessor based embedded system? What are his/her
concern? [2017 spring, 2017 Fall, 2016 Spring]]
21. How can you design General purpose processor? Explain with necessary steps and diagram.
[2017 Fall]
22. Design a synchronous sequential machine that produces output 1 when input sequence is 1011
using JK flip flop. [2016 Fall]
23. Design a custom single-purpose processor to calculate GCD between two integers. [2016 Fall]
24. Explain General purpose processor design with a suitable diagram. [2016 Fall]
25. Explain with an example how to optimize custom single purpose processors. [2016 Spring]
26. Draw the combinational logic design for three inputs a, b and c, and two outputs y & z. the
output y is such that y is 1 if a is 1 or b & c is 1 and z is 1 if b or c is 1 but not both. [2016 Spring]

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27. Why decoders and counters are respectively called combinational and sequential logic circuits?
Write the design steps for both combinational and sequential logic circuits with conceptual block
diagrams. [2015 Spring]
28. Design a 3-bit counter that counts the following sequence 1,2, 4, 5, 7, 1, 2, etc. This counter ha
an output “odd” whose value is 1 when the current count value is odd. Use the sequential
design technique of the chapter. Start from a state diagram, draw he state table, minimize the
logic and draw the final circuit. [2015 Spring]
29. Explain with an example how to optimize custom single purpose processors. [2015 Fall]
30. Explain in brief about combinational and sequential logic. [2015 Fall]
31. Define Target and Development processor. Explain three ways to test the program intended for
Embedded system. [2015 Fall]

***

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