School of Computing

Department of Computer Science & Engineering

10211CS201-DIGITAL ELECTRONICS
Category : Program Core
UNIT-II
Course Handling Faculty :
Dr.P.Rajalakshmi
27-08-2024
Asst. Professor 1
 • Logic circuits for digital systems may be combinational or
sequential.
• A combinational circuit consists of input variables, logic
gates, and output variables.

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 Half Adder
• A combinational circuit that performs the addition of two bits is C: Carry
called a half adder.
• The truth table for the half adder is y y y
S: Sum x 0 1
C: Carry x y C S
0 0
0 0 0 0 x 0 0 1
xy
0 1 0 1 x 1 0
2
1
3

1 0 0 1 S: Sum
y y y
x 1
1 1 1 0 0
0 1
x 0 0 1
xy
S = x’y + xy’
x 1 1
2
0
3
27-08-2024 C = xy
3 xy
Implementation of Half-Adder

x’y + xy’ = s

xy = c

S = x’y + xy’ ➔ x⊕ y
C = xy

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 Full Adder
• A combinational circuit that performs the addition of three bits is
called a full adder.
• The truth table for the full adder is yz yz
yz yz
C yz
x y S x 01 10
00 11
m0 m1 m3 m2
x 0 0 1 3 2

S: Sum x 1 m4
4
m5
5
m7
7
m6
6
C: Carry 5
yz
x 00 yz 01 y z 11 yz 10 yz
m0 m1 m3 m2
0
x 0 1 3 2

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x 1 m4
4
m5
5
m7
7
m6
6
Full-Adder
• One that performs the addition of three bits(two
significant bits and a previous carry) is a full adder.

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Simplified Expressions

S = x’y’z + x’yz’ + xy’z’ + xyz

C = xy + xz + yz

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Full Adder implementation
• Full-adder can also implemented with two half adders and
one OR gate (Carry Look-Ahead adder).
S = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
C = z(xy’ + x’y) + xy = xy’z + x’yz + xy

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Magnitude comparator
• The equality relation of each pair
of bits can be expressed logically
with an exclusive-NOR function as:

A = A3A2A1A0 ; B = B3B2B1B0

xi=AiBi+Ai’Bi’ for i = 0, 1, 2, 3

(A = B) = x3x2x1x0

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Magnitude comparator
• We inspect the relative magnitudes
of pairs of MSB. If equal, we
compare the next lower significant
pair of digits until a pair of unequal
digits is reached.

• If the corresponding digit of A is 1

and that of B is 0, we conclude that
A>B.

(A>B)=
A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’0
(A<B)=
A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B0
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Decoders
• The decoder is called n-to-m-line decoder, where m≤2n .

• the decoder is also used in conjunction with other code converters

such as a BCD-to-seven_segment decoder.

• 3-to-8 line decoder: For each possible input combination, there are
seven outputs that are equal to 0 and only one that is equal to 1.

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Implementation and truth table

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Decoder with enable input
• Some decoders are constructed with NAND gates, it becomes more
economical to generate the decoder minterms in their
complemented form.
• As indicated by the truth table , only one output can be equal to 0
at any given time, all other outputs are equal to 1.

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Demultiplexer
• A decoder with an enable input is referred to as a
decoder/demultiplexer.
• The truth table of demultiplexer is the same with decoder.
A B

D0

Demultiplexer D1
E
D2
D3

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Encoders
• An encoder is the inverse operation of a decoder.
• We can derive the Boolean functions by table
z = D 1 + D 3 + D 5 + D7
y = D 2 + D3 + D 6 + D 7
x = D 4 + D5 + D 6 + D 7

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Priority encoder
• If two inputs are active simultaneously, the output produces an undefined
combination. We can establish an input priority to ensure that only one input is
encoded.
• Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is
generated when all the inputs are 0; the output is the same as when D0 is equal
to 1.
• The discrepancy tables can resolve aforesaid condition by providing one more
output to indicate that at least one input is equal to 1.

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Priority encoder
V=0→no valid inputs
V=1→valid inputs

X’s in output columns represent

don’t-care conditions
X’s in the input columns are
useful for representing a truth
table in condensed form.
Instead of listing all 16
minterms of four variables.

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4-input priority encoder
0
• Implementation of 0
table 0
0
x = D2 + D3
y = D3 + D1D’2
V = D 0 + D 1 + D2 + D 3

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Multiplexers
S = 0, Y = I0 Truth Table→ S Y Y = S’I0 + SI1
S = 1, Y = I1 0 I0
1 I1

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4-to-1 Line Multiplexer

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Boolean function implementation
• A more efficient method for implementing a Boolean function of n
variables with a multiplexer that has n-1 selection inputs.
F(x, y, z) = (1,2,6,7)

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4-input function with a multiplexer
F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

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Code Conversion
Code-Conversion example, first, we can list the relation of
the BCD and Excess-3 codes in the truth table.

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Karnaugh map
For each symbol of the Excess-3 code, we use 1’s to draw
the map for simplifying Boolean function.

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Circuit implementation
z = D’; y = CD + C’D’ = CD + (C + D)’
x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’
w = A + BC + BD = A + B(C + D)

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Describing a Design
In VHDL an entity is used to describe a hardware module. An entity can be
described using,

• Entity declaration
• Architecture
• Configuration
• Package declaration
• Package body

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VHDL Introduction
• VHDL stands for very high-speed integrated circuit hardware description
language.

• It is a programming language used to model a digital system by dataflow,

behavioral and structural style of modeling.

• This language was first introduced in 1981 for the department of Defense
(DoD) under the VHSIC program.

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Entity Declaration
Syntax −
entity entity_name is
Port declaration;
end entity_name;

An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The
direction will be input, output or inout.

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Architecture
• Architecture − Architecture can be described using structural, dataflow,
behavioral or mixed style.

Syntax −

architecture architecture_name of entity_name

architecture_declarative_part;
begin
Statements;
end architecture_name;

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Data Flow Modeling

• In this modeling style, the flow of data through the entity is expressed using
concurrent (parallel) signal.

• The concurrent statements in VHDL are WHEN and GENERATE.

In concurrent code, the following can be used −

Operators
The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
The GENERATE statement;
The BLOCK statement

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Behavioral Modeling
• In this modeling style, the behavior of an entity as set of statements is executed
sequentially in the specified order.

• Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are

sequential.

• PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code

that are executed sequentially.

• The behavior statements are IF, WAIT, CASE, and LOOP

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Structural Modelling

• In this modeling, an entity is described as a set of interconnected

components.
• A component instantiation statement is a concurrent statement.
Therefore, the order of these statements is not important.
• The structural style of modeling describes only an interconnection of
components (viewed as black boxes), without implying any behavior
of the components themselves nor of the entity that they collectively
represent.

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Logic Operation – AND GATE
• VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity and1 is
port(x,y:in bit ; z:out bit);
end and1;

architecture virat of and1 is

begin
z<=x and y;
end virat;
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Logic Operation – OR Gate

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity or1 is
port(x,y:in bit ; z:out bit);
end or1;

architecture virat of or1 is

begin
z<=x or y;
end virat;

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Logic Operation – NOT Gate
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity not1 is
port(x:in bit ; y:out bit);
end not1;

architecture virat of not1 is

begin
y<=not x;
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end virat;
 Examples of VHDL Code
• Arithmetic Circuits in VHDL:
– Consider the half addercircuit

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 • Using Structural Architecture:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_AIS
PORT (A, B: IN STD_LOGIC; S, C: OUT STD_LOGIC);
END H_A;

ARCHITECTURE HA_STR OF H_AIS

COMPONENT XOR2
PORT (X, Y: IN STD_LOGIC; Z: OUT STD_LOGIC); END
COMPONENT;
COMPONENT AND2
PORT (P, Q: IN STD_LOGIC; R: OUT STD_LOGIC); END
COMPONENT;

BEGIN
X1: XOR2 PORT MAP (A,B,S);
X2: AND2 PORT MAP (A,B,C);
END HA_STR;

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 • Using Data Flow Architecture:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_A IS
PORT (A, B: IN STD_LOGIC; S, C: OUT
STD_LOGIC); END H_A;

ARCHITECTURE HA_DF OF H_A IS

BEGIN
S <= A XOR B AFTER
10ns; C <= AAND B
AFTER 5ns;
END HA_DF;

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• Using Behavioural Modeling
ENTITY H_A IS PORT(A, B: IN BIT;
S, C: OUT BIT); END H_A;

ARCHITECTUER BEHAVE_HA OF H_AIS

BEGIN
PROSESS (A, B) BEGIN
IF A=‘0’AND B=‘0’ THEN
S <= ‘0’ AFTER 10ns; C <= ‘0’ AFTER
10ns;
ELSEIF A=‘0’AND B=‘1’THEN
S <= ‘1’ AFTER 10ns;
C <= ‘0’ AFTER 10ns; ELSEIF A=‘1’
AND B=‘0’THEN
S <= ‘1’ AFTER 10ns; C <= ‘0’ AFTER
10ns;
ELSEIF A=‘1’AND B=‘1’ THEN
S <= ‘0’ AFTER 10ns;
C <= ‘1’ AFTER10ns;

ENDIF;
END PROCESS; END BEHAVE_HA;

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• Using Data Flow Architecture with selected signal
assignment:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_AIS
PORT (A, B: IN STD_LOGIC; S, C: OUT STD_LOGIC); END H_A;

ARCHITECTURE HA_DFSS OF H_A IS

BEGIN
HA_X <= A & B; HA_Y <= C & S;
WITH HA_X SELECT
HA_Y <= “00” WHEN “00”,
“01” WHEN “01”,
“01” WHEN “10”,
“10” WHEN “11”;
END HA_DFSS;

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 Examples of VHDL Code
• Arithmetic Circuits in VHDL:
– Consider the half subtractorcircuit

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• Using Structural Architecture:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_S IS
PORT (A, B: IN STD_LOGIC; DIFF, BORROW: OUT STD_LOGIC);
END H_S;

ARCHITECTURE HS_STR OF H_S IS COMPONENT

XOR2
PORT (X, Y: IN STD_LOGIC; Z: OUT STD_LOGIC); END
COMPONENT;
COMPONENT AND2
PORT (P, Q: IN STD_LOGIC; R: OUT STD_LOGIC);
END COMPONENT; COMPONENT
NOT2
PORT (M: IN STD_LOGIC; N: OUT STD_LOGIC); END
COMPONENT;

SIGNAL BB: BIT;

BEGIN
X1: XOR2 PORT MAP (A,B,DIFF); X2: NOT2 PORT
MAP (A,AA);
X3: AND2 PORT MAP (AA,B,BORROW); END HS_STR;

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 • Using Data Flow Architecture:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_S IS
PORT (A, B: IN STD_LOGIC; DIFF, BORROW: OUT STD_LOGIC); END
H_S;

ARCHITECTURE HS_DF OF H_S IS

BEGIN
DIFF <= A XOR B AFTER 10ns;
BORROW <= ((NOT A) AND B) AFTER 5ns; END
HS_DF;

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• Using Behavioural Modeling

ENTITY H_S IS PORT(A, B: IN BIT;

DIFF, BORROW: OUT BIT); END H_S;

ARCHITECTUER BEHAVE_HS OF H_S IS

BEGIN
PROSESS (A, B) BEGIN
IF A=‘0’AND B=‘0’ THEN
DIFF <= ‘0’ AFTER 10ns; BORROW <= ‘0’
AFTER 10ns;
ELSEIF A=‘0’AND B=‘1’THEN
DIFF <= ‘1’ AFTER 10ns;
BORROW <= ‘1’ AFTER 10ns; ELSEIF A=‘1’
AND B=‘0’THEN
DIFF <= ‘1’ AFTER 10ns; BORROW <= ‘0’
AFTER 10ns;
ELSEIF A=‘1’AND B=‘1’ THEN
DIFF <= ‘0’ AFTER 10ns;
BORROW <= ‘0’ AFTER 10ns;

ENDIF;
END PROCESS; END BEHAVE_HS;

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 • Using Data Flow Architecture with selected
signal assignment:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_S IS
PORT (A, B: IN STD_LOGIC; DIFF, BORROW: OUT STD_LOGIC); END H_S;

ARCHITECTURE HS_DFSS OF H_S IS

BEGIN
HA_X <= A & B;
HA_Y <= BORROW & DIFF; WITH HA_X
SELECT
HA_Y <= “00” WHEN “00”,
“11” WHEN “01”,
“01” WHEN “10”,
“00” WHEN “11”;
END HS_DFSS;
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 Examples of VHDL Code
• Multiplexers in VHDL:
– Consider the 4:1 multiplexercircuit

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• Using CASE statement

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX IS
PORT( I3: IN STD_LOGIC_VECTOR(1 DOWNTO 0); I2: IN
STD_LOGIC_VECTOR(1 DOWNTO 0); I1: IN
STD_LOGIC_VECTOR(1 DOWNTO 0); I0: IN
STD_LOGIC_VECTOR(1 DOWNTO 0); S:IN
STD_LOGIC_VECTOR(1 DOWNTO 0); O:OUT
STD_LOGIC_VECTOR(1 DOWNTO 0));
END MUX;

ARCHITECTURE BEHV1 OF MUX IS

BEGIN
PROCESS(I3,I2,I1,I0,S) BEGIN
-- USE CASE STATEMENT CASE S IS
WHEN "00" => O <= I0; WHEN "01"
=> O <= I1; WHEN "10" => O <= I2;
WHEN "11" => O <=I3;
WHEN OTHERS => O <= "ZZ"; END CASE;
END PROCESS; END BEHV1;

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 Examples of VHDL Code
• Decoder in VHDL:
– Consider the 2:4 decodercircuit

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• Using Sequential Architecture model

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DECODER24 IS
PORT( A, B, EN:IN STD_LOGIC;
Z:OUT STD_LOGIC_VECTOR(0 TO 3));
END DECODER24;

ARCHITECTURE BEHV_DEC OF DECODER24 IS BEGIN

-- PROCESS STATEMENT

PROCESS (A, B, EN)

VARIABLE AB, BB: STD_LOGIC;
BEGIN
AB := NOTA; BB := NOT B;
IF EN = ‘1’ THEN
Z(3) <= NOT(A AND B); Z(2) <= NOT
(AB AND B); Z(1) <= NOT (A AND BB);
Z(0) <= NOT (AB AND BB);
ELSE
Z <= “1111”;
END IF;
END PROCESS;
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END
2024 BEHV_DEC;
 • Using CASE Statement
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DECODER24 IS
PORT( A, B, EN:INSTD_LOGIC;
Z:OUT STD_LOGIC_VECTOR(0 to 3));
END DECODER24;

ARCHITECTURE BEHV_DEC2 OF DECODER24 IS SIGNAL AB

: STD_LOGIC_VECTOR (1 DOWN TO 0); BEGIN
AB <= A & B; PROCESS (AB, EN)
BEGIN
IF EN = ‘1’THEN
CASE AB IS
WHEN "00" => Z <= “1110";
WHEN "01" => Z <= “1101“; WHEN OTHERS
=> Z <= “1011“;
END CASE; ELSE Z <= “1111";
END IF;
END PROCESS END
BEHV_DEC2;
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 • Using Selected signal Assignment Statement

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DECODER24 IS
PORT( A, B, EN:INSTD_LOGIC;
Z:OUT STD_LOGIC_VECTOR(0 TO 3)); END
DECODER24;

ARCHITECTURE BEHV_DEC2 OF DECODER24 IS SIGNAL

ENAB : STD_LOGIC_VECTOR (2 DOWN TO 0); BEGIN
ENAB <= EN & A & B; WITH
ENAB SELECT
Z <= “1110” WHEN “100”,
“1101” WHEN “101”,
“1011” WHEN “110”,
“0111” WHEN “111”;
“1111” WHEN OTHERS; END
BEHV_DEC2;

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 Examples of VHDL Code
• Priority Encoder in VHDL:
– Consider the Decimal to BCD Priority Encoder circuit

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 • Using Conditional Signal AssignmentStatement

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PRIORITY_ENCODER IS
PORT( I : IN STD_LOGIC_VECTOR(9 DOWN TO 0);
Y : OUT STD_LOGIC_VECTOR(3 DOWN TO 0) ); END
PRIORITY_ENCODER;

ARCHITECTURE BEHV_PE OF PRIORITY_ENCODER IS BEGIN

Y <= “0110” WHEN I(9) = ‘0’ELSE “0111”
WHEN I(8) = ‘0’ELSE
“1000” WHEN I(7) = ‘0’ELSE
“1001” WHEN I(6) = ‘0’ELSE
“1010” WHEN I(5) = ‘0’ELSE
“1011” WHEN I(4) = ‘0’ELSE
“1100” WHEN I(3) = ‘0’ELSE
“1101” WHEN I(2) = ‘0’ELSE
“1110” WHEN I(1) = ‘0’ELSE
“1111” END
BEHV_DEC2;

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 • Using Sequential Signal Statement
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PRIORITY_ENCODER IS
PORT( I : IN STD_LOGIC_VECTOR(9 DOWN TO0);
Y : OUT STD_LOGIC_VECTOR(3 DOWN TO 0) );
END PRIORITY_ENCODER;

ARCHITECTURE BEHV_PE2 OF PRIORITY_ENCODER IS

BEGIN
PROCESS(I)
BEGIN
IF I(9) = ‘0’ THEN Y <= ‘0110’;
ELSEIF I(8) = ‘0’ THEN Y <= ‘0111’;
ELSEIF I(7) = ‘0’ THEN Y <= ‘1000’;
ELSEIF I(6) = ‘0’ THEN Y <= ‘1001’;
ELSEIF I(5) = ‘0’ THEN Y <= ‘1010’;
ELSEIF I(4) = ‘0’ THEN Y <= ‘1011’;
ELSEIF I(3) = ‘0’ THEN Y <= ‘1100’;
ELSEIF I(2) = ‘0’ THEN Y <= ‘1101’;
ELSEIF I(1) = ‘0’ THEN Y <= ‘1110’;
ELSE Y <= ‘1111’
END IF; END
PROCESS;
END BEHV_DEC2;

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 Examples of VHDL Code
• Comparator in VHDL:

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 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COMPARATOR IS
PORT( A, B : IN STD_LOGIC_VECTOR(1 DOWN
TO 0); AGTB, AEQB, ALTBY : OUT
STD_LOGIC);
END COMPARATOR;

ARCHITECTURE BEHV OF COMPARATOR IS

BEGIN
AGTB <= ‘1’ WHEN A>B ELSE
‘0’; AEQB <= ‘1’ WHEN A=B
ELSE ‘0’; ALTB <= ‘1’ WHEN
A<B ELSE ‘0’;
END BEHV;

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 Examples of VHDL Code
• BCD to 7-Segment Decoder in VHDL:

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 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DEC_7_SEG IS
PORT( BCD : IN STD_LOGIC_VECTOR(3 DOWN TO 0);
LED7 : OUT STD_LOGIC_VECTOR(1 TO 7));
END DEC_7_SEG;

ARCHITECTURE BCDTO7SEG OF DEC_7_SEG IS

BEGIN
PROCESS(BCD)
BEGIN
CASE BCD IS
WHEN “0000” => LED7 <= “1111110”;
WHEN “0001” => LED7 <= “0110000”;
WHEN “0010” => LED7 <= “1101101”;
WHEN “0011” => LED7 <= “1111001”;
WHEN “0100” => LED7 <= “0110011”;
WHEN “0101” => LED7 <= “1011011”;
WHEN “0110” => LED7 <= “0011111”;
WHEN “0111” => LED7 <= “1110000”;
WHEN “1000” => LED7 <= “1111111”;
WHEN “1001” => LED7 <= “1110011”;
WHEN OTHERS => LED7 <= “-------”;
END CASE;
END PROCESS;
END BCDTO7SEG;

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